CN103776907A - Ultrasonic phased array received signal fine delaying method based on sinc interpolation - Google Patents

Abstract

The invention discloses an ultrasonic phased array received signal fine delaying method based on a sinc interpolation. In view of important influences on system performances by time delaying precision of an ultrasonic phased array received signal, the fine delaying method based on the sinc interpolation is provided on the basis of comprehensively considering the precision of signal delaying, processing speed, system optimization flexibility and the like. The ultrasonic phased array received signal fine delaying method combines the characteristic of a sinc function release signal and the advantages of a relatively small sidelobe and a relatively high attenuation speed of a Harming window to obtain an accurate interpolation coefficient. The strong real-time parallel processing capability and the strong storage capability of an FPGA (Field Programmable Gate Array) are utilized to rapidly and accurately carry out the sinc interpolation in a production line manner so as to finish the accurate delaying of any step length of a sampling signal. The ultrasonic phased array received signal fine delaying method based on the sinc interpolation has the high precision and the high processing efficiency, and can be used for obviously improving the time delaying precision of the ultrasonic phased array received signal and increasing the contrast ratio resolution ratio and the space resolution ratio of a detection system.

Description

Ultrasonic phase array based on sinc interpolation receives signal essence time-delay method

Technical field

The invention belongs to industrial ultrasonic non-destructive inspection techniques field, relate to a kind of ultrasonic phase array based on sinc interpolation and receive signal essence time-delay method.

Background technology

Ultrasonic phase array detection technique is a kind of advanced person's ultrasonic non-destructive inspection techniques, due to its significant advantage, is widely used in fields such as aviation, nuclear energy, machinery, electric power, petrochemical industry and railways, has created huge Social benefit and economic benefit.Ultrasonic phase array detection system is used array energy transducer, realize phase delay by the time delay of adjusting each array element transmitting/receiving signal, can control curvature, sensing, aperture of composite wave front etc., reach the multiple phased effects such as wave beam focusing, deflection, wave beam formation, form image clearly.Time-delay accuracy has determined phase delay precision, and contrast resolution and spatial resolution to detection system have material impact, is one of important indicator of measurement system.

The precision of digital delay is high, controls convenient, good stability, can greatly improve ultrasonic phased array imaging quality.The realization of digital delay can be divided into thick time delay and smart time delay, and thick time delay is counted based on sampling clock, implements fairly simplely, and precision can reach 10ns, and smart delay requirement can reach in 10ns, implements more difficult.Realize at present smart time delay and mainly contain two kinds of methods, a kind of is that each passage uses a special sampling clock sampling, and the phase place of these clocks staggers mutually, is worth poor for each channel delay.Increase to 32 passages even manyly when the autonomous channel of system, system cannot improve so multi-clock resource.Another kind is first the same clock of whole passages to be sampled, then the signal of each passage is carried out to interpolation increases counting of sampling, to improve the precision of smart time delay, is called signal restoring.Sinc interpolation is a kind of agonic signal restoring method, according to Shannon sampling thheorem, under the condition that meets sampling thheorem, any frequency limit signal can be realized Accurate Reconstruction by its discrete samples, and the smart time delay that therefore utilizes sinc interpolation to realize signal is a kind of effective method.But, sinc interpolation needs infinite summation, in the time of specific implementation, will carry out truncation, is conventionally limited in below 8, inevitably like this can produce some errors, as Gibbs effect.In order to reduce this impact, reply interpolation kernel is carried out windowing sharpening processing.

FPGA(field programmable gate arrays in recent years, FPGA) develop rapidly on speed and capacity makes it be widely used in high-speed digital signal process field, because ultrasound phase-control array 1 system has the features such as big data quantity, computing complexity, flow process be relatively fixing, therefore FPGA becomes the optimal selection that ultrasonic phase array system data is processed in real time.

Summary of the invention

The present invention is directed to the deficiencies in the prior art, provide a kind of ultrasonic phase array based on sinc interpolation to receive signal essence time-delay method.

The present invention can obtain the release signal of any time by sinc interpolation, realize the reception signal essence time delay of any step-length.Cause Gibbs phenomenon for fear of directly blocking sinc function, sinc function is carried out to windowing process, to obtain more accurate inhibit signal.Utilize the real-time parallel processing power that FPGA is powerful, carry out rapidly sinc interpolation with pipeline system, directly export original sampled signal essence time delay signal afterwards.The present invention can obviously improve ultrasonic phase array and receive the time-delay accuracy of signal, and has higher treatment effeciency, greatly improves contrast resolution and the spatial resolution of detection system.

Technical matters of the present invention is solved by following technical scheme:

Step 1: 8 sinc interpolation coefficients that main control computer needs according to reception signal lag accuracy computation 8 point interpolations that arrange, obtain 8 interpolation coefficients corresponding to each delay value in the sampling period.

Step 2: convert 8 corresponding each delay value interpolation coefficients to 32 floating numbers, be stored to respectively 8 dual port RAMs in FPGA.

Step 3: generate corresponding address of reading interpolation coefficient dual port RAM according to smart time delay.

Step 4: FPGA starts sampling, converts the valid data of input to 32 floating type data, and in 8 data cache registers, transmits successively storage with pipeline mode.

Step 5: take sampling clock as step, the data in current 8 data cache registers are multiplied each other with each self-corresponding interpolation coefficient respectively, to 8 product summations, flowing water is exported the data after a succession of interpolation.

Step 6: the data after interpolation are converted to the processing of integer as floating type, the signal after output time delay, completes the smart time delay of sampled input signal.

Beneficial effect of the present invention is mainly manifested in:

(1) utilize sinc function to there is the functional characteristics of release signal, and it is carried out to windowing process with Hanning window, obtain interpolation coefficient accurately.

(2) utilize FPGA processing capability in real time design fast sinc interpolating module, realize efficiently the smart time delay of signal.

(3) high-precision signal delay determines the phase delay of signal, can control more accurately the curvature, sensing, aperture of composite wave front etc., reaches the multiple phased effects such as wave beam focusing, deflection, wave beam formation, forms image more clearly.

(4) greatly improve contrast resolution and the spatial resolution of detection system.

Accompanying drawing explanation

Fig. 1 is that sinc interpolation realizes the operational flowchart that ultrasonic phase array reception signal essence postpones.

Fig. 2 is sinc function and adds Hanning window sinc function schematic diagram.

Fig. 3 is the MATLAB emulation schematic diagram that sinc interpolation realizes the time delay of ultrasonic phase array reception signal essence.

Fig. 4 is that sinc interpolation realizes the FPGA functional block diagram that ultrasonic phase array reception signal essence postpones.Embodiment

Below in conjunction with accompanying drawing, the invention will be further described.

As shown in Figure 1, the operating process that the present invention utilizes sinc interpolation to realize the time delay of ultrasonic phase array reception signal essence can be divided into following step:

Step 1: 8 sinc interpolation coefficients that main control computer needs according to reception signal lag accuracy computation 8 point interpolations that arrange, obtain 8 interpolation coefficients corresponding to each delay value in the sampling period.

Step 2: convert 8 corresponding each delay value interpolation coefficients to 32 floating numbers, be stored to respectively 8 dual port RAMs in FPGA.

Step 3: generate corresponding address of reading interpolation coefficient dual port RAM according to smart time delay.

Step 4: FPGA starts sampling, converts the valid data of input to 32 floating type data, and in 8 data cache registers, transmits successively storage with pipeline mode.

Step 5: take sampling clock as step, the data in current 8 data cache registers are multiplied each other with each self-corresponding interpolation coefficient respectively, to 8 product summations, flowing water is exported the data after a succession of interpolation.

Step 6: the data after interpolation are converted to the processing of integer as floating type, the signal after output time delay, completes the smart time delay of sampled input signal.

8 interpolation coefficients corresponding to each delay value in a kind of described calculating sampling cycle of step, by sinc function windowing block and obtain.The essence that ultrasonic phase array receives smart time delay is to realize the interpolation of signal by the method for digital signal processing, and this process can realize with an ideal low-pass filter, and sinc function is regarded ideal low-pass filter always, and its interpolation formula is

$\hat{x}\left(t\right)=\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}x\left(\mathrm{nT}\right)\frac{\sin [\mathrm{\π}(t-\mathrm{nT})/T]}{\mathrm{\π}(t-\mathrm{nT})/T}=\underset{n=-\∞}{\overset{+\∞}{\mathrm{\Σ}}}x\left(\mathrm{nT}\right)\sin c(t/T-n)$

In formula, for the signal after postponing, t is time delay, x (nT) is original sampled signal, n is sampled point sequence number, T is the sampling period, sinc function expression be sinc (t)=sin (π t)/π t, can see, the sinc interpolation that realizes some points needs infinite summation, and this is infeasible in actual use.In fact, signal is postponed just need to draw after original signal to signal value sometime, do not need complete restoring signal, can block to carry out interpolation to sinc function finite length, each interpolation point only uses the information of contiguous several points, general 8 point interpolations that use, centered by the complete cycle of interpolation point point, select its first three put and four points thereafter.Therefore, the formula of sinc interpolation becomes

$\hat{x}\left(t\right)==\underset{m=-3}{\overset{4}{\mathrm{\Σ}}}x\left(\mathrm{nT}\right)\sin c(t/T-n)$

But when using the sinc function that directly blocks when existing the signal of brink to carry out interpolation, there will be a kind of ringing of the Gibbs of being called effect.In order to reduce the impact of Gibbs effect, need to be to the windowing process of sinc function.Because Hanning window has less secondary lobe and the larger rate of decay, therefore sinc function is added to Hanning window processing, calculate corresponding 8 interpolation coefficients according to delay value.Fig. 2 is sinc function and adds the schematic diagram of Hanning window sinc function, can make secondary lobe decay fast after sinc function is added to Hanning window, reduces the leakage of energy, thereby reduces the impact of Gibbs effect.Fig. 3 is the MATLAB emulation schematic diagram that sinc interpolation realizes the time delay of ultrasonic phase array reception signal essence, input signal is that frequency is the True Data of the sampling clock collection of 100MHz, utilize sinc interpolation algorithm in MATLAB software, to carry out smart time delay simulation, sampled signal is carried out respectively to the smart time delay simulation of 3ns and 8ns, the simulated effect obtaining is very good.

Described in step 2, interpolation coefficient is converted to 32 floating numbers, be stored to respectively 8 dual port RAMs in FPGA.Fig. 4 is that sinc interpolation realizes the FPGA functional block diagram that ultrasonic phase array reception signal essence postpones.Because interpolation coefficient is the decimal that is less than 1, in FPGA, can not store the data of fractional format, therefore all convert interpolation coefficient to 32 floating numbers, can directly be stored to FPGA, can keep again precision.The degree of depth of 8 dual port RAMs in FPGA is 100, can use according to delay precision the space of part or all of dual port RAM, and delay precision is the highest can reach 1/100 of the sampling period.

Described in step 3, generate corresponding address of reading interpolation coefficient dual port RAM according to smart time delay, essence time delay is divided by the delay precision arranging, business's processing that rounds up, is the memory address of interpolation coefficient under this time delay, reads 8 interpolation coefficients in dual port RAM simultaneously.

Described in step 4, the valid data of input are converted to 32 floating type data, and with pipeline mode successively 8 data cache register transmission storages.Because interpolation coefficient is 32 floating types, for operative data type is unified, will input data-switching and become 32 floating types.Sampled data is according to sequencing, with pipeline mode successively 8 data cache register transmission storages.

Input data described in step 5 interpolation coefficient respectively and separately multiplies each other and the summation that adds up, and flowing water is exported the data after a succession of interpolation.According to the formula of 8 sinc interpolation, the interpolated data that calculates certain certain time of data delay needs 3 data and below 4 data above, totally 8 data respectively with interpolation coefficient phase multiply accumulating, due to input data be in 8 data cache registers with pipeline mode transmission storage, therefore the data after interpolation are continuous wave outputs.Should be noted that, several interpolation points that sampling starts are likely got less than three whole points before it, now by get less than the whole zero setting of data point.Last several interpolation point is got less than four whole thereafter points, now also will by get less than all zero setting of data.

The processing that the data after interpolation is converted to integer as floating type described in step 6, the signal after output time delay, completes the smart time delay of sampled input signal.Because the interpolated data after phase multiply accumulating is floating type, for the needs of subsequent treatment, convert interpolated data to integer, output signal, has completed the smart time delay that receives signal.

Claims (2)

1. the ultrasonic phase array based on sinc interpolation receives signal essence time-delay method, and its feature comprises the following steps in the method:

Step 1: 8 sinc interpolation coefficients that main control computer needs according to reception signal lag accuracy computation 8 point interpolations that arrange, obtain 8 interpolation coefficients corresponding to each delay value in the sampling period;

Step 2: convert 8 corresponding each delay value interpolation coefficients to 32 floating numbers, be stored to respectively 8 dual port RAMs in FPGA;

Step 3: generate corresponding address of reading interpolation coefficient dual port RAM according to smart time delay;

Step 4: FPGA starts sampling, converts the valid data of input to 32 floating type data, and in 8 data cache registers, transmits successively storage with pipeline mode;

Step 5: take sampling clock as step, the data in current 8 data cache registers are multiplied each other with each self-corresponding interpolation coefficient respectively, to 8 product summations, flowing water is exported the data after a succession of interpolation;

Step 6: the data after interpolation are converted to the processing of integer as floating type, the signal after output time delay, completes the smart time delay of sampled input signal.

2. the ultrasonic phase array based on sinc interpolation according to claim 1 receives signal essence time-delay method, it is characterized in that:

8 interpolation coefficients corresponding to each delay value in sampling period described in step 1, by sinc function windowing block and obtain.

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