CN109597777A - A kind of MCBSP interface inter-link device and method based on FPGA - Google Patents
A kind of MCBSP interface inter-link device and method based on FPGA Download PDFInfo
- Publication number
- CN109597777A CN109597777A CN201811511599.XA CN201811511599A CN109597777A CN 109597777 A CN109597777 A CN 109597777A CN 201811511599 A CN201811511599 A CN 201811511599A CN 109597777 A CN109597777 A CN 109597777A
- Authority
- CN
- China
- Prior art keywords
- data
- message
- fpga
- mcbsp
- mcbsp interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention discloses a kind of MCBSP interface inter-link device and method based on FPGA, belongs to technical field of data transmission.MCBSP interface inter-link device based on FPGA of the invention includes several chips, MCBSP interface sending module, message analysis module and arbitration Switching Module, the MCBSP interface sending module, message analysis module and arbitration Switching Module are separately positioned on FPGA, MCBSP interface sending module, message analysis module, arbitration Switching Module are sequentially connected with, wherein several chips are connected with MCBSP interface sending module respectively.The MCBSP interface inter-link device data transmission bauds based on FPGA of the invention is fast, and priority is configurable and flexible online, has good application value.
Description
Technical field
The present invention relates to technical field of data transmission, specifically provide a kind of MCBSP interface inter-link device based on FPGA and
Method.
Background technique
FPGA (Field Programmable Gate Array) i.e. field programmable gate array, it be PAL, GAL,
The product further developed on the basis of the programming devices such as CPLD.It is as one in the field specific integrated circuit (ASIC)
It plants semi-custom circuit and occurs, not only solved the deficiency of custom circuit, but also overcome original programming device gate circuit number to have
The shortcomings that limit.The exploitation of FPGA is very different relative to the exploitation of traditional PC, single-chip microcontroller.FPGA based on concurrent operation, with
Hardware description language is realized；It is operated compared to the sequence of PC or single-chip microcontroller (either von Neumann structure or Harvard structure)
There is very big difference, it is more difficult to also result in FPGA exploitation introduction.There are the FPGA external coordination exploitation producer of profession, such as [Beijing in the country at present
Middle section's ancient cooking vessel bridge ZKDQ-TECH] etc..FPGA exploitation needs more from Top-layer Design Method, module layering, logic realization, hardware and software debugging etc.
Aspect is set about.FPGA has very high flexibility simultaneously, there is I/O pin abundant, reliability short relative to the ASIC development cycle
It is high.
MCBSP is the multichannel buffer serial port of the digital signal processing chip of TI company production, is connect in standard serial
Function is extended on the basis of mouth, it can be communicated with other serial ports devices such as other DSP device, encoders.MCBSP
Including a data channel and a control channel, it is connect by 7 pins with external equipment.Data send pin DX and are responsible for number
According to transmission, data receiver pin DR is responsible for the reception of data, and tranmitting data register pin CLKX receives clock pins CLKR, sends
Frame synchronization pin FSX and reception frame synchronization pin FSR provide serial clock and control signal.
At present in field of data transmission, generally existing data transmission bauds is slow, and the online configurability of priority is smaller, and
The not high enough disadvantage of flexibility ratio, is further improved.
Summary of the invention
Technical assignment of the invention is in view of the above problems, to provide that a kind of data transmission bauds is fast, and priority exists
Line can configure and the flexible high MCBSP interface inter-link device based on FPGA.
The further technical assignment of the present invention is to provide a kind of MCBSP interface inter-link method based on FPGA.
To achieve the above object, the present invention provides the following technical scheme that
A kind of MCBSP interface inter-link device based on FPGA, including several chips, MCBSP interface sending module, report
Literary analysis module and arbitration Switching Module, the MCBSP interface sending module, message analysis module and arbitration Switching Module
It being separately positioned on FPGA, MCBSP interface sending module, message analysis module, arbitration Switching Module are sequentially connected with, wherein
Several chips are connected with MCBSP interface sending module respectively.
Preferably, the MCBSP interface sending module simulates the reading of MCBSP according to the interface sequence of MCBSP
Write control.
Preferably, several chips send data to MCBSP interface sending module, wherein to MCBSP interface
Receiving the data format that sending module is sent is heading+data+message trailer.
Preferably, the heading includes header indicatingjhe number, source ID, purpose ID and the priority of data.
Preferably, the message trailer includes the tail portion indication signal and CRC of data.
The message analysis module analyzes message, first by the CRC of source ID, purpose ID and message trailer in message
It extracts, analyzes the CRC of message trailer then to determine the correctness of message, so that it is determined that the data that each chip is sent are just
True property.Arbitration Switching Module according to inside message priority and source ID message is arbitrated, according to source ID and purpose ID
To determine the forward-path of data.
Chip of the MCBSP interface sending module for FPGA and muti-piece with MCBSP interface carries out data
It sending and receiving, the data needs for passing in and out FPGA are sent and received according to heading+data+message trailer format,
Middle header includes header indicatingjhe number, source ID, purpose ID and priority, and message trailer includes tail portion indication signal and CRC.Report
Literary analysis module can analyze the message received, extract information required for arbitration Switching Module.Arbitrate interchange mode
Block can select the forward-path of message according to the combination of source ID and purpose ID, if data will be sent to from different source ID
Identical purpose ID can then determine that message is sent successive according to the priority of message, if the priority of message is identical,
See the size of source ID, ID small preferential carry out data transmission.
In the MCBSP interface inter-link device use process based on FPGA, data are respectively sent to MCBSP by several chips
Interface sending module, MCBSP interface sending module send data to message analysis module, message analysis module from
The message parameter of data is extracted in data, and judges the correctness for the data that each chip is sent according to message parameter, if having
Mistake then informs corresponding chip retransmission data, and otherwise message analysis module sends data to arbitration Switching Module, arbitration exchange
Module handles data according to the message parameter of data and selects the forward-path of data.Wherein, in arbitration Switching Module
When handling message, the message that other chips are sent, which can be buffered in, waits the Message processing arrived first to finish in FIFO, if there is difference
The message that the chip of source ID is sent reaches simultaneously, then the report preferentially forwarded is determined according to the priority in message analysis module
Text determines the message of priority processing if priority is identical according to the numerical values recited of the source ID of message, other messages are all at this time
It is buffered in FIFO, upper message forwarding is waited to complete.
A kind of MCBSP interface inter-link method based on FPGA, in this method, data are respectively sent to by several chips
MCBSP interface sending module, MCBSP interface sending module send data to message analysis module, message analysis
Module extracts the message parameter of data from data, and judges the correct of the data that each chip is sent according to message parameter
Property, corresponding chip retransmission data is informed if wrong, otherwise message analysis module sends data to arbitration Switching Module, secondary
Switching Module is cut out to handle data according to the message parameter of data and select the forward-path of data.
The MCBSP interface inter-link method based on FPGA based on the MCBSP interface inter-link device of FPGA by being realized.Institute
Stating the MCBSP interface inter-link device based on FPGA includes several chips, MCBSP interface sending module, message analysis module
With arbitration Switching Module, the MCBSP interface sending module, message analysis module and arbitration Switching Module are separately positioned on
On FPGA, MCBSP interface sending module, message analysis module, arbitration Switching Module are sequentially connected with, wherein several chips point
It is not connected with MCBSP interface sending module.
Preferably, the data format that several chips are sent is heading+data+message trailer, wherein heading packet
Header indicatingjhe number, source ID, purpose ID and priority containing data, message trailer include the tail portion indication signal and CRC of data.
Preferably, the message analysis module judges the correctness of data by calculating the CRC of message trailer.
Preferably, the message parameter for the data that the message analysis module is extracted include message source ID, purpose ID and
Priority.
Preferably, the arbitration Switching Module is handled the data of multiple chips according to arriving first the principle first handled
And it forwards；If have the data of the chip transmission of not homologous ID while reaching, handled according to data priority and being forwarded；If
Priority is identical, is handled and is forwarded according to the size of data of the source ID of data, and source ID is small preferentially to be handled and turned
Hair.
When arbitrating Switching Module processing message, the message that other chips are sent can be buffered in the report for waiting and arriving first in FIFO
Text is disposed, if there is the message that the chip of not homologous ID is sent reaches simultaneously, then according to preferential in message analysis module
Grade determines the message preferentially forwarded, if priority is identical determines priority processing according to the numerical values recited of the source ID of message
Message, other messages are all buffered in FIFO at this time, and upper message forwarding is waited to complete.
Compared with prior art, the MCBSP interface inter-link method of the invention based on FPGA has following prominent beneficial
Effect: some data sharings and interconnection of each chip chamber may be implemented in the MCBSP interface inter-link method based on FPGA, also
So that the system has higher flexibility and better performance, while being somebody's turn to do the MCBSP interface inter-link method based on FPGA also
Feature fast with data transmission bauds, that priority can configure online and flexibility ratio is high, has good application value.
Detailed description of the invention
Fig. 1 is the topological diagram of the MCBSP interface inter-link device of the present invention based on FPGA.
Specific embodiment
Below in conjunction with drawings and examples, the MCBSP interface inter-link device and method of the invention based on FPGA is made
It is further described.
Embodiment
As shown in Figure 1, the MCBSP interface inter-link device of the invention based on FPGA, including several chips, MCBSP interface
Receive sending module, message analysis module and arbitration Switching Module.
MCBSP interface sending module, message analysis module and arbitration Switching Module are separately positioned on FPGA,
MCBSP interface sending module, message analysis module, arbitration Switching Module be sequentially connected with, wherein several chips respectively with
MCBSP interface sending module is connected.
MCBSP interface sending module simulates the Read-write Catrol of MCBSP according to the interface sequence of MCBSP.
Several chips send data to MCBSP interface sending module, wherein sending out to MCBSP interface sending module
The data format sent is heading+data+message trailer.Heading includes the header indicatingjhes number of data, source ID, purpose ID and excellent
First grade, message trailer include the tail portion indication signal and CRC of data.
Message analysis module analyzes message, first extracts the CRC of source ID, purpose ID and message trailer in message
Out, the CRC of message trailer is analyzed then to determine the correctness of message, so that it is determined that the data that each chip is sent is correct
Property.Arbitration Switching Module according to inside message priority and source ID message is arbitrated, according to source ID and purpose ID come
Determine the forward-path of data.
Chip of the MCBSP interface sending module for FPGA and muti-piece with MCBSP interface carries out the transmission of data
And reception, the data needs for passing in and out FPGA are sent and received according to heading+data+message trailer format, wherein reporting
Literary head includes header indicatingjhe number, source ID, purpose ID and priority, and message trailer includes tail portion indication signal and CRC.Message point
Analysis module can analyze the message received, extract information required for arbitration Switching Module.Arbitrate Switching Module meeting
The forward-path of message is selected according to the combination of source ID and purpose ID, if data to be sent to from different source ID it is identical
Purpose ID, then can be determined according to the priority of message message send it is successive, if the priority of message is identical, see source
The size of ID, ID small preferential carry out data transmission.Wherein, when arbitrating Switching Module processing message, what other chips were sent
Message, which can be buffered in, waits the Message processing arrived first to finish in FIFO, if there is the message that the chip of not homologous ID is sent arrives simultaneously
It reaches, then determines the message preferentially forwarded according to the priority in message analysis module, according to message if priority is identical
The numerical values recited of source ID determines the message of priority processing, other messages are all buffered in FIFO at this time, wait a upper message
Forwarding is completed.
Data are respectively sent to MCBSP interface by the MCBSP interface inter-link method based on FPGA of the invention, several chips
Sending module is received, MCBSP interface sending module sends data to message analysis module, and message analysis module is from data
In extract the message parameters of data, and the correctness for the data that each chip is sent is judged according to message parameter, if wrong
Inform corresponding chip retransmission data, otherwise message analysis module sends data to arbitration Switching Module, arbitrates Switching Module
According to the message parameter of data data are handled and are selected with the forward-path of data.
The MCBSP interface inter-link method based on FPGA based on the MCBSP interface inter-link device of FPGA by being realized.Institute
Stating the MCBSP interface inter-link device based on FPGA includes several chips, MCBSP interface sending module, message analysis module
With arbitration Switching Module, the MCBSP interface sending module, message analysis module and arbitration Switching Module are separately positioned on
On FPGA, MCBSP interface sending module, message analysis module, arbitration Switching Module are sequentially connected with, wherein several chips point
It is not connected with MCBSP interface sending module.The data format that several chips are sent is heading+data+message trailer,
Middle heading includes header indicatingjhe number, source ID, purpose ID and the priority of data, and message trailer includes that the tail portion of data indicates letter
Number and CRC.Message analysis module judges the correctness of data by calculating the CRC of message trailer.What message analysis module was extracted
The message parameter of data includes the source ID, purpose ID and priority of message.Arbitration Switching Module is according to arriving first the principle first handled
The data of multiple chips are handled and forwarded；If have the data of the chip transmission of not homologous ID while reaching, according to number
It is handled and is forwarded according to priority；It is handled and is forwarded according to the size of data of the source ID of data if priority is identical,
Source ID is small preferentially to be handled and is forwarded.When arbitrating Switching Module processing message, the message that other chips are sent can be cached
The Message processing arrived first is waited to finish in FIFO, if there is the message that the chip of not homologous ID is sent reaches simultaneously, then basis
Priority in message analysis module determines the message preferentially forwarded, according to the numerical value of the source ID of message if priority is identical
Size determines the message of priority processing, other messages are all buffered in FIFO at this time, upper message forwarding is waited to complete.
Embodiment described above, the only present invention more preferably specific embodiment, those skilled in the art is at this
The usual variations and alternatives carried out within the scope of inventive technique scheme should be all included within the scope of the present invention.
Claims (10)
1. a kind of MCBSP interface inter-link device based on FPGA, it is characterised in that: sent out including several chips, MCBSP interface
Send module, message analysis module and arbitration Switching Module, the MCBSP interface sending module, message analysis module and secondary
It cuts out Switching Module to be separately positioned on FPGA, MCBSP interface sending module, message analysis module, arbitration Switching Module are suitable
Secondary connection, wherein several chips are connected with MCBSP interface sending module respectively.
2. the MCBSP interface inter-link device according to claim 1 based on FPGA, it is characterised in that: the MCBSP interface
Receive the Read-write Catrol that sending module simulates MCBSP according to the interface sequence of MCBSP.
3. the MCBSP interface inter-link device according to claim 1 or 2 based on FPGA, it is characterised in that: several cores
Piece sends data to MCBSP interface sending module, wherein being to the data format that MCBSP interface sending module is sent
Heading+data+message trailer.
4. the MCBSP interface inter-link device according to claim 3 based on FPGA, it is characterised in that: the heading packet
Header indicatingjhe number, source ID, purpose ID and priority containing data.
5. the MCBSP interface inter-link device according to claim 4 based on FPGA, it is characterised in that: the message trailer packet
Tail portion indication signal and CRC containing data.
6. a kind of MCBSP interface inter-link method based on FPGA, it is characterised in that: in this method, several chips distinguish data
It is sent to MCBSP interface sending module, MCBSP interface sending module sends data to message analysis module, report
Literary analysis module extracts the message parameter of data from data, and judges the data that each chip is sent according to message parameter
Correctness informs corresponding chip retransmission data if wrong, and otherwise message analysis module sends data to arbitration interchange mode
Block, arbitration Switching Module handle data according to the message parameter of data and select the forward-path of data.
7. the MCBSP interface inter-link method according to claim 6 based on FPGA, it is characterised in that: several chips
The data format of transmission is heading+data+message trailer, and wherein heading includes the header indicatingjhe number of data, source ID, purpose
ID and priority, message trailer include the tail portion indication signal and CRC of data.
8. the MCBSP interface inter-link method according to claim 6 or 7 based on FPGA, it is characterised in that: the message point
Analysis module judges the correctness of data by calculating the CRC of message trailer.
9. the MCBSP interface inter-link method according to claim 8 based on FPGA, it is characterised in that: the message analysis
The message parameter for the data that module is extracted includes the source ID, purpose ID and priority of message.
10. the MCBSP interface inter-link method according to claim 9 based on FPGA, it is characterised in that: the arbitration exchange
Module is handled and is forwarded to the data of multiple chips according to arriving first the principle first handled；If there is the chip of not homologous ID to send
Data reach simultaneously, then handled and forwarded according to data priority；According to the source ID's of data if priority is identical
Size of data is handled and is forwarded, and source ID is small preferentially to be handled and forwarded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811511599.XA CN109597777A (en) | 2018-12-11 | 2018-12-11 | A kind of MCBSP interface inter-link device and method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811511599.XA CN109597777A (en) | 2018-12-11 | 2018-12-11 | A kind of MCBSP interface inter-link device and method based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109597777A true CN109597777A (en) | 2019-04-09 |
Family
ID=65961783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811511599.XA Pending CN109597777A (en) | 2018-12-11 | 2018-12-11 | A kind of MCBSP interface inter-link device and method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109597777A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110059045A (en) * | 2019-04-22 | 2019-07-26 | 仓领电子科技(上海)有限公司 | A kind of no-dig technique sensing device bus sharing system based on FPGA, method and device |
| CN110113265A (en) * | 2019-05-16 | 2019-08-09 | 济南浪潮高新科技投资发展有限公司 | More I2C interface interconnected methods and module based on FPGA |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1677947A (en) * | 2004-03-31 | 2005-10-05 | 华为技术有限公司 | Apparatus and method for realizing inter-communication between digital signal processors |
| CN101609544A (en) * | 2009-07-21 | 2009-12-23 | 华中科技大学 | A kind of image processor data load and method of testing and device |
| CN101651828A (en) * | 2009-09-07 | 2010-02-17 | 哈尔滨工程大学科技园发展有限公司 | Radar image collection card based on DSP and FPGA |
| CN101741722A (en) * | 2009-12-10 | 2010-06-16 | 中兴通讯股份有限公司 | Data interactive method and device |
| CN101887382A (en) * | 2010-06-28 | 2010-11-17 | 中兴通讯股份有限公司 | Method and device for arbitrating dynamic priority |
| CN102368696A (en) * | 2011-09-14 | 2012-03-07 | 杭州华三通信技术有限公司 | Method for selecting synchronous clock source and apparatus thereof |
| CN103530245A (en) * | 2013-10-31 | 2014-01-22 | 武汉邮电科学研究院 | SRIO interconnection exchanging device based on field programmable gate array (FPGA) |
| US20140067083A1 (en) * | 2012-08-31 | 2014-03-06 | The Johns Hopkins University | Control System for Prosthetic Limb |
| CN104572529A (en) * | 2015-02-09 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | Efficient bus arbitration system applicable to heterogeneous multi-core DSP |
| CN105553883A (en) * | 2014-10-28 | 2016-05-04 | 江苏绿扬电子仪器集团有限公司 | Multi-DSP data exchange apparatus based on FPGA |
| CN106850373A (en) * | 2017-02-24 | 2017-06-13 | 宁波工程学院 | Towards the non-demolition formula dynamically optimized scheduling method of CAN |
| CN107621819A (en) * | 2017-08-24 | 2018-01-23 | 电子科技大学 | A kind of FPGA configuration file online updating device of three-dimensional acoustic wave logging instrument |
-
2018
- 2018-12-11 CN CN201811511599.XA patent/CN109597777A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1677947A (en) * | 2004-03-31 | 2005-10-05 | 华为技术有限公司 | Apparatus and method for realizing inter-communication between digital signal processors |
| CN101609544A (en) * | 2009-07-21 | 2009-12-23 | 华中科技大学 | A kind of image processor data load and method of testing and device |
| CN101651828A (en) * | 2009-09-07 | 2010-02-17 | 哈尔滨工程大学科技园发展有限公司 | Radar image collection card based on DSP and FPGA |
| CN101741722A (en) * | 2009-12-10 | 2010-06-16 | 中兴通讯股份有限公司 | Data interactive method and device |
| CN101887382A (en) * | 2010-06-28 | 2010-11-17 | 中兴通讯股份有限公司 | Method and device for arbitrating dynamic priority |
| CN102368696A (en) * | 2011-09-14 | 2012-03-07 | 杭州华三通信技术有限公司 | Method for selecting synchronous clock source and apparatus thereof |
| US20140067083A1 (en) * | 2012-08-31 | 2014-03-06 | The Johns Hopkins University | Control System for Prosthetic Limb |
| CN103530245A (en) * | 2013-10-31 | 2014-01-22 | 武汉邮电科学研究院 | SRIO interconnection exchanging device based on field programmable gate array (FPGA) |
| CN105553883A (en) * | 2014-10-28 | 2016-05-04 | 江苏绿扬电子仪器集团有限公司 | Multi-DSP data exchange apparatus based on FPGA |
| CN104572529A (en) * | 2015-02-09 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | Efficient bus arbitration system applicable to heterogeneous multi-core DSP |
| CN106850373A (en) * | 2017-02-24 | 2017-06-13 | 宁波工程学院 | Towards the non-demolition formula dynamically optimized scheduling method of CAN |
| CN107621819A (en) * | 2017-08-24 | 2018-01-23 | 电子科技大学 | A kind of FPGA configuration file online updating device of three-dimensional acoustic wave logging instrument |
Non-Patent Citations (1)
| Title |
|---|
| 孙利刚: ""机间数据链设计与仿真"", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110059045A (en) * | 2019-04-22 | 2019-07-26 | 仓领电子科技(上海)有限公司 | A kind of no-dig technique sensing device bus sharing system based on FPGA, method and device |
| CN110059045B (en) * | 2019-04-22 | 2024-04-12 | 吴进国 | FPGA-based bus sharing system, method and device for non-excavation sensing device |
| CN110113265A (en) * | 2019-05-16 | 2019-08-09 | 济南浪潮高新科技投资发展有限公司 | More I2C interface interconnected methods and module based on FPGA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106612141B (en) | A kind of fiber channel protocol common simulation test card and its data interactive method | |
| CN106411740B (en) | Network port extended method based on ethernet controller | |
| CN109597777A (en) | A kind of MCBSP interface inter-link device and method based on FPGA | |
| CN103995764B (en) | A kind of logic analyser with serial bus protocol continuous trigger function | |
| CN207718364U (en) | A kind of multichannel RS-422 serial ports expansion interfaces based on FPGA | |
| CN102438010B (en) | For the method and apparatus of streaming data profiling | |
| CN102223452B (en) | The TTY method of testing of mobile terminal and system | |
| CN103823785B (en) | Multi-way ARINC429 data transmit-receive circuit structure based on development of DSP and CPLD | |
| CN110493079A (en) | The production automation test method of industrial ethernet switch | |
| CN110334046A (en) | A kind of communication means, the apparatus and system of SPI full duplex | |
| CN101169771A (en) | Multiple passage internal bus external interface device and its data transmission method | |
| CN103955419A (en) | Logic analyzer with serial bus protocol on-line real-time detection analysis function | |
| CN104536924A (en) | Multi-channel delay deviation correction method and device for board-level high-speed transmission bus | |
| CN105720986B (en) | Multi-path data acquiring system with unified time mark | |
| CN109656856A (en) | Multiplex bus and multiplex bus interconnect device and method are realized using FPGA | |
| CN100410887C (en) | Structuring method of distributed type simulated testing system series based on signal classification | |
| CN106650128B (en) | A kind of method of graphic software platform timing topology and timing dependence | |
| CN109407574A (en) | Output-controlling device and its method may be selected in a kind of multibus | |
| CN206431607U (en) | A kind of LCD drive circuit systems | |
| CN103916336B (en) | Ethernet driver realized by FPGA | |
| CN108107351A (en) | Adjustment method, debugger and the system of JTAG debuggers | |
| CN109960674A (en) | A kind of USB interface interconnected method and system based on FPGA | |
| CN107301143A (en) | A kind of asynchronous arbiter based on the phase Handshake Protocol of coding and double track four | |
| Laddha et al. | Implementation of serial communication using UART with configurable baud rate | |
| CN110113265A (en) | More I2C interface interconnected methods and module based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190409 |
|
| RJ01 | Rejection of invention patent application after publication |