CN1677947A - Apparatus and method for realizing inter-communication between digital signal processors - Google Patents
Apparatus and method for realizing inter-communication between digital signal processors Download PDFInfo
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- CN1677947A CN1677947A CNA2004100307073A CN200410030707A CN1677947A CN 1677947 A CN1677947 A CN 1677947A CN A2004100307073 A CNA2004100307073 A CN A2004100307073A CN 200410030707 A CN200410030707 A CN 200410030707A CN 1677947 A CN1677947 A CN 1677947A
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Abstract
The device comprises exchange network slice module and digital signal processor (DSP) module. The invention also discloses corresponding method. The invention divides clock pulse cycle supplied from external into time slots corresponded to each DSP in DSP module. In time slot corresponding to second DSP, the exchange network slice module receives second DSP data sent from first DSP. In time slot corresponding to first DSP, the exchange network slice module sends the said data to second DSP. Based on received data, the second DSP ensures that it is first DSP to communicate with. The disclosed device and method decreases occupied CPU resources, and raises communication rate between DSPs.
Description
Technical field
The present invention relates to Digital Signal Processing, particularly relate to mutual communicating devices and method between a kind of realization digital signal processor.
Background technology
Digital signal processor (DSP) is a kind of being suitable for to carry out the microprocessor that real time digital signal is handled computing, and it is mainly used is to realize various digital signal processing algorithms real-time.The advantage of DSP is: strong, the high arithmetic speed of data-handling capacity, to finish complicated calculations, monocycle multiple instruction function, pulse-width modulation (PWM, Pulse-Width Modulation) resolution height, sampling period in real time short etc.Therefore, under current digital times background, DSP has obtained using widely in a lot of science and engineering field, and becomes the basic device in fields such as communication, computer, consumer electronics product.
In order to improve the handling property of system, need on a veneer, use multi-disc DSP to satisfy the lot of data processing demands sometimes, therefore, with regard to the problem of intercommunication that a plurality of DSP occurred.
Connection diagram when Fig. 1 is the intercommunication of DSP in the prior art.As shown in Figure 1, in order to realize the intercommunication mutually between the DSP, prior art links to each other all DSP that use on the veneer with a slice central processing unit (CPU), the communication data between the DSP is all transmitted by CPU, and each DSP and CPU form star topology on data flow direction.
Fig. 2 is the encapsulation format schematic diagram that DSP becomes the message bag in the prior art with the transmission data encapsulation between the CPU, and Fig. 3 is the flow chart of the intercommunication of existing techniques in realizing DSP.As shown in Figures 2 and 3, the detailed process of the intercommunication of existing techniques in realizing DSP may further comprise the steps:
Step 301:DSP is packaged into the message bag with its communication data after receiving the Data Receiving order that CPU sends, and the message bag is divided into message header and message body two parts.Wherein, message header comprises that message header sign (Flag), source CPU sign (Src CPUID), purpose CPU identify (Dest CPUID), message packet length (Length) and message bag type (Type).And Src CPUID represents the source DSP numbering of transmission packet, and Dest CPUID represents the purpose DSP numbering that the message bag should send to.Message body is the communication data of DSP.
Message bag after step 302:DSP will encapsulate sends to CPU.
Step 303:CPU sends to purpose DSP with this message bag then according to the purpose DSP that Dest CPUID in the message header of this message bag determines this message bag.
After step 304: purpose DSP obtains the message bag, determine to send the source DSP of this message bag according to the Src CPUID in the message header.
As seen, there is following shortcoming in prior art:
1, the data of the intercommunication of each DSP must be transmitted by CPU, and therefore the disposal ability to CPU has proposed higher requirement.
2, more when the DSP number, and when the flow of communication data is big between DSP, can take a large amount of cpu resources.
3, CPU must rely on the executive software instruction to finish the work that receives and transmit communication data between the DSP, therefore, has increased the path delay of time that data send, and greatly reduces the traffic rate between the DSP, has influenced the performance of system.
Summary of the invention
In view of this, the object of the present invention is to provide mutual method for communicating between a kind of realization digital signal processor, make its resource that can less take CPU, and improve the traffic rate between the DSP.
Another object of the present invention is to provide mutual communicating devices between a kind of realization digital signal processor, make the data forwarding work of CPU between DSP to discharge, and the traffic rate between the raising DSP.
In order to achieve the above object, technical scheme of the present invention is achieved in that
Mutual method for communicating is applied to more than in the system that communicates between one the digital signal processor DSP between a kind of realization digital signal processor, and this method comprises:
The switching net module is set, will be divided into several slots each clock cycle, a DSP sends data at a time slot to the switching net module, and the switching net module sends to the 2nd DSP at subsequent timeslot with these data.
To be divided into some time slots unit described clock cycle, comprise in each time slot unit equate with the DSP number and respectively with the corresponding different time-gap of each DSP;
A described DSP sends data with the 2nd DSP time slot corresponding to the switching net module in a time slot unit;
Described switching net module sends to the 2nd DSP with a DSP time slot corresponding with these data in the subsequent timeslot unit.
This method further comprises: the memory block that each DSP of storage sends data is set in the switching net module, and each memory block is divided into the storage subarea corresponding with each time slot;
Described switching net module receives the data that a DSP sends with the 2nd DSP time slot corresponding in a described time slot unit after, directly these data are kept at storage the one DSP send in the memory block of data with the pairing storage of the corresponding time slot of the 2nd DSP subarea in, and in described subsequent timeslot unit, during with a DSP time slot corresponding, the data of preserving in this storage subarea are sent to the 2nd DSP.
This method further comprises: described switching net module comprises at least one switching net, and each switching net receives and transmit the data in the different addresses of each DSP data transmission interval simultaneously.
Described switching net module comprises two switching nets, wherein, first switching net receives and transmits the data that are stored in each DSP data transmission interval odd address, and simultaneously, second switching net receives and transmit the data that are stored in each DSP data transmission interval even address.
Mutual communicating devices between a kind of realization digital signal processor is applied to it is characterized in that more than in the system that communicates between the DSP, and this device comprises the switching net module and comprise the DSP module of two DSP at least, wherein,
DSP in the DSP module, a time slot in clock cycle sends data to the switching net module;
The switching net module receives the data that the DSP in the DSP module sends at this time slot, and at subsequent timeslot these data is sent to the 2nd DSP in the DSP module;
The 2nd DSP in the DSP module receives the data that the switching net module is sent at described subsequent timeslot.
Comprise some time slots unit in described clock cycle, comprise in each time slot unit equate with the DSP number and respectively with the corresponding different time-gap of each DSP;
DSP in the described DSP module sends data with the 2nd DSP time slot corresponding to the switching net module in a time slot unit;
Described switching net module sends to the 2nd DSP with a DSP time slot corresponding with these data in the subsequent timeslot unit.
Further be provided with the memory block that each DSP of storage sends data in the described switching net module, and comprise the storage subarea corresponding in each memory block with each time slot;
Described switching net module receives the data that a DSP sends with the 2nd DSP time slot corresponding in a described time slot unit after, directly saving the data in storage the one DSP sends in the memory block of data, in the pairing storage of the corresponding time slot of the 2nd DSP subarea, and in described subsequent timeslot unit, during with a DSP time slot corresponding, the data in this storage subarea are sent to the 2nd DSP.
Described switching net module comprises at least one switching net, and each switching net receives and transmit the data in the different addresses of each DSP data transmission interval simultaneously.
Comprise two switching nets in the described switching net module, wherein, first switching net receives and transmits the data that are stored in each DSP data transmission interval odd address, and second switching net receives and transmit the data that are stored in each DSP data transmission interval even address.
As seen, apparatus and method of the present invention have the following advantages:
1, the use switching net is transmitted the communication data between the DSP, makes CPU discharge the lot of data forwarding work between DSP, thereby has reduced taking cpu resource;
2, the communication data that uses switching net to transmit between the DSP is hardware operation, and promptly switching net need not the executive software instruction, only needs to receive or transmit data according to each time slot, therefore, improve treatment effeciency widely, reduced data transmission delay, improved the traffic rate between the DSP;
3, the present invention uses two switching nets, has increased communication bandwidth, has further improved the traffic rate between the DSP;
4, replace CPU with switching net and transmit communication data between the DSP,, therefore reduced cost because that switching net is compared with CPU is cheap;
5, among the present invention switching net to distribute the mode of the corresponding time slot of each DSP be semipermanent connected mode, promptly can revise by programming with the distribution condition of the corresponding time slot of each DSP, thereby can be according to practical business situation flexible allocation time interval resource, and can adapt to adjustment, thereby satisfied the variation demand of communication service between the DSP to DSP quantity.
Description of drawings
Connection diagram when Fig. 1 is the intercommunication of DSP in the prior art.
Fig. 2 is the encapsulation format schematic diagram that DSP becomes the message bag in the prior art with the transmission data encapsulation between the CPU.
Fig. 3 is the flow chart of the intercommunication of existing techniques in realizing DSP.
Fig. 4 is an apparatus structure schematic diagram of realizing embodiments of the invention.
Fig. 5 is the sequential chart on the DSP communication port pin among the present invention.
Fig. 6 realizes in the embodiments of the invention in the time slot cell schematics of transmission one frame data in the time.
Fig. 7 is that DSP stores the schematic diagram that it sends data among the present invention.
Fig. 8 is that switching net SD539 preserves the schematic diagram that DSP sends data among the present invention.
Fig. 9 is a flow chart of realizing embodiments of the invention.
Figure 10 is the apparatus structure schematic diagram that the present invention adopts two switching nets.
Embodiment
Core concept of the present invention is: each cycle of the clock pulse signal that the outside is provided be divided into the DSP module in each DSP time slot corresponding, in clock cycle during with the 2nd DSP time slot corresponding, the switching net module receives the data that a DSP issues the 2nd DSP, and, the switching net module is sending to the 2nd DSP with a DSP time slot corresponding with these data, and that the 2nd DSP determines to communicate with according to its time slot that receives data is a DSP.
In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with drawings and the specific embodiments.
In the present embodiment, the outside provides the clock pulse signal of 16MHz, and, the DSP frame synchronizing signal of 2KHz is provided.The data of each DSP are that unit sends continuously with the frame.
Fig. 4 is an apparatus structure schematic diagram of realizing embodiments of the invention.As shown in Figure 4, the device of present embodiment comprises DSP module 401 and switching net module 402, comprise 16 DSP in the DSP module 401, and be labeled as DSP0 to DSP15 successively, each DSP uses full-duplex communication port McBSP, respectively with switching net module 802 in model be that the switching net of SD539 links to each other.
Fig. 5 is the sequential chart on the DSP communication port pin among the present invention, and Fig. 6 realizes in the embodiments of the invention in the time slot cell schematics of transmission one frame data in the time.As shown in Figure 5 and Figure 6, the DSP frame synchronizing signal of a 2KHz represents that DSP sends the beginning of frame data, and be 16MHz clock cycle, therefore, number in the time internal clock pulse of transmitting frame data is 16M/2K=8K, 1 byte is 8 again, 1K=1024, so on a time slot passage, transmit the data that to transmit 8K=1024 byte in time of frame data, divide according to time slot of 4 bytes, then in the time of transmission one frame data, 1024/4=256 time slot arranged, 256 time slots are divided into 16 time slot unit, be labeled as time slot unit 0 successively to time slot unit 15,256/16=16 again, can with each time slot dividing elements 16 time slots, be labeled as time slot 0 successively to time slot 15, the number of DSP is 16 again, so with each DSP respectively with each time slot unit in the time slot identical with its numbering carry out corresponding, it is the time slot 0 in corresponding each the time slot unit of DSP0, time slot 1 in corresponding each the time slot unit of DSP1, the rest may be inferred, the time slot 15 to corresponding each the time slot unit of DSP15.
Fig. 7 is that DSP stores the schematic diagram that it sends data among the present invention.As shown in Figure 7, with DSP0 is example, DSP0 is stored its transmission buffering area that sends data be divided into 15 sending areas, be labeled as successively and send 1 district to sending 15 districts, and store the data that will send to DSP1 to DSP15 successively, simultaneously, each sending area is divided into 16 Word districts, be labeled as the Word0 district to the Word15 district, be stored in the data that send in time slot unit 0 to the time slot unit 15 successively.
Fig. 8 is that switching net SD539 preserves the schematic diagram that DSP sends data among the present invention, as shown in Figure 8, the buffering area that SD539 is used to store the data that each DSP sends is divided into 16 memory blocks, be labeled as memory block 0 to memory block 15 successively, and store the data that DSP0 to DSP15 sends successively, simultaneously, each memory block is divided into 16 time slot districts, be labeled as time slot 0 district successively to time slot 15 districts, the data that the time slot 0 that is stored in each time slot unit successively SD539 to the time slot 15 receives, for example, in time slot 0 district of SD539 memory block 1, preserve the data that DSP1 sends at the time slot 0 of each time slot unit.
In the present embodiment, if DSPi (i=0,1..15) need be to DSPj (j ≠ i, j=0,1..15) transmission data, then DSPi with DSPj time slot corresponding (j+N * 16) (N=0,1..15) upward its data are sent to switching net SD539, switching net SD539 is then in that (N=0 sends the data to DSPj on 1..15), and DSPj learns that from receiving slot (i+N * 16) data that receive are that DSPi sends with DSPi time slot corresponding (i+N * 16).Here, described N is meant the sequence number of each time slot unit that comprises in the time of transmission one frame data.
In the present embodiment, each DSP corresponding each time slot in time slot unit 0 sends data to switching net, and each DSP corresponding each time slot in time slot unit 1 receives the data that switching net is sent, thereby realizes the intercommunication mutually between 16 DSP.
Fig. 9 is a flow chart of realizing embodiments of the invention.In conjunction with Fig. 4 and Fig. 9, on the basis of apparatus of the present invention, the inventive method realizes that the detailed process of the intercommunication of DSP may further comprise the steps:
Step 901: the time slot 0 in time slot unit 0, DSP1 to DSP15 in the DSP module 401 sends to find in the buffering area at it and is used to preserve transmission 0 district that sends to the DSP0 data, then in sending 0 district, find the Word0 district that sends data during being kept at time slot unit 0, judge then whether data are arranged in the Word0 district, if have, reading of data from the Word0 district then, and these valid data that will read send to the switching net SD539 in the switching net module 402, if no, then the invalid data frame is sent to switching net SD539;
Switching net SD539 is kept at the data that receive respectively in the memory block of each DSP data of storage in time slot 0 district, for example SD539 data that DSP1 is sent are kept in time slot 0 district of memory block 1, the data that DSP2 is sent are kept in time slot 0 district of SD539 memory block 2, the rest may be inferred, up to having preserved the data that each DSP sends.
Here, because at time slot 0, so DSP0 does not send data, other DSP then will send to switching net SD539 with the communication data of DSP0.
Step 902: time slot 1 in time slot unit 0, DSP0 in the DSP module 401 and DSP2 to DSP15 send to find in the buffering area at it and are used to preserve transmission 1 district that sends to the DSP1 data, then in sending 1 district, find the Word0 district that sends data during being kept at time slot unit 0, judge then whether data are arranged in the Word0 district, if have, reading of data from the Word0 district then, and these valid data that will read send to the switching net SD539 in the switching net module 402, if no, then the invalid data frame is sent to switching net SD539;
Switching net SD539 is kept at the data that receive respectively in the memory block of each DSP data of storage in time slot 1 district, for example SD539 data that DSP2 is sent are kept in time slot 1 district of SD539 memory block 2, the rest may be inferred, up to having preserved the data that each DSP sends.
Here, because at time slot 1, so DSP1 does not send data, other DSP then will send to switching net SD539 with the communication data of DSP1.
Step 903: according to the principle of step 901 to the described process of step 902, switching net SD539 receives and preserves the data that each DSP sends at other each time slot of time slot unit 0.
Step 904: the time slot 0 in time slot unit 1, switching net SD539 sends to DSP1 with the data in time slot 1 district in the memory block 0, and the data in time slot 2 districts are sent to DSP2, and the rest may be inferred, until the data in time slot 15 districts are sent to DSP15.
Here, because the data that DSP1 receives at time slot 0 are that DSP0 sends so DSP1 can determine the data that receive, that promptly communicate with is DSP0.In like manner, other DSP is a time slot 0 according to the time slot that receives data, and specified data is that DSP0 sends.
Step 905: the time slot 1 in time slot unit 1, switching net SD539 sends to DSP0 with the data in time slot 0 district in the memory block 1, and the data in time slot 2 districts are sent to DSP2, and the rest may be inferred, until the data in time slot 15 districts are sent to DSP15.
Here, because the data that DSP0 receives at time slot 1 are that DSP1 sends so DSP0 can determine the data that receive, that promptly communicate with is DSP1.In like manner, other DSP is a time slot 1 according to the time slot that receives data, and specified data is that DSP1 sends.
Step 906: according to the principle of step 904 to the described process of step 905, switching net SD539 sends the data to corresponding DSP at other each time slot of time slot unit 1.
In order to enlarge the communication bandwidth between the DSP, improve the traffic rate between the DSP, a preferable embodiment is to use the parallel data forwarding work of finishing between the DSP of two switching nets.Figure 10 is the apparatus structure schematic diagram that the present invention adopts two switching nets.Referring to Figure 10, can comprise in the switching net module 402 of apparatus of the present invention that two models are the switching net of SD539, and be labeled as SD539#0 and SD539#1, SD539#0 is by the full-duplex communication port McBSP on each DSP, being labeled as McBSP1 links to each other with each DSP respectively, SD539#1 is labeled as McBSP2 and links to each other with each DSP respectively by another full-duplex communication port McBSP on each DSP.
Correspondingly, on the basis of apparatus of the present invention, in the detailed process of the intercommunication of the inventive method realization DSP, SD539#0 and SD539#1 concurrent working by a part of data of SD539#0 forwarding DSP, are transmitted another part data of DSP simultaneously by SD539#1.Send to switching net SD539#0 such as the data that will be stored in the DSP buffering area even address, transmit data in this even address by SD539#0, simultaneously, the data that are stored in this DSP buffering area odd address are sent to switching net SD539#1, transmit data in this odd address by SD539#1, and other content of described process and other corresponding contents in the above-mentioned implementation process are identical.
In the present embodiment, switching net is preserved the data that it receives at a time slot unit, and in next time slot unit the data of its preservation is sent to corresponding D SP.In other embodiment beyond the present embodiment, switching net also can receive in continuous several time slots unit and preserve data, and sends data to corresponding DSP in follow-up several time slots unit, and the principle of its specific implementation process is identical with present embodiment.
In a word, the above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1, mutual method for communicating between a kind of realization digital signal processor, be applied to more than in the system that communicates between one the digital signal processor DSP, it is characterized in that, this method comprises: the switching net module is set, several slots will be divided into each clock cycle, the one DSP sends data at a time slot to the switching net module, and the switching net module sends to the 2nd DSP at subsequent timeslot with these data.
2, method according to claim 1 is characterized in that, will be divided into some time slots unit described clock cycle, comprise in each time slot unit equate with the DSP number and respectively with the corresponding different time-gap of each DSP;
A described DSP sends data with the 2nd DSP time slot corresponding to the switching net module in a time slot unit;
Described switching net module sends to the 2nd DSP with a DSP time slot corresponding with these data in the subsequent timeslot unit.
3, method according to claim 2 is characterized in that, this method further comprises: the memory block that each DSP of storage sends data is set in the switching net module, and each memory block is divided into the storage subarea corresponding with each time slot;
Described switching net module receives the data that a DSP sends with the 2nd DSP time slot corresponding in a described time slot unit after, directly these data are kept at storage the one DSP send in the memory block of data with the pairing storage of the corresponding time slot of the 2nd DSP subarea in, and in described subsequent timeslot unit, during with a DSP time slot corresponding, the data of preserving in this storage subarea are sent to the 2nd DSP.
4, according to claim 1,2 or 3 described methods, it is characterized in that, this method further comprises: described switching net module comprises at least one switching net, and each switching net receives and transmit the data in the different addresses of each DSP data transmission interval simultaneously.
5, method according to claim 4, it is characterized in that, described switching net module comprises two switching nets, wherein, first switching net receives and transmits the data that are stored in each DSP data transmission interval odd address, simultaneously, second switching net receives and transmits the data that are stored in each DSP data transmission interval even address.
6, mutual communicating devices between a kind of realization digital signal processor is applied to it is characterized in that more than in the system that communicates between the DSP, and this device comprises the switching net module and comprise the DSP module of two DSP at least, wherein,
DSP in the DSP module, a time slot in clock cycle sends data to the switching net module;
The switching net module receives the data that the DSP in the DSP module sends at this time slot, and at subsequent timeslot these data is sent to the 2nd DSP in the DSP module;
The 2nd DSP in the DSP module receives the data that the switching net module is sent at described subsequent timeslot.
7, device according to claim 6 is characterized in that, comprises some time slots unit in described clock cycle, comprise in each time slot unit equate with the DSP number and respectively with the corresponding different time-gap of each DSP;
DSP in the described DSP module sends data with the 2nd DSP time slot corresponding to the switching net module in a time slot unit;
Described switching net module sends to the 2nd DSP with a DSP time slot corresponding with these data in the subsequent timeslot unit.
8, device according to claim 7 is characterized in that, further is provided with the memory block that each DSP of storage sends data in the described switching net module, and comprises the storage subarea corresponding with each time slot in each memory block;
Described switching net module receives the data that a DSP sends with the 2nd DSP time slot corresponding in a described time slot unit after, directly saving the data in storage the one DSP sends in the memory block of data, in the pairing storage of the corresponding time slot of the 2nd DSP subarea, and in described subsequent timeslot unit, during with a DSP time slot corresponding, the data in this storage subarea are sent to the 2nd DSP.
9, device according to claim 6 is characterized in that, described switching net module comprises at least one switching net, and each switching net receives and transmit the data in the different addresses of each DSP data transmission interval simultaneously.
10, according to claim 6 or 9 described devices, it is characterized in that, comprise two switching nets in the described switching net module, wherein, first switching net receives and transmits the data that are stored in each DSP data transmission interval odd address, and second switching net receives and transmit the data that are stored in each DSP data transmission interval even address.
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| CN109597777A (en) * | 2018-12-11 | 2019-04-09 | 济南浪潮高新科技投资发展有限公司 | A kind of MCBSP interface inter-link device and method based on FPGA |
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| US5243626A (en) * | 1991-08-29 | 1993-09-07 | Apple Computer, Inc. | Method for clocks synchronization for receiving pulse position encoded signals |
| JP4451558B2 (en) * | 2000-09-26 | 2010-04-14 | 株式会社リコー | Modem using DSP signal processor |
| CN100417232C (en) * | 2001-09-30 | 2008-09-03 | 中兴通讯股份有限公司 | Vocoder system using multiple port routing to communicate and its business frame exchanging method |
| CN1252953C (en) * | 2001-11-23 | 2006-04-19 | 中兴通讯股份有限公司 | Method and apparatus for parallel realizing CDMA circuit data and voice business |
| CN1269331C (en) * | 2002-05-31 | 2006-08-09 | 华为技术有限公司 | Method for sanding and receiving data based on synchronous serial interface in digital signal processor |
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