CN109960674A - A kind of USB interface interconnected method and system based on FPGA - Google Patents
A kind of USB interface interconnected method and system based on FPGA Download PDFInfo
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- CN109960674A CN109960674A CN201910274084.0A CN201910274084A CN109960674A CN 109960674 A CN109960674 A CN 109960674A CN 201910274084 A CN201910274084 A CN 201910274084A CN 109960674 A CN109960674 A CN 109960674A
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- usb interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- General Engineering & Computer Science (AREA)
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- Computer And Data Communications (AREA)
- Information Transfer Systems (AREA)
Abstract
The present invention relates to field of data transmission, specifically provide a kind of USB interface interconnected method and system based on FPGA.The system includes FPGA and several chips with USB interface, and USB interface sending/receiving module, usb protocol parsing module, FIFO, message analysis module and arbitration Switching Module are arranged in FPGA；Several chips with USB interface are connect with USB interface sending/receiving module, realize the transmission of data, according to the parameter in data, by the forward-path of arbitration Switching Module selection data.Compared with prior art, some data sharings and interconnection of each chip chamber not only may be implemented in the present invention, and the system is also made to have higher flexibility and better performance, have good promotional value.
Description
Technical field
The present invention relates to technical field of data transmission, specifically provide a kind of USB interface interconnected method based on FPGA and are
System.
Background technique
FPGA (Field Programmable Gate Array), i.e. field programmable gate array have very high flexible
Property, while FPGA has I/O pin abundant, short relative to the ASIC development cycle, reliability is higher.
USB is an external bus standard, for being connected and communicate with for specification computer and external equipment.USB interface is supported
The plug and play and warm connection function of equipment.USB interface can be used for connect up to 127 kinds of peripheral hardwares, as mouse, modem and
Keyboard etc..USB is to be proposed in the end of the year 1994 by Intel, Compaq, IBM, Microsoft Deng Duo company joint, from 1996
After year releasing, successfully substitute serial ports and parallel port, and become current PC and a large amount of smart machines the interface that must match it
One.
At present in field of data transmission, when generally existing multiple interfaces connect multiple ports the larger transmission speed of data volume it is slow and
The problem of data are easily lost, it is on the other hand, lower there is also the online configurability of priority and flexibility ratio is not high enough, data it
Between transmission and forwarding flexibility ratio also not high enough disadvantage, be further improved.
Summary of the invention
The present invention be directed to above-mentioned the deficiencies in the prior art, provide a kind of practical USB interface interconnection based on FPGA
Method.
The further technical assignment of the present invention be to provide it is a kind of design rationally, the safe and applicable USB interface based on FPGA
Interacted system.
The technical solution adopted by the present invention to solve the technical problems is:
A kind of USB interface interconnected method based on FPGA, the equipment that this method is related to have FPGA and several with USB interface
Chip, USB interface sending/receiving module, usb protocol parsing module, FIFO, message analysis module and arbitration are set in FPGA
Switching Module.The transmission mode of this method are as follows: data are respectively sent to USB interface and sent by several chips with USB interface
Receiving module, the CRC that USB interface sending/receiving module receives data and accounting counts in, judges according to the CRC in data
Whether data are correct；If receiving the wrong chip for just informing opposite end of data retransmits data, if errorless, USB interface transmission is connect
It receives module and these data is sent to message analysis module through usb protocol parsing module, message analysis module is by parameter in data
It extracts, is sent to arbitration Switching Module, the parameter selection number that arbitration Switching Module is extracted according to message analysis module
According to forward-path.
Further, several chips with USB interface refer to that n block has the chip of USB interface, and n is more than or equal to 1
Natural number less than or equal to 10.
Further, the USB interface sending/receiving module simulates the Read-write Catrol of USB according to the interface sequence of USB.
Preferably, several chips with USB interface send number to USB interface sending/receiving module simultaneously
According to the format of above-mentioned data is heading+data+message trailer, wherein the heading includes header indicatingjhe number, source ID, mesh
ID and priority, the message trailer include tail portion indication signal and CRC.
Further, the parameter that the message analysis module extracts includes source ID, purpose ID and priority.
Further, it is extracted when the forward-path of the arbitration Switching Module selection data depending on message analysis module
Purpose ID.
Preferably, according to arriving first the principle first handled when the arbitration modules carry out data processing.
Further, when first handling the data that one group of chip with USB interface is sent, other have the core of USB interface
The data that piece is sent, which can be buffered in FIFO, to be waited.
Further, if having the data of the chip transmission of not homologous ID in the data stored in FIFO while reaching,
The mode of arbitration Switching Module priority processing has 3 kinds, as follows:
1. determining preferential forwarding according to the priority screened in message analysis module；
2. determining the data of priority processing according to the numerical values recited of data source ID if priority is identical, source ID is small
High priority data processing；
3. the size of source ID is also identical if priority is identical, then using the method for timesharing slice, pass through one in each time
The data packet of a source ID, the next period by the data packet of another source ID, and so on interact the transmissions of data.
A kind of system of the USB interface interconnection based on FPGA, includes FPGA and several chips with USB interface, wherein
USB interface sending/receiving module, usb protocol parsing module, FIFO, message analysis module and arbitration interchange mode are set in FPGA
Block.
Several chips with USB interface are connect with USB interface sending/receiving module, USB interface sending/receiving
Block receives above-mentioned data and can calculate the CRC in message；Usb protocol parsing module by from USB interface sending/receiving module come
Data are further parsed；FIFO is used to store the data of usb protocol parsing module；Message analysis module is by USB interface
Source ID, purpose ID and priority extract in the data message head that sending/receiving module is sent；Switching Module is arbitrated according to report
The forward-path for the purpose ID selection data that literary analysis module is extracted.Several chips with USB interface refer to that n block has
The chip of USB interface, n are the natural number for being less than or equal to 10 more than or equal to 1.
Compared to the prior art a kind of USB interface interconnected method and system based on FPGA of the invention, has following prominent
Out the utility model has the advantages that some data of each chip chamber not only may be implemented in USB interface interconnected method and system based on FPGA
Shared and interconnection also makes the system have higher flexibility and better performance, meanwhile, the USB interface based on FPGA
Interconnected method and system also have data transmission bauds fast, and the feature that priority can configure online and flexibility ratio is high has good
Good promotion and use value.
Detailed description of the invention
Attached drawing 1 is a kind of system block diagram of USB interface interacted system based on FPGA；
Specific embodiment
In order to make those skilled in the art better understand the solution of the present invention, below with reference to specific embodiment pair
The present invention is described in further detail.Obviously, described embodiments are only a part of the embodiments of the present invention, rather than complete
The embodiment in portion.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work
Every other embodiment obtained shall fall within the protection scope of the present invention.
A most preferred embodiment is given below:
As shown in Figure 1, a kind of system of the USB interface interconnection based on FPGA, comprising FPGA and several with USB interface
Chip, several chips with USB interface refer to that n block has the chip of USB interface, and wherein n is to be less than or equal to more than or equal to 1
10 natural number.In FPGA be arranged USB interface sending/receiving module, usb protocol parsing module, FIFO, message analysis module and
Arbitrate Switching Module.
Several chips with USB interface are connect with USB interface sending/receiving module, USB interface sending/receiving
Block receives above-mentioned data and can calculate the CRC in message；Usb protocol parsing module by from USB interface sending/receiving module come
Data are further parsed；FIFO is used to store the data of usb protocol parsing module；Message analysis module is by USB interface
Source ID, purpose ID and priority extract in the data message head that sending/receiving module is sent；Switching Module is arbitrated according to report
The forward-path for the purpose ID selection data that literary analysis module is extracted.Above-mentioned several chips with USB interface, USB interface hair
Sending between receiving module, usb protocol parsing module, FIFO, message analysis module and arbitration Switching Module data is all mutually to pass
It send.
For the chip and FPGA by 5 with USB interface carry out data transmission below, transmission mode are as follows: 5 have
The chip of USB interface is respectively chip 0, chip 1, chip 2, chip 3, chip 4, and said chip is sent data to simultaneously respectively
USB interface sending/receiving module simulates the Read-write Catrol of USB, USB interface sending/receiving module according to the interface sequence of USB
The data CRC that simultaneously accounting counts in is received, above-mentioned received data all meet heading+data+message trailer format.Its
In, heading includes header indicatingjhe number, source ID, purpose ID and priority, and message trailer includes tail portion indication signal and CRC.Root
Judge whether data are correct according to the CRC in message；If receiving the wrong chip for just informing opposite end of data retransmits data, if
Errorless, these data are sent to message analysis module, message point through usb protocol parsing module by USB interface sending/receiving module
Analysis module comes out the parameter extractions such as source ID, purpose ID and priority in message, is sent to arbitration Switching Module, arbitration exchange
The forward-path for the purpose ID selection data that module is extracted according to message analysis module.
Wherein, one group is first handled with USB according to the principle first handled is arrived first when arbitration Switching Module progress data processing
When the data that the chip of interface is sent, the data that other chips with USB interface are sent, which can be buffered in FIFO, to be waited.With core
For piece 0 to chip 4, if the data of chip 0 to chip 4 successively reach, arbitrates Switching Module and first handle the transmission of chip 0
Data, the data that chip 1, chip 2, chip 3 and chip 4 are sent, which can be buffered in FIFO, to be waited；If chip 0 and chip 1 are sent
Data simultaneously when reaching, according to the different source ID of chip 0 and chip 1, the mode for arbitrating Switching Module priority processing has 3 kinds,
It is as follows:
1. determining preferential forwarding according to the priority screened in message analysis module；
2. determining the data of priority processing according to the numerical values recited of data source ID if priority is identical, source ID is small
High priority data processing；
3. the size of source ID is also identical if priority is identical, then using the method for timesharing slice, pass through one in each time
The data packet of a source ID, the next period by the data packet of another source ID, and so on interact the transmissions of data.
It is waited at this point, chip 2 can be all buffered in FIFO to the data that chip 4 is sent.
Above-mentioned specific embodiment is only the specific case of the present invention, and scope of patent protection of the invention includes but unlimited
In above-mentioned specific embodiment, any method and system right for meeting the USB interface interconnection of the invention based on FPGA is wanted
Ask book and any technical field those of ordinary skill appropriate variation or replacement that it is made, it should all fall into the present invention
Scope of patent protection.
Claims (10)
1. a kind of USB interface interconnected method based on FPGA, which is characterized in that
The equipment that this method is related to has FPGA and several chips with USB interface, and USB interface sending/receiving is arranged in FPGA
Block, usb protocol parsing module, FIFO, message analysis module and arbitration Switching Module；
The transmission mode of this method are as follows: several chips with USB interface send data to USB interface sending/receiving respectively
Block, the CRC that USB interface sending/receiving module receives data and accounting counts in, judges that data are according to the CRC in data
It is no correct；If receiving the wrong chip for just informing opposite end of data retransmits data, if errorless, USB interface sending/receiving module
These data are sent to message analysis module through usb protocol parsing module, message analysis module goes out parameter extraction in data
Come, be sent to arbitration Switching Module, the parameter selection data that arbitration Switching Module is extracted according to message analysis module turn
Send out path.
2. a kind of USB interface interconnected method based on FPGA according to claim 1, it is characterised in that described several to have
The chip of USB interface refers to that n block has the chip of USB interface, and n is the natural number for being less than or equal to 10 more than or equal to 1.
3. a kind of USB interface interconnected method based on FPGA according to claim 1, it is characterised in that the USB interface
Sending/receiving module simulates the Read-write Catrol of USB according to the interface sequence of USB.
4. a kind of USB interface interconnected method based on FPGA according to claim 1, it is characterised in that several bands
There is the chip of USB interface to send data to USB interface sending/receiving module simultaneously, the formats of above-mentioned data be heading+data+
Message trailer, wherein the heading includes header indicatingjhe number, source ID, purpose ID and priority, and the message trailer includes tail portion
Indication signal and CRC.
5. a kind of USB interface interconnected method based on FPGA according to claim 4, it is characterised in that the message analysis
The parameter that module extracts includes source ID, purpose ID and priority.
6. a kind of USB interface interconnected method based on FPGA according to claim 5, it is characterised in that the arbitration exchange
Module selects the purpose ID extracted when the forward-path of data depending on message analysis module.
7. a kind of USB interface interconnected method based on FPGA according to claim 6, it is characterised in that the arbitration exchange
According to arriving first the principle first handled when module carries out data processing.
8. a kind of USB interface interconnected method based on FPGA according to claim 7, it is characterised in that the arbitration exchange
When the data that one group of the resume module chip with USB interface is sent, the data that other chips with USB interface are sent can be delayed
There are wait in FIFO.
9. a kind of USB interface interconnected method based on FPGA according to claim 8, it is characterised in that described in FIFO
If there are the data of the chip transmission of not homologous ID in the data of storage while reaching, the mode of Switching Module priority processing is arbitrated
There are 3 kinds, as follows:
1. determining preferential forwarding according to the priority screened in message analysis module；
2. determining the data of priority processing, source ID small data according to the numerical values recited of data source ID if priority is identical
Priority processing；
3. the size of source ID is also identical if priority is identical, then using the method for timesharing slice, pass through a source in each time
The data packet of ID, the next period by the data packet of another source ID, and so on interact the transmissions of data.
10. a kind of system of the USB interface interconnection based on FPGA, which is characterized in that comprising FPGA and several with USB interface
Chip, wherein USB interface sending/receiving module, usb protocol parsing module, FIFO, message analysis module and secondary are set in FPGA
Cut out Switching Module；
Several chips with USB interface are connect with USB interface sending/receiving module, and USB interface sending/receiving module connects
It receives above-mentioned data and the CRC in message can be calculated；The data that usb protocol parsing module will come from USB interface sending/receiving module
Further parsed；FIFO is used to store the data of usb protocol parsing module；Message analysis module sends USB interface
Source ID, purpose ID and priority extract in the data message head that receiving module is sent；Switching Module is arbitrated according to message point
Analyse the forward-path for the purpose ID selection data that module is extracted.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910274084.0A CN109960674A (en) | 2019-04-08 | 2019-04-08 | A kind of USB interface interconnected method and system based on FPGA |
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| CN201910274084.0A CN109960674A (en) | 2019-04-08 | 2019-04-08 | A kind of USB interface interconnected method and system based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111274180A (en) * | 2020-01-17 | 2020-06-12 | 济南浪潮高新科技投资发展有限公司 | Aurora and Rapid IO interface conversion device |
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Application publication date: 20190702 |