CN109585557A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
- Publication number
- CN109585557A CN109585557A CN201811062244.7A CN201811062244A CN109585557A CN 109585557 A CN109585557 A CN 109585557A CN 201811062244 A CN201811062244 A CN 201811062244A CN 109585557 A CN109585557 A CN 109585557A
- Authority
- CN
- China
- Prior art keywords
- region
- conduction type
- semiconductor devices
- extrinsic
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 claims description 60
- 239000012535 impurity Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 19
- 239000013078 crystal Substances 0.000 claims description 13
- 238000000926 separation method Methods 0.000 claims description 4
- 238000007667 floating Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 85
- 102100025395 Zinc finger CCHC domain-containing protein 7 Human genes 0.000 description 58
- 101000788853 Homo sapiens Zinc finger CCHC domain-containing protein 7 Proteins 0.000 description 57
- 101100378708 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) AIR2 gene Proteins 0.000 description 49
- 239000011229 interlayer Substances 0.000 description 24
- 101150064559 FTR1 gene Proteins 0.000 description 17
- 238000005530 etching Methods 0.000 description 15
- 230000000052 comparative effect Effects 0.000 description 12
- 101100386054 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CYS3 gene Proteins 0.000 description 9
- 101100204457 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SVF1 gene Proteins 0.000 description 9
- 101150035983 str1 gene Proteins 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 230000005611 electricity Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 101100286131 Arabidopsis thaliana HXK1 gene Proteins 0.000 description 3
- 102100034058 Gypsy retrotransposon integrase-like protein 1 Human genes 0.000 description 3
- 101000926251 Homo sapiens Gypsy retrotransposon integrase-like protein 1 Proteins 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052744 lithium Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000017260 vegetative to reproductive phase transition of meristem Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/18—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for batteries; for accumulators
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Protection Of Static Devices (AREA)
Abstract
本公开涉及一种半导体器件及其制造方法,其简化了制造工艺,同时减小了第一MOS晶体管区域和第二MOS晶体管区域之间的分离的宽度。第一MOS晶体管和第二MOS晶体管配置双向开关。第一MOS晶体管和第二MOS晶体管均具有垂直沟槽结构。第一杂质区域邻接在第一MOS晶体管区域外的第一MOS晶体管元件的第一栅极沟槽的侧壁上,并且电耦合至第一源极区域。
Description
相关申请的交叉参考
2017年9月28日提交的日本专利申请第2017-188349号的包括说明书、附图和摘要的公开通过引证全部引入本文。
技术领域
本发明涉及半导体器件及其制造方法,并且更具体地,涉及具有双向开关的半导体器件及其制造方法。
背景技术
例如,日本未审查专利申请公开第2004-274039号、2007-201338号和2006-147700号均描述了具有双向开关的半导体器件。
在日本未审查专利申请公开第2004-274039号、2007-201338号和2006-147700号中,在一个芯片上交替地布置配置双向开关的垂直第一MOS(金属氧化物半导体)晶体管元件和第二MOS晶体管元件。
发明内容
关于在日本未审查专利申请公开第2004-274039号、2007-201338号和2006-147700号中描述的交替布置第一MOS晶体管元件区域和第二MOS晶体管元件区域的结构,存在减小第一MOS晶体管元件区域和第二MOS晶体管元件区域之间的分离的宽度并简化制造工艺的需求。
本发明的上述和进一步的目的和新颖特征将从本说明书和附图的以下详细描述中变得更加明显。
根据本发明的一个方面,提供了一种具有双向开关的半导体器件。该半导体器件包括半导体衬底、第一晶体管元件和第二导电类型的第一杂质区域。半导体衬底具有彼此相对的第一表面和第二表面,并且具有从第一表面朝向第二表面延伸的第一栅极沟槽。第一晶体管元件包括位于第二表面中的第一导电类型的第一漏极区域、位于第一表面中的第一导电类型的第一源极区域以及位于第一栅极沟槽内且包括在双向开关中的第一栅电极。第一杂质区域邻接在第一栅极沟槽的用于第一晶体管元件的区域外的侧壁上,并且电耦合至第一源极区域。
根据本发明的另一方面,提供了一种用于制造具有双向开关的半导体器件的方法,其包括以下步骤。
形成半导体衬底,其具有彼此相对的第一表面和第二表面,并且具有从第一表面朝向第二表面延伸的第一栅极沟槽。形成第一晶体管元件,其包括位于第二表面中的第一导电类型的第一漏极区域、位于第一表面中的第一导电类型的第一源极区域以及位于第一栅极沟槽内且包括在双向开关中的第一栅电极。形成第二导电类型的第一杂质区域,其邻接在第一栅极沟槽的用于第一晶体管元件的区域外的侧壁上,并且电耦合至第一源极区域。
根据本发明,提供了一种半导体器件及其制造方法,简化了制造工艺,同时减小了第一MOS晶体管元件区域和第二MOS晶体管元件区域之间的分离的宽度。
附图说明
图1示出了根据每个实施例的应用于半导体器件的保护电路的示例;
图2是示出根据第一实施例的半导体器件的结构的平面图;
图3是示出图2中的区域RA的部分放大平面图;
图4是沿着图3中的线IV_IV截取的截面图;
图5是示出根据第一实施例的半导体器件的制造方法的第一步骤的截面图;
图6是示出根据第一实施例的半导体器件的制造方法的第二步骤的截面图;
图7是示出根据第一实施例的半导体器件的制造方法的第三步骤的截面图;
图8是示出根据第一实施例的半导体器件的制造方法的第四步骤的截面图;
图9是示出根据第一实施例的半导体器件的制造方法的第五步骤的截面图;
图10是示出根据第一实施例的半导体器件的制造方法的第六步骤的截面图;
图11是示出根据第一实施例的半导体器件的制造方法的第七步骤的截面图;
图12是示出根据第一实施例的半导体器件的制造方法的第八步骤的截面图;
图13是示出根据第一实施例的半导体器件的制造方法的第九步骤的截面图;
图14是示出根据第一实施例的半导体器件的制造方法的第十步骤的截面图;
图15是解释比较示例1中的导通状态电流路径的截面图;
图16是示出如何根据第一MOS晶体管和第二MOS晶体管的划分数量改变电阻的示图;
图17是示出比较示例2中的半导体器件的结构的截面图;
图18是示出比较示例3中的半导体器件的结构的截面图;
图19是示出根据第二实施例的半导体器件的结构的截面图;
图20是示出根据第二实施例的半导体器件的制造方法的第一步骤的截面图;
图21是示出根据第二实施例的半导体器件的制造方法的第二步骤的截面图;
图22是示出根据第二实施例的半导体器件的制造方法的第三步骤的截面图;
图23是示出根据第二实施例的半导体器件的制造方法的第四步骤的截面图;
图24是示出根据第二实施例的半导体器件的制造方法的第五步骤的截面图;
图25是示出根据第三实施例的半导体器件的结构的截面图;
图26是示出根据第四实施例的半导体器件的结构的截面图;
图27是沿着图28中的线XXVII-XXVII截取的截面图,其示出了根据第五实施例的半导体器件的结构;
图28是示出根据第五实施例的半导体器件的结构的平面图;
图29是示出根据第五实施例的半导体器件的制造方法的第一步骤的截面图;
图30是示出根据第五实施例的半导体器件的制造方法的第二步骤的截面图;
图31是示出根据第五实施例的半导体器件的制造方法的第三步骤的截面图;
图32是示出根据第五实施例的半导体器件的制造方法的第四步骤的截面图;
图33是示出根据第五实施例的半导体器件的制造方法的第五步骤的截面图;
图34是示出根据第五实施例的半导体器件的制造方法的第六步骤的截面图;以及
图35是示出根据第五实施例的半导体器件的制造方法的第七步骤的截面图。
具体实施方式
首先,下面将解释根据每个实施例的半导体器件的使用模式。半导体器件的使用模式
例如,图1所示的电路是用于二次电池SBA的保护电路。例如,二次电池SBA是锂离子电池。半导体器件SED和控制器PCP耦合至二次电池SBA。
半导体器件SED具有双向开关。该双向开关包括第一MOS晶体管FMTR和第二MOS晶体管SMTR。第一MOS晶体管FMTR和第二MOS晶体管SMTR彼此之间串联电耦合。
具体地,第一MOS晶体管FMTR的漏极D和第二MOS晶体管SMTR的漏极D相互电耦合。第一MOS晶体管FMTR的源极S1电耦合至保护电路的负(-)端子。第二MOS晶体管SMTR的源极S2电耦合至二次电池SBA的负(-)电极。
二次电池SBA的正(+)电极电耦合至保护电路的正端子。第一MOS晶体管FMTR的第一栅极G1和第二MOS晶体管SMTR的第二栅极G2电耦合至控制器PCP。
为了对该保护电路中的二次电池SBA进行充电,首先将外部电源EBA耦合至保护电路的负端子和正端子。根据来自控制器PCP的信号,半导体器件SED中的第一MOS晶体管FMTR和第二MOS晶体管SMTR均导通。电流在箭头Y1的方向上从外部电源EBA流动,以对二次电池SBA进行充电。
当完成充电时,控制器PCP检测到充电的完成,并且截止第一MOS晶体管FMTR。这就断开了电路,并且防止二次电池SBA被过充电。
为了对二次电池SBA进行放电,负载(未示出)耦合至保护电路的负端子和正端子。根据来自控制器PCP的信号,半导体器件SED中的第一MOS晶体管FMTR和第二MOS晶体管SMTR均导通。电流在箭头Y2的方向上从二次电池SBA流向负载,使得存储在二次电池SBA中的电量减小,并且二次电池SBA被放电。
当完成放电时,控制器PCP检测到放电的完成,并且截止第二MOS晶体管SMTR。这就断开了电路,并且防止二次电池SBA被过放电。
接下来,将描述包括第一MOS晶体管FMTR和第二MOS晶体管SMTR的半导体器件SED。
第一实施例
如图2和图3所示,根据第一实施例的半导体器件SED包括第一MOS晶体管FMTR和第二MOS晶体管SMTR。
第一MOS晶体管FMTR包括多个第一MOS晶体管元件FMTE。第一MOS晶体管元件FMTE分别布置在多个第一MOS晶体管区域FMTA中(图3)。
如图3所示,在平面图中,第一MOS晶体管区域FMTA被第一栅极沟槽TR1的外壁环绕(图中被链线环绕的区域)。多个第一MOS晶体管元件FMTE被布置在一个第一MOS晶体管区域FMTA中。在该实施例中,例如,两个第一MOS晶体管元件FMTE布置在一个第一MOS晶体管区域FMTA中。然而,布置在一个第一MOS晶体管区域FMTA中的第一MOS晶体管元件FMTE的数量也可以是一个或者多于两个。
如图2和图3所示,第二MOS晶体管SMTR包括多个第二MOS晶体管元件SMTE。第二MOS晶体管元件SMTE分别布置在多个第二MOS晶体管区域SMTA中(图3)。
如图3所示,在平面图中,第二MOS晶体管区域SMTA被第二栅极沟槽TR2的外壁环绕(图中被双点划线环绕的区域)。多个第二MOS晶体管元件SMTE被布置在一个第二MOS晶体管区域SMTA中。在该实施例中,例如,两个第二MOS晶体管元件SMTE布置在一个第二MOS晶体管区域SMTA中。然而,布置在一个第二MOS晶体管区域SMTA中的第二MOS晶体管元件SMTE的数量也可以是一个或者多于两个。
如图2和图3所示,在平面图中,交替地布置第一MOS晶体管区域FMTA和第二MOS晶体管区域SMTA。一个第一源电极S1位于一个第一MOS晶体管区域FMTA中。如稍后所描述的,第一源电极S1通过插塞导电层PL电耦合至第一MOS晶体管元件FMTE的第一源极区域。一个第一源电极S1电耦合至多个第一MOS晶体管元件FMTE。
一个第二源电极S2位于一个第二MOS晶体管区域SMTA中。如稍后所描述的,第二源电极S2通过插塞导电层PL电耦合至第二MOS晶体管元件SMTE的第二源极区域。一个第二源电极S2电耦合至多个第二MOS晶体管元件SMTE。
如稍后所描述的,第一栅电极G1位于一个第一MOS晶体管区域FMTA中的第一栅极沟槽TR1内。每个第一栅电极G1都通过插塞导电层PL电耦合至第一栅极布线层GIN1。第一栅极布线层GIN1电耦合至第一栅极焊盘GP1。
从而,每个第一MOS晶体管区域FMTA的第一栅电极G1通过插塞导电层PL和第一栅极布线层GIN1电耦合至第一栅极焊盘GP1。
如稍后所描述的,第二栅电极G2位于一个第二MOS晶体管区域SMTA中的第二栅极沟槽TR2内。每个第二栅电极G2都通过插塞导电层PL电耦合至第二栅极布线层GIN2。第二栅极布线层GIN2电耦合至第二栅极焊盘GP2。
从而,每个第二MOS晶体管区域SMTA的第二栅电极G2通过插塞导电层PL和第二栅极布线层GIN2电耦合至第二栅极焊盘GP2。
如图4所示,半导体衬底SUB具有彼此相对的第一表面FS和第二表面SS。多个第一MOS晶体管元件FMTE和多个第二MOS晶体管元件SMTE形成在半导体衬底SUB中。
第一MOS晶体管元件FMTE和第二MOS晶体管元件SMTE均具有垂直沟槽栅极结构。
半导体衬底SUB在第一MOS晶体管区域FMTA中的第一表面FS中具有第一栅极沟槽TR1。此外,半导体衬底SUB在第二MOS晶体管区域SMTA中的第一表面FS中具有第二栅极沟槽TR2。
第一漏极区域DR、第一外延区域ER、第一基极区域BR1和第一源极区域SR1位于第一MOS晶体管区域FMTA中的半导体衬底SUB中。
第一漏极区域DR具有n型导电性,并且位于半导体衬底SUB的第二表面SS中。第一外延区域ER具有n型导电性,并且比第一漏极区域DR具有更低的n型杂质浓度。第一外延区域ER位于第一漏极区域DR的第一表面FS侧上,并且邻接在第一漏极区域DR上。
第一源极区域SR1具有n型导电性,并且位于半导体衬底SUB的第一表面FS中。第一基极区域BR1具有p型导电性,并且位于第一源极区域SR1和第一外延区域ER之间。第一基极区域BR1与第一源极区域SR1组成PN结,并且与第一外延区域ER组成PN结。
第一栅极沟槽TR1从第一表面FS延伸到达第一漏极区域DR。这使得导通状态电流沿着第一栅极沟槽TR1的侧壁和底壁流动。第一栅电极G1位于第一栅极沟槽TR1内。例如,第一栅电极G1有掺有杂质的多晶硅制成。第一栅极绝缘层GI1位于第一栅极沟槽TR1的壁面与第一栅电极G1之间。
第一栅极绝缘膜GI1具有第一较薄膜部分FGI1和第一较厚膜部分SGI1。第一较薄膜部分FGI1中的第一栅极绝缘层GI1的厚度小于第一较厚膜部分SGI1中的第一栅极绝缘层GI1的厚度。
第一较薄膜部分FGI1比第一较厚膜部分SGI1更接近第一表面FS。第一较薄膜部分FGI1从第一表面FS延伸到第一深度位置。第一较厚膜部分SGI1从第一深度位置延伸到第二深度位置,第二深度位置与第一深度位置更接近第二表面SS。第二深度位置与第一栅极沟槽TR1的底部的深度位置相同。
第一栅电极G1具有第一较宽部分FG1和第一较窄部分SG1。第一较宽部分FG1中的第一栅电极G1的宽度大于第一较窄部分SG1中的第一栅电极G1的宽度。
第一较宽部分FG1比第一较窄部分SG1更接近第一表面FS。第一较宽部分FG1从第一表面FS延伸到第一深度位置。第一较窄部分SG1从第一深度位置延伸到比第一深度位置更接近第二表面SS的位置。
第一栅极沟槽TR1具有第一较浅沟槽部分FTR1和第一较深沟槽部分STR1。第一较浅沟槽部分FTR1邻接在第一较薄膜部分FGI1上,并且第一较深沟槽部分STR1邻接在第一较厚膜部分SGI1上。第一较浅沟槽部分FTR1比第一较深沟槽部分STR1更接近第一表面FS。
以邻接在第一栅极沟槽TR1的侧壁上的方式,第一杂质区域AIR1位于第一MOS晶体管区域FMTA外。第一杂质区域AIR1具有p型导电性,并且位于第一表面FS中。第一杂质区域AIR1与第一外延区域ER组成PN结。第一杂质区域AIR1的底部(第二表面SS侧上的端部)与第一深度位置相比更接近第一表面FS。备选地,第一杂质区域AIR1的底部(第二表面SS侧上的端部)可以处于与第一深度位置相同的深度层级。如图3所示,在平面图中,第一杂质区域AIR1环绕第一栅极沟槽TR1。
如图4所示,第二漏极区域DR、第二外延区域ER、第二基极区域BR2和第二源极区域SR2位于第二MOS晶体管区域SMTA中的半导体衬底SUB中。
第二漏极区域DR具有n型导电性,并且位于半导体衬底SUB的第二表面SS中。第二漏极区域DR电耦合至第一漏极区域DR。第二漏极区域DR与第一漏极区域DR共享相同的杂质区域。
第二外延区域ER具有n型导电性,并且具有比第二漏极区域DR更低的n型杂质浓度。第二外延区域ER位于第二漏极区域DR的第一表面FS侧上,并且邻接在第二漏极区域DR上。
第二外延区域ER电耦合至第一外延区域ER。第二外延区域ER与第一外延区域ER共享相同的杂质区域。
第二源极区域SR2具有n型导电性,并且位于半导体衬底SUB的第一表面FS中。第二基极区域BR2具有p型导电性,并且位于第二源极区域SR2和第二外延区域ER之间。第二基极区域BR2与第二源极区域SR2组成PN结,并且与第二外延区域ER组成PN结。
第二栅极沟槽TR2从第一表面FS延伸到达第二漏极区域DR。这使得导通状态电流沿着第二栅极沟槽TR2的侧壁和底壁流动。第二栅电极G2位于第二栅极沟槽TR2中。例如,第二栅电极G2由掺有杂质的多晶硅制成。第二栅极绝缘膜GI2位于第二栅极沟槽TR2的壁面和第二栅电极G2之间。
第二栅极绝缘膜GI2具有第二较薄膜部分FGI2和第二较厚膜部分SGI2。第二较薄膜部分FGI2中的第二栅极绝缘层GI2的厚度小于第二较厚膜部分SGI2中的第二栅极绝缘层GI2的厚度。
第二较薄膜部分FGI2比第二较厚膜部分SGI2更接近第一表面FS。第二较薄膜部分FGI2从第一表面FS延伸到第一深度位置。第二较厚膜部分SGI2从第一深度位置延伸到第二深度位置,第二深度位置比第一深度位置更接近第二表面SS。第二深度位置与第二栅极沟槽TR2的底部的深度位置相同。
第二栅电极G2具有第二较宽部分FG2和第二较窄部分SG2。第二较宽部分FG2中的第二栅电极G2的宽度大于第二较窄部分SG2中的第二栅电极G2的宽度。
第二较宽部分FG2比第二较窄部分SG2更接近第一表面FS。第二较宽部分FG2从第一表面FS延伸到第一深度位置。第二较窄部分SG2从第一深度位置延伸到比第一深度位置更接近第二表面SS的位置。
第二栅极沟槽TR2具有第二较浅沟槽部分FTR2和第二较深沟槽部分STR2。第二较浅沟槽部分FTR2邻接在第二较薄膜部分FGI2上,并且第二较深沟槽部分STR2邻接在第二较厚膜部分SGI2上。第二较浅沟槽部分FTR2比第二较深沟槽部分STR2更接近第一表面FS。
第一较薄膜部分FGI1延伸到的第一深度位置几乎与第二较薄膜部分FGI2延伸到的第一深度位置相同。第一较厚膜部分SGI1延伸到的第二深度位置几乎与第二较厚膜部分SGI2延伸到的第二深度位置相同。第二表面SS侧上的第一较窄部分SG1的端部的深度位置几乎与第二表面SS侧上的第二较窄部分SG2的端部的深度位置相同。
以邻接在第二栅极沟槽TR2的侧壁上的方式,第二杂质区域AIR2位于第二MOS晶体管区域SMTA外。第二杂质区域AIR2具有p型导电性,并且位于第一表面FS中。第二杂质区域AIR2与第二外延区域ER组成PN结。第二杂质区域AIR2的底部(第二表面SS侧上的端部)与第一深度位置相比更接近第一表面FS。备选地,第二杂质区域AIR2的底部(第二表面SS侧上的端部)可以与第一深度位置处于相同的深度层级。如图3所示,在平面图中,第二杂质区域AIR2环绕第二栅极沟槽TR2。
第一杂质区域AIR1和第二杂质区域AIR2相互分离。具体地,在第一MOS晶体管区域FMTA和第二MOS晶体管区域SMTA之间的分离区域SPR中,第一杂质区域AIR1和第二杂质区域AIR2利用它们之间的外延区域ER(第一或第二外延区域ER)相互分离。
层间绝缘膜II1位于半导体衬底SUB的第一表面FS之上。在层间绝缘膜II1中制造多个接触孔CH,以便从层间绝缘膜II1的上表面到达半导体衬底SUB的第一表面FS。接触孔CH具有相同深度,并且从半导体衬底SUB的第一表面FS朝向第二表面SS延伸。例如,由钨(W)制成的插塞导电层PL埋入每个接触孔CH中。
第一MOS晶体管区域FMTA中的每个接触孔CH从半导体衬底SUB的第一表面FS经过第一源极区域SR1并到达第一基极区域BR1。因此,埋入第一MOS晶体管区域FMTA中的每个接触孔CH的插塞导电层PL邻接在第一源极区域SR1和第一基极区域BR1上。
插塞导电层PL还埋入从层间绝缘膜II1的上表面延伸并到达第一杂质区域AIR1的每个接触孔CH。
以位于第一MOS晶体管区域FMTA正上方的方式,第一源电极S1位于层间绝缘层II1的上表面之上。第一源电极S1耦合至埋入第一MOS晶体管区域FMTA中的每个接触孔CH的插塞导电层PL以及埋入到达第一杂质区域AIR1的每个接触孔CH的插塞导电层PL。从而,第一源电极S1通过插塞导电层PL电耦合至第一源极区域SR1、第一基极区域BR1和第一杂质区域AIR1。第一杂质区域AIR1被制造为具有与第一源电极S1相同的电位(第一源极电位)。
第一源电极S1被定位为在多个第一MOS晶体管元件FMTE正上方,并且电耦合至第一MOS晶体管元件FMTE。
第二MOS晶体管区域SMTA中的每个接触孔CH从半导体衬底SUB的第一表面FS经过第二源极区域SR2并到达第二基极区域BR2。因此,埋入第二MOS晶体管区域SMTA中的每个接触孔CH的插塞导电层PL邻接在第二源极区域SR2和第二基极区域BR2上。
插塞导电层PL还埋入从层间绝缘层II2的上表面延伸并到达第二杂质区域AIR2的每个接触孔CH中。
以位于第二MOS晶体管区域SMTA正上方的方式,第二源电极S2位于层间绝缘膜层II1的上表面之上。第二源电极S2耦合至埋入第二MOS晶体管区域SMTA中的每个接触孔CH的插塞导电层PL以及埋入到达第二杂质区域AIR2的每个接触孔CH的插塞导电层PL。从而,第二源电极S2通过插塞导电层PL电耦合至第二源极区域SR2、第二基极区域BR2和第二杂质区域AIR2。第二杂质区域AIR2被制造为具有与第二源极区域S2相同的电位(第二源极电位)。
第二源电极S2位于多个第二MOS晶体管元件SMTE正上方,并且电耦合至第二MOS晶体管元件SMTE。
层间绝缘层II2形成在层间绝缘层II1之上,以便覆盖第一源电极S1和第二源电极S2。背电极(漏电极)不形成在半导体衬底SUB的第二表面SS中。
接下来,将参照图4至图14描述根据第一实施例的半导体器件的制造方法。如图5所示,通过外延生长,n-外延区域ER形成在漏极区域DR之上。从而,形成半导体衬底SUB,其中漏极区域DR位于第二表面SS中且n-外延区域ER位于第一表面FS中。漏极区域DR是变为第一漏极区域和第二漏极区域的区域。外延区域ER是变为第一外延区域和第二外延区域的区域。
此后,通过常规的光刻蚀技术和蚀刻技术,在第一MOS晶体管区域FMTA的第一表面FS中制造第一较浅沟槽部分FTR1,并且在第二MOS晶体管区域SMTA的第一表面FS中制造第二较浅沟槽部分FTR2。
如图6所示,以覆盖半导体衬底SUB的第一表面FS以及第一较浅沟槽部分FTR1和第二较浅沟槽部分FTR2的壁面的方式形成掩膜层ML1。例如,掩膜层ML1是氮化硅膜。然后,选择性地去除掩膜层ML1。从而,从掩膜层ML1部分地暴露第一较浅沟槽部分FTR1的底部和第二较浅沟槽部分FTR2的底部。
此后,通过蚀刻去除从掩膜层ML1暴露的第一较浅沟槽部分FTR1的底部和第二较浅沟槽部分FTR2的底部的部分。
如图7所示,作为上述蚀刻的结果,第一较深沟槽部分STR1被制造位于第一较浅沟槽部分FTR1下方。类似地,第二较深沟槽部分STR2被制造位于第二较浅沟槽部分FTR2下方。形成第一较深沟槽部分STR1,以便具有比第一较浅沟槽部分FTR1小的宽度。形成第二较深沟槽部分STR2,以便具有比第二较浅沟槽部分FTR2小的宽度。第一较浅沟槽部分FTR1和第一较深沟槽部分STR1配置第一栅极沟槽TR1,并且第二较浅沟槽部分FTR2和第二较深沟槽部分STR2配置第二栅极沟槽TR2。
如图8所示,在掩膜层ML1保持不变的同时在氧化气氛中氧化半导体衬底SUB。通过该氧化,从掩膜层ML1暴露的第一较深沟槽部分STR1和第二较深沟槽部分STR2的壁面被氧化。从而,作为氧化硅膜的绝缘层SGI1形成在第一较深沟槽部分STR1的壁面上,并且作为氧化硅膜的绝缘层SGI2形成在第二较深沟槽部分STR2的壁面上。之后,通过蚀刻选择性地移除掩膜层ML1。
如图9所示,作为蚀刻上述掩膜层ML1的结果,暴露半导体衬底SUB的第一表面FS以及第一较浅沟槽部分FTR1的壁面和第二较浅沟槽部分FTR2的壁面。
如图10所示,第一较浅沟槽部分FTR1的壁面和第二较浅沟槽部分FTR2的壁面被氧化。从而,作为氧化硅膜的绝缘层FGI1形成在第一较浅沟槽部分FTR1的壁面上,并且作为氧化硅膜的绝缘层FGI2形成在第二较浅沟槽部分FTR2的壁面上。
形成绝缘层FGI1以便薄于绝缘层SGI1。绝缘层FGI1和绝缘层SGI1组成第一栅极绝缘层GI1。形成绝缘层FGI2以便薄于绝缘层SGI2。绝缘层FGI2和绝缘层SGI2组成第二栅极绝缘层GI2。
如图11所示,第一栅电极G1形成在第一栅极沟槽TR1内。形成第一栅电极G1,使得埋入第一较浅沟槽部分FTR1的部分FG1具有的宽度大于埋入第一较深沟槽部分STR1的部分SG1的宽度。
类似地,第二栅电极G2形成在第二栅极沟槽TR2内。形成第二栅电极G2,使得埋入第二较浅沟槽部分FTR2的部分FG2具有的宽度大于埋入第二较深沟槽部分STR2的部分SG2的宽度。
如图12所示,例如通过离子注入技术,p型杂质被注入到半导体衬底SUB的第一表面FS中。从而,第一基极区域BR1、第二基极区域BR2、第一杂质区域AIR1和第二杂质区域AIR2形成在半导体衬底SUB的第一表面FS中。在相同的离子注入步骤中形成第一基极区域BR1、第二基极区域BR2、第一杂质区域AIR1和第二杂质区域AIR2。
第一基极区域BR1位于第一MOS晶体管区域FMTA中的第一栅极沟槽TR1之间的第一表面FS中。以邻接在第一栅极沟槽TR1的侧壁上的方式,第一杂质区域AIR1位于第一MOS晶体管区域FMTA外的第一表面FS中。
第二基极区域BR2位于第二MOS晶体管区域SMTA中的第二栅极沟槽TR2之间的第一表面FS中。以邻接在第二栅极沟槽TR2的侧壁上的方式,第二杂质区域AIR2位于第二MOS晶体管区域SMTA外的第一表面FS中。
如图13所示,例如通过离子注入技术,n型杂质被注入半导体衬底SUB的第一表面FS中。从而,第一源极区域SR1和第二源极区域SR2形成在半导体衬底SUB的第一表面FS中。
第一源极区域SR1位于第一MOS晶体管区域FMTA中的第一栅极沟槽TR1之间的第一表面FS中,以与第一基极区域BR1组成PN结。第二源极区域SR2位于第二MOS晶体管区域SMTA中的第二栅极沟槽TR2之间的第一表面FS中,以与第二基极区域BR2组成PN结。
从而,形成包括第一漏极区域DR、第一源极区域SR1和第一栅电极G1的第一MOS晶体管元件FMTE。类似地,形成包括第二漏极区域DR、第二源极区域SR2和第二栅电极G2的第二MOS晶体管元件SMTE。
如图14所示,层间绝缘层II1形成在半导体衬底SUB的第一表面FS之上。然后,通过常规的光刻蚀技术和蚀刻技术在层间绝缘层II1中制造多个接触孔CH。
第一MOS晶体管区域FMTA中的接触孔CH被制造,以便穿过第一源极区域SR1并到达第一基极区域BR1。第二MOS晶体管区域SMTA中的接触孔CH被制造,以便穿过第二源极区域SR2并到达第二基极区域BR2。
此外,制造到达第一杂质区域AIR1的接触孔CH和到达第二杂质区域AIR2的接触孔CH。
如图4所示,第一源电极S1和第二源电极S2形成在层间绝缘层II1的上表面之上。第一源电极S1电耦合至第一源极区域SR1、第一基极区域BR1和第一杂质区域AIR1。第二源电极S2电耦合至第二源极区域SR2、第二基极区域BR2和第二杂质区域AIR2。
此后,层间绝缘层II2形成在层间绝缘层II1之上,以便覆盖第一源电极S1和第二源电极S2。由此,制造了根据第一实施例的半导体器件。
接下来,将通过与图15所示的比较示例1、图17所示的比较示例2和图18所示的比较示例3的比较来解释第一实施例的效果。
在图15所示的第一比较示例1中,背电极(漏电极)形成在半导体衬底SUB的背面上。在图15中,为了说明的方便没有示出晶体管。
在比较示例1中,导通状态电流沿着图中的箭头垂直地从半导体衬底SUB的正面侧上的第二源电极S2流向背电极DE,然后在背电极DE中水平地流动,然后垂直地从背电极DE流向第一源电极S1。比较示例1具有导通状态电流路径较长并且不容易降低导通电阻的缺陷。
导通电阻主要包括以下组成部分:沟道区域的电阻、外延区域的电阻和衬底区域的电阻(当导通状态电流垂直流动时)以及金属电阻(当在背电极DE中流动时)。为了减小电阻部分,期望使半导体衬底SUB的厚度尽可能小。然而,这样做会使得半导体衬底SUB容易断裂或弯曲。此外,如果低阻背电极DE由厚金属形成,则其形成工艺会较为复杂并且在成本方面是不利的。
为了避免上述缺陷,日本未审查专利申请公开第2006-147700号公开了第一MOS晶体管元件和第二MOS晶体管元件被布置为在一个芯片中彼此交替相邻的结构。在该结构中,第一MOS晶体管元件和第二MOS晶体管元件之间的导通状态电流不在背电极中流动而是沿着沟槽底部流动。这提供了不需要形成低阻背电极的优势。然而,该结构具有以下缺陷:由于沟槽底部包括外延层,所以高阻外延区域的电阻被添加到水平路径中的导通电阻。
在第一MOS晶体管元件和第二MOS晶体管元件被交替布置的结构中,可以使导通电阻的增加最小化。然而,源电极必须形成在晶体管的水平尺寸内,这是困难且不现实的。此外,随着朝向更高密度的单元缩小的增加趋势,更加难以形成源电极。
为了避免该问题,本发明的发明人设想了以下结构:一个第一源电极电耦合至多个第一MOS晶体管元件,并且一个第二源电极电耦合至多个第二MOS晶体管元件,并且第一源电极和第二源电极交替布置。
本发明的发明人进行了仿真以便查看导通电阻如何根据不具有背电极的MOS晶体管的划分数量而变化。图16示出了仿真结果。
如图16所示,当MOS晶体管的划分数量较大时,衬底区域的电阻较低。当划分数量太大时,沟道区域的电阻和外延区域的电阻增加,尽管衬底区域的电阻降低。这是因为第一MOS晶体管区域和第二MOS晶体管区域之间的分离的临时设置宽度较大,由此当划分数量较大时,MOS晶体管区域减小。
为了增加划分数量,重要的是减小第一MOS晶体管区域和第二MOS晶体管区域之间的分离的宽度。
在图17所示的比较示例2的结构中,具有浮置电位的杂质区域AIR被定为在分离区域SPR中的第一表面FS中。在比较示例2的结构中,当第一MOS晶体管截止时,高漏极-源极电压被施加于第一MOS晶体管区域FMTA的最外边的较薄的第一较薄膜部分FGI1(区域R1)。为此,第一较薄膜部分FGI1不能被减薄,并且难以减小分离区域SPR的宽度。
在图18所示比较示例3的结构中,在分离区域SPR中的第一表面FS中制造沟槽TR3,并且绝缘层BI和导电层BE埋入沟槽TR3中。施加于较薄的第一较薄部分FGI1(区域R2)的电场可以通过加厚绝缘层BI并且使导电层BE具有源极电位来缓解。然而,需要形成沟槽TR3、绝缘层BI和导电层BE,这产生了增加了制造步骤的数量并且分离宽度应该较大的问题。
相反,在第一实施例中,如图4所示,在分离区域SPR中的第一表面FS中,电耦合至第一源电极S1的第一杂质区域AIR1邻接在第一栅极沟槽TR1的第一较浅沟槽部分FTR1的壁面上。换句话说,具有源极电位的第一杂质区域AIR1邻接在薄的第一较薄膜部分FGI1上。
从而,将在第一MOS晶体管元件FMTE截止的情况下施加的高漏极-源极电压被施加在具有漏极电位的外延区域ER与具有源极电位的第一杂质区域AIR1之间的结。因此,在结处生成的耗尽层共享电场。从而,只有栅极-源极电位被施加给第一栅极绝缘层GI1,从而允许第一栅极绝缘层GI1的第一较薄膜部分FGI1被减薄。因此,可以降低导通电阻。
此外,由于可以减薄第一栅极绝缘层GI1的较薄的第一较薄膜部分FGI1,所以可以减小第一MOS晶体管区域FMTA与第二MOS晶体管区域SMTA之间的分离的宽度。当分离宽度较小时,划分的数量可以较大,以根据图16所示的仿真结果降低导通电阻。换句话说,当划分的数量较大时,从第一MOS晶体管区域FMTA到第二MOS晶体管区域SMTA的电流流动距离缩短,由此导通电阻降低。
此外,由于可以如上所述降低导通电阻,所以不需要在第二表面SS上形成由金属制成的背电极(漏电极)。
如图12所示,可以在与第一基极区域BR1相同的步骤中形成第一杂质区域AIR1。这消除了如图18所示比较示例3增加步骤数量的需求,并且简化了根据第一实施例的半导体器件的制造方法。
可以进一步通过以与第一MOS晶体管FMTR相同的方式形成第二MOS晶体管SMTR来减小第一MOS晶体管区域FMTA与第二MOS晶体管区域SMTR之间的分离的宽度。
第一杂质区域AIR1和第二杂质区域AIR2彼此分离。因此,第一杂质区域AIR1可以具有与第一源极区域SR1相同的电位,并且第二杂质区域AIR2可以具有与第二源极区域SR2相同的电位。这意味着,可以在不同的电位下控制第一杂质区域AIR1和第二杂质区域AIR2。
从第一表面FS开始,第一杂质区域AIR1具有与第一基极区域BR1相同的深度,并且具有与第一基极区域BR1相同的杂质浓度。这使得可以在同一步骤中形成第一杂质区域AIR1和第一基极区域BR1,从而如上所述简化根据第一实施例的半导体器件的制造方法。
从第一表面FS开始,第二杂质区域AIR2具有与第二基极区域BR2相同的深度,并且具有与第二基极区域BR2相同的杂质浓度。这使得可以在同一步骤中形成第二杂质区域AIR2和第二基极区域BR2,从而如上所述简化根据第一实施例的半导体器件的制造方法。第二实施例
如图19所示,根据第二实施例的半导体器件与图4所示根据第一实施例的半导体器件在结构上的不同在于:第一杂质区域AIR1、第二杂质区域AIR2和插塞导电层PL。
从第一表面FS开始,第一杂质区域AIR1具有比第一基极区域BR1更大的深度,并且具有比第一基极区域BR1更低的杂质浓度。第一杂质区域AIR1可以从第一表面FS延伸得深于第一深度位置,或者延伸到与第一深度位置相同的深度位置。
从第一表面FS开始,第二杂质区域AIR2具有比第二基极区域BR2更大的深度,并且具有比第二基极区域BR2更低的杂质浓度。第二杂质区域AIR2可以从第一表面FS延伸得深于第一深度位置,或者延伸到与第一深度位置相同的深度位置。
第一杂质区域AIR1和第二杂质区域AIR2延伸到相同的深度位置。
耦合第一源电极S1和第一源极区域SR1的插塞导电层PL(第一导电层)从第一表面FS开始比耦合第一源电极S1和第一杂质区域AIR1的插塞导电层PL(第二导电层)更深地延伸到半导体衬底SUB中。
耦合第二源电极S2和第二源极区域SR2的插塞导电层PL从第一表面FS开始比耦合第二源电极S2和第二杂质区域AIR2的插塞导电层PL更深地延伸到半导体衬底SUB中。
除上述第二实施例外的元件实际上与第一实施例相同,并且与第一实施例相同的元件由相同的参考标号表示,并且这里不再重复描述。
接下来,将参照图19至图24描述根据第二实施例的半导体器件的制造方法。
在根据第二实施例的半导体器件的制造方法中,首先,执行与根据第一实施例的图5至图11所示相同的步骤。此后,如图20所示,例如通过离子注入技术,p型杂质被注入到半导体衬底SUB的第一表面FS中。从而,在半导体衬底SUB的第一表面FS中形成第一杂质区域AIR1和第二杂质区域AIR2。在相同的离子注入步骤中将第一杂质区域AIR1和第二杂质区域AIR2形成为相互分离。
以邻接在第一栅极沟槽TR1的侧壁上的方式,第一杂质区域AIR1被定位在第一MOS晶体管区域FMTA外的第一表面FS中。以邻接在第二栅极沟槽TR2的侧壁上的方式,第二杂质区域AIR2被定位在第二MOS晶体管区域SMTA外的第一表面FS中。
如图21所示,例如通过离子注入技术,p型杂质被注入半导体衬底SUB的第一表面FS中。从而,第一基极区域BR1和第二基极区域BR2形成在半导体衬底SUB的第一表面FS中。在相同的离子注入步骤中形成第一基极区域BR1和第二基极区域BR2。
第一基极区域BR1被定位在第一MOS晶体管区域FMTA中的第一栅极沟槽TR1之间的第一表面FS中。形成第一基极区域BR1,以便与第一杂质区域AIR1相比具有更小的深度和更低的p型杂质浓度。
第二基极区域BR2被定位在第二MOS晶体管区域SMTA中的第二栅极沟槽TR2之间的第一表面FS中。形成第二基极区域BR2,以便与第二杂质区域AIR2相比具有更小的深度和更低的p型杂质浓度。
如图22所示,例如通过离子注入技术,n型杂质被注入到半导体衬底SUB的第一表面FS中。从而,在半导体衬底SUB的第一表面FS中形成第一源极区域SR1和第二源极区域SR2。
第一源极区域SR1被定位在第一MOS晶体管区域FMTA中的第一栅极沟槽TR1之间的第一表面FS中,以与第一基极区域BR1组成PN结。第二源极区域SR2被定位在第一MOS晶体管区域SMTA中的第二栅极沟槽TR2之间的第一表面FS中,以与第二基极区域BR2组成PN结。
从而,形成包括第一漏极区域DR、第一源极区域SR1和第一栅电极G1的第一MOS晶体管元件FMTE。类似地,形成包括第二漏极区域DR、第二源极区域SR2和第二栅电极G2的第二MOS晶体管元件SMTE。
如图23所示,层间绝缘层II1形成在半导体衬底SUB的第一表面FS之上。然后,通过常规的光刻蚀技术和蚀刻技术,在层间绝缘层II1中制造多个接触孔CH。接触孔CH包括到达第一杂质区域AIR1的接触孔CH和到达第二杂质区域AIR2的接触孔CH。插塞导电层PL被埋入这些接触孔CH中的每一个。
如图24所示,通过常规的光刻蚀技术和蚀刻技术,在层间绝缘层II1中制造多个接触孔CH。接触孔CH包括穿过第一源极区域SR1并到达第一基极区域BR1的接触孔CH以及穿过第二源极区域SR2并到达第二基极区域BR2的接触孔CH。插塞导电层PL被埋入这些接触孔CH中的每一个中。
到达第一源极区域SR1的接触孔CH从第一表面FS开始比到达第一杂质区域AIR1的接触孔CH更深地延伸到半导体衬底SUB中。到达第二源极区域SR2的接触孔CH从第一表面FS开始比到达第二杂质区域AIR2的接触孔CH更深地延伸到半导体衬底SUB中。
如图19所示,第一源电极S1和第二源电极S2形成在层间绝缘层II1的上表面之上。第一源电极S1电耦合至第一源极区域SR1、第一基极区域BR1和第一杂质区域AIR1。第二源电极S2电耦合至第二源极区域SR2、第二基极区域BR2和第二杂质区域AIR2。
此后,以覆盖第一源电极S1和第二源电极S2的方式,层间绝缘层II1形成在层间绝缘层II1之上。由此,制造根据第二实施例的半导体器件。
接下来,将解释根据第二实施例的半导体器件的效果。
在第二实施例中,如图19所示,在第一MOS晶体管区域FMTA外的第一表面FS中,电耦合至第一源电极S1的第一杂质区域AIR1邻接在第一栅极沟槽TR1的第一较浅沟槽部分FTR1的壁面上。换句话说,具有源极电位的第一杂质区域AIR1邻接在薄的第一较薄膜部分FGI1上。这带来与第一实施例相同的效果。
此外,第一杂质区域AIR1形成为具有比第一基极区域BR1更大的深度以及更低的p型杂质浓度。从而,消耗层容易从第一杂质区域AIR1与外延区域ER之间的结延伸到第一杂质区域AIR中,从而改进了击穿电压。
此外,到达第一杂质区域AIR1的接触孔CH被制造,以便邻接在第一表面FS上并且不从第一表面FS开始较深地延伸到半导体衬底SUB中。因此,即使耗尽层延伸到第一杂质区域AIR中,耗尽层也被限制与接触孔CH中的插塞导电层PL接触。这也改进了击穿电压。
由于第二杂质区域AIR2具有与第一杂质区域AIR1相同的结构,所以第二杂质区域AIR2也带来与第一杂质区域AIR1相同的有利效果。
第三实施例
如图25所示,根据第三实施例的半导体器件与根据第一实施例的半导体器件在结构上的不同在于:第一栅极沟槽TR1和第二栅极沟槽TR2不同于第一实施例,并且设置有p-柱区域SJ1、SJ2、SJ3、SJ4和SJ5。
在第三实施例中,第一栅极沟槽TR1不到达漏极区域DR。第一栅极沟槽TR1的底部位于外延区域ER内。第一栅极沟槽TR1中的第一栅极绝缘层GI1具有单一厚度。第一栅电极G1具有单一宽度。
第二栅极沟槽TR2不到达漏极区域DR。第二栅极沟槽TR2的底部位于外延区域ER内。第二栅极沟槽TR2中的第二栅极绝缘层GI2具有单一厚度。第二栅电极G2具有单一宽度。
p-柱区域SJ1、SJ2、SJ3、SJ4和SJ5均具有比第一基极区域BR1、第二基极区域BR2、第一杂质区域AIR1和第二杂质区域AIR2中的每一个的p型杂质浓度低的p型杂质区域。
p-柱区域SJ1(第一柱区域)耦合至第一基极区域BR1,并且从第一基极区域BR1开始朝向第二表面SS延伸。p-柱区域SJ2(第二柱区域)耦合至第二基极区域BR2,并且从第二基极区域BR2开始朝向第二表面SS延伸。
p-柱区域SJ3耦合至第一杂质区域AIR1,并且从第一杂质区域AIR1开始朝向第二表面SS延伸。p-柱区域SJ4耦合至第二杂质区域AIR2,并且从第二杂质区域AIR2开始朝向第二表面SS延伸。
p-柱区域SJ5位于第一MOS晶体管区域FMTA与第二MOS晶体管区域SMTA之间的分离区域SPR中的外延区域ER中。p-柱区域SJ5被外延区域ER环绕。p-柱区域SJ5具有浮置电位。
第三实施例中除上述之外的元件与第一实施例几乎相同,并且与第一实施例相同的元件由相同的参考标号表示,并且这里不再重复描述。
接下来,将解释根据第三实施例的半导体器件的效果。
在第三实施例中,如图25所示,在第一MOS晶体管区域FMTA外的第一表面FS中,电耦合至第一源电极S1的第一杂质区域AIR1邻接在第一栅极沟槽TR1的第一较浅沟槽部分FTR1的壁面上。换句话说,具有源极电位的第一杂质区域AIR1邻接在较薄的第一较薄膜部分FGI1上。这带来与第一实施例相同的有利效果。
由于第二杂质区域AIR2具有与第一杂质区域AIR1相同的结构,所以第二杂质区域AIR2也带来与第一杂质区域AIR1相同的有利效果。
柱区域SJ1-SJ5在垂直方向(从第一表面FS朝向第二表面SS的方向)上延伸到n-外延区域ER中。因此,柱区域SJ1-SJ5和n-外延区域ER可以组成超级结结构,从而减小了导通电阻并且改进了击穿电压。
第四实施例
如图26所示,根据第四实施例的半导体器件与根据第三实施例的半导体器件在结构上的不同在于:多个(两个或多个)p-柱区域SJ5被设置在分离区域SPR中。
第四实施例中除上述之外的元件与第三实施例几乎相同,并且与第三实施例相同的元件由相同的参考标号表示,并且这里不再重复描述。
第四实施例与第三实施例相比可以更多地改进击穿电压。
第五实施例
如图27和图28所示,根据第五实施例的半导体器件与根据第三实施例的半导体器件在结构上的不同在于:没有设置柱区域SJ2和SJ4。
在第五实施例中,第二基极区域BR2的整个下表面以及第二杂质区域AIR2的整个下表面均与外延区域ER组成PN结。
第五实施例中除上述之外的元件与第三实施例几乎相同,并且与第三实施例相同的元件由相同的参考标号表示,这里不再重复描述。
接下来,将参照图27至图35描述根据第五实施例的半导体器件的制造方法。
如图27所示,通过外延生长,n-外延区域ER形成在漏极区域DR之上。从而,形成半导体衬底SUB,其中漏极区域DR被定位在第二表面SS中,并且n-外延区域ER被定位在第一表面FS中。漏极区域DR是变为第一漏极区域和第二漏极区域的区域。外延区域ER是变为第一外延区域和第二外延区域的区域。
此后,如图29所示,通过常规的光刻蚀技术和蚀刻技术,在第一MOS晶体管区域FMTA中的第一表面FS中制造第一栅极沟槽TR1,并且在第二MOS晶体管区域SMTA中的第一表面FS中制造第二栅极沟槽TR2。
如图30所示,在第一栅极沟槽TR1中形成第一栅极绝缘层GI1和第一栅电极G1。类似地,在第二栅极沟槽TR2中形成第二栅极绝缘层GI2和第二栅电极G2。
在相同步骤中形成第一栅极绝缘层GI1和第二栅极绝缘层GI2。此外,在相同步骤中形成第一栅电极G1和第二栅电极G2。
如图31所示,例如通过离子注入技术,在半导体衬底SUB的第一表面FS中注入p型杂质。从而,在半导体衬底SUB的第一表面FS中形成第一基极区域BR1、第二基极区域BR2、第一杂质区域AIR1和第二杂质区域AIR2。在相同的离子注入步骤中形成第一基极区域BR1、第二基极区域BR2、第一杂质区域AIR1和第二杂质区域AIR2。
第一基极区域BR1被定位在第一MOS晶体管区域FMTA中的第一栅极沟槽TR1之间的第一表面FS中。以邻接在第一栅极沟槽TR1的侧壁上的方式,第一杂质区域AIR1被定位在第一MOS晶体管区域FMTA外的第一表面FS中。
第二基极区域BR2被定位在第二MOS晶体管区域SMTA中的第二栅极沟槽TR2之间的第一表面FS中。以邻接在第二栅极沟槽TR2的侧壁上的方式,第二杂质区域AIR2被定位在第二MOS晶体管区域SMTA外的第一表面FS中。
如图32所示,例如通过离子注入技术,在半导体衬底SUB中注入p型杂质。从而,在半导体衬底SUB中形成柱区域SJ1、SJ3和SJ5。在相同的离子注入步骤中形成柱区域SJ1、SJ3和SJ5。
在第二MOS晶体管区域SMTA和第二杂质区域AIR2被整体掩蔽的同时执行该离子注入步骤。因此,没有柱区域形成在第二基极区域BR2和第二杂质区域AIR2下方。
如图33所示,例如通过离子注入技术,在半导体衬底SUB的第一表面FS中注入n型杂质。从而,在半导体衬底SUB的第一表面FS中形成第一源极区域SR1和第二源极区域SR2。
第一源极区域SR1被定位在第一MOS晶体管区域FMTA中的第一栅极沟槽TR1之间的第一表面FS中,以与第一基极区域BR1组成PN结。第二源极区域SR2被定位在第二MOS晶体管区域SMTA中的第二栅极沟槽TR2之间的第一表面FS中,以与第二基极区域BR2组成PN结。
如图34所示,层间绝缘层II1形成在半导体衬底SUB的第一表面FS之上。此后,通过常规的光刻蚀技术和蚀刻技术,在层间绝缘层II1中制造多个接触孔CH。
形成第一MOS晶体管区域FMTA中的接触孔CH,以穿过第一源极区域SR1并到达第一基极区域BR1。形成第二MOS晶体管区域SMTA中的接触孔CH,以穿过第二源极区域SR2并到达第二基极区域BR2。
此外,制造达到第一杂质区域AIR1的接触孔CH和到达第二杂质区域AIR2的接触孔CH。
如图35所示,插塞导电层PL形成在每个接触孔CH中。此后,第一源电极S1和第二源电极S2形成在层间绝缘层II1的上表面之上。
第一源电极S1电耦合至第一源极区域SR1、第一基极区域BR1和第一杂质区域AIR1。第二源电极S2电耦合至第二源极区域SR2、第二基极区域BR2和第二杂质区域AIR2。
此后,如图27所示,以覆盖第一源电极S1和第二源电极S2的方式,层间绝缘层II2形成在层间绝缘层II之上。由此,制造根据第五实施例的半导体器件。
在第五实施例中,由于没有设置柱区域SJ2和SJ4,所以第二MOS晶体管区域SMTA中的击穿电压低于第三实施例,而导通电阻低于第三实施例。
根据上述每个实施例的半导体器件SED不限于半导体芯片;备选地,其可以为晶圆或树脂密封封装的形式。
此外,第一MOS晶体管FMTA和第二MOS晶体管SMTR可以由MIS(金属绝缘体半导体)晶体管代替。
至此已经假设第一MOS晶体管FMTA和第二MOS晶体管SMTR为n沟道类型而描述了实施例,但是备选地,它们可以为p沟道类型。如果它们是p沟道类型,则第一杂质区域AIR1和第二杂质区域AIR2具有n型导电性。
至此已经参照优选实施例详细解释了发明人做出的本发明。然而,本发明不限于此,明显地,在不背离本发明的精神的情况下可以各种方式修改这些细节。
Claims (15)
1.一种半导体器件,具有双向开关,所述半导体器件包括:
半导体衬底,具有彼此相对的第一表面和第二表面,并且具有从所述第一表面朝向所述第二表面延伸的第一栅极沟槽;
第一晶体管元件,包括位于所述第二表面中的第一导电类型的第一漏极区域、位于所述第一表面中的所述第一导电类型的第一源极区域、以及位于所述第一栅极沟槽内的第一栅电极,并且被包括在所述双向开关中;以及
第二导电类型的第一杂质区域,所述第一杂质区域在用于所述第一晶体管元件的区域外邻接在所述第一栅极沟槽的侧壁上,并且电耦合至所述第一源极区域。
2.根据权利要求1所述的半导体器件,
所述半导体衬底具有从所述第一表面朝向所述第二表面延伸的第二栅极沟槽;
所述半导体器件还包括:
第二晶体管元件,包括位于所述第二表面中的所述第一导电类型的第二漏极区域、位于所述第一表面中的所述第一导电类型的第二源极区域、以及位于所述第二栅极沟槽内的第二栅电极,并且被包括在所述双向开关中;以及
所述第二导电类型的第二杂质区域,所述第二杂质区域在用于所述第二晶体管元件的区域外邻接在所述第二栅极沟槽的侧壁上,并且电耦合至所述第二源极区域。
3.根据权利要求2所述的半导体器件,其中所述第一杂质区域和所述第二杂质区域彼此分离。
4.根据权利要求1所述的半导体器件,还包括:
所述第二导电类型的基极区域,与所述第一源极区域组成PN结,并且面对所述第一栅电极且与所述第一栅电极绝缘,
其中所述第一杂质区域距离所述第一表面具有与所述基极区域相同的深度,并且具有与所述基极区域相同的杂质浓度。
5.根据权利要求1所述的半导体器件,还包括:
所述第二导电类型的基极区域,与所述第一源极区域组成PN结,并且面对所述第一栅电极且与所述第一栅电极绝缘,
其中所述第一杂质区域距离所述第一表面具有大于所述基极区域的深度,并且具有低于所述基极区域的杂质浓度。
6.根据权利要求5所述的半导体器件,还包括:
源极电极,位于所述第一表面之上;
第一导电层,耦合至所述源极电极和所述第一源极区域;以及
第二导电层,耦合至所述源极电极和所述第一杂质区域,
其中所述第一导电层从所述第一表面比所述第二导电层更深地延伸到所述半导体衬底中。
7.根据权利要求5所述的半导体器件,还包括:
栅极绝缘层,位于所述第一栅极沟槽的壁面与所述第一栅电极之间,
其中所述栅极绝缘层在从所述第一表面到第一深度的第一区域中具有第一厚度,并且在从所述第一深度到更接近所述第二表面的第二深度的第二区域中具有第二厚度,所述第二厚度大于所述第一厚度,并且
其中所述第一杂质区域从所述第一表面延伸到比所述第一深度更接近所述第二表面的深度位置。
8.根据权利要求2所述的半导体器件,还包括:
所述第二导电类型的第一基极区域,与所述第一源极区域组成PN结,并且面对所述第一栅电极且与所述第一栅电极绝缘;
所述第二导电类型的第二基极区域,与所述第二源极区域组成PN结,并且面对所述第二栅电极且与所述第二栅电极绝缘;
所述第二导电类型的第一柱区域,耦合至所述第一基极区域,并且从所述第一基极区域朝向所述第二表面延伸;以及
所述第二导电类型的第二柱区域,耦合至所述第二基极区域,并且从所述第二基极区域朝向所述第二表面延伸。
9.根据权利要求2所述的半导体器件,还包括:
所述第二导电类型的第一基极区域,与所述第一源极区域组成PN结,并且面对所述第一栅电极且与所述第一栅电极绝缘;
所述第二导电类型的第二基极区域,与所述第二源极区域组成PN结,并且面对所述第二栅电极且与所述第二栅电极绝缘;
所述第一导电类型的外延区域,与所述第一基极区域和所述第二基极区域中的每一个组成PN结;以及
所述第二导电类型的柱区域,定位在用于所述第一晶体管元件的区域与用于所述第二晶体管元件的区域之间的所述外延区域中,并且具有浮置电位。
10.一种半导体器件的制造方法,所述半导体器件具有双向开关,所述方法包括以下步骤:
形成半导体衬底,所述半导体衬底具有彼此相对的第一表面和第二表面,并且具有从所述第一表面朝向所述第二表面延伸的第一栅极沟槽;
形成第一晶体管元件,所述第一晶体管元件包括位于所述第二表面中的第一导电类型的第一漏极区域、位于所述第一表面中的所述第一导电类型的第一源极区域、以及位于所述第一栅极沟槽内的第一栅电极,并且被包括在所述双向开关中;以及
形成第二导电类型的第一杂质区域,所述第一杂质区域在用于所述第一晶体管元件的区域外邻接在所述第一栅极沟槽的侧壁上,并且电耦合至所述第一源极区域。
11.根据权利要求10所述的半导体器件的制造方法,还包括以下步骤:
在所述半导体衬底中,制造从所述第一表面朝向所述第二表面延伸的第二栅极沟槽;
形成第二晶体管元件,所述第二晶体管元件包括位于所述第二表面中的所述第一导电类型的第二漏极区域、位于所述第一表面中的所述第一导电类型的第二源极区域、以及位于所述第二栅极沟槽内的第二栅电极,并且被包括在所述双向开关中;以及
形成所述第二导电类型的第二杂质区域,所述第二杂质区域在用于所述第二晶体管元件的区域外邻接在所述第二栅极沟槽的侧壁上,并且电耦合至所述第二源极区域。
12.根据权利要求11所述的半导体器件的制造方法,其中所述第一杂质区域和所述第二杂质区域彼此分离。
13.根据权利要求10所述的半导体器件的制造方法,还包括以下步骤:
形成所述第二导电类型的第一基极区域,所述第一基极区域与所述第一源极区域组成PN结,并且面对所述第一栅电极且与所述第一栅电极绝缘;
其中在与所述第一基极区域相同的步骤中形成所述第一杂质区域。
14.根据权利要求10所述的半导体器件的制造方法,还包括以下步骤:
形成所述第二导电类型的第一基极区域,所述第一基极区域与所述第一源极区域组成PN结,并且面对所述第一栅电极且与所述第一栅电极绝缘,
其中在与形成所述第一基极区域的步骤不同的步骤中形成所述第一杂质区域。
15.根据权利要求11所述的半导体器件的制造方法,还包括以下步骤:
形成所述第二导电类型的第一基极区域,所述第一基极区域与所述第一源极区域组成PN结,并且面对所述第一栅电极且与所述第一栅电极绝缘;
形成所述第二导电类型的第二基极区域,所述第二基极区域与所述第二源极区域组成PN结,并且面对所述第二栅电极且与所述第二栅电极绝缘;以及
形成第一柱区域和第二柱区域中的至少一个,所述第一柱区域为所述第二导电类型且从所述第一基极区域朝向所述第二表面延伸,所述第二柱区域为所述第二导电类型且从所述第二基极区域朝向所述第二表面延伸。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017-188349 | 2017-09-28 | ||
JP2017188349A JP2019067796A (ja) | 2017-09-28 | 2017-09-28 | 半導体装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN109585557A true CN109585557A (zh) | 2019-04-05 |
CN109585557B CN109585557B (zh) | 2024-07-12 |
Family
ID=65809042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201811062244.7A Active CN109585557B (zh) | 2017-09-28 | 2018-09-12 | 半导体器件及其制造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10763336B2 (zh) |
JP (1) | JP2019067796A (zh) |
CN (1) | CN109585557B (zh) |
TW (1) | TW201921686A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113690956A (zh) * | 2021-07-09 | 2021-11-23 | 东莞新能安科技有限公司 | 一种开关电路、电池管理***及电池包 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI802012B (zh) * | 2021-09-17 | 2023-05-11 | 日商新唐科技日本股份有限公司 | 半導體裝置 |
JP2024022285A (ja) * | 2022-08-05 | 2024-02-16 | 株式会社デンソー | 絶縁ゲート型バイポーラトランジスタ |
CN116741811B (zh) * | 2023-08-11 | 2023-10-20 | 成都森未科技有限公司 | 一种超结mosfet器件及其加工方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060033128A1 (en) * | 2004-08-11 | 2006-02-16 | Min-Hwa Chi | Logic switch and circuits utilizing the switch |
KR20060055338A (ko) * | 2004-11-17 | 2006-05-23 | 산요덴키가부시키가이샤 | 반도체 장치 |
US20140027781A1 (en) * | 2012-07-26 | 2014-01-30 | Cree, Inc. | Monolithic bidirectional silicon carbide switching devices and methods of forming the same |
WO2016064923A1 (en) * | 2014-10-20 | 2016-04-28 | Ideal Power Inc. | Bidirectional power switching with bipolar conduction and with two control terminals gated by two merged transistors |
CN106449747A (zh) * | 2016-11-28 | 2017-02-22 | 电子科技大学 | 一种逆阻型氮化镓高电子迁移率晶体管 |
WO2017049006A1 (en) * | 2015-09-15 | 2017-03-23 | Ideal Power Inc. | Operation of double-base bipolar transistors with additional timing phases at switching transitions |
US20170110448A1 (en) * | 2015-10-15 | 2017-04-20 | Infineon Technologies Austria Ag | Bidirectional Normally-Off Devices and Circuits |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4961658B2 (ja) | 2003-02-17 | 2012-06-27 | 富士電機株式会社 | 双方向素子および半導体装置 |
CN101567373B (zh) | 2004-02-16 | 2011-04-13 | 富士电机***株式会社 | 双方向元件及其制造方法 |
JP2007201338A (ja) | 2006-01-30 | 2007-08-09 | Sanyo Electric Co Ltd | 半導体装置 |
DE102017108048A1 (de) * | 2017-04-13 | 2018-10-18 | Infineon Technologies Austria Ag | Halbleitervorrichtung mit einer grabenstruktur |
-
2017
- 2017-09-28 JP JP2017188349A patent/JP2019067796A/ja active Pending
-
2018
- 2018-09-04 US US16/121,346 patent/US10763336B2/en active Active
- 2018-09-06 TW TW107131250A patent/TW201921686A/zh unknown
- 2018-09-12 CN CN201811062244.7A patent/CN109585557B/zh active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060033128A1 (en) * | 2004-08-11 | 2006-02-16 | Min-Hwa Chi | Logic switch and circuits utilizing the switch |
KR20060055338A (ko) * | 2004-11-17 | 2006-05-23 | 산요덴키가부시키가이샤 | 반도체 장치 |
CN1776911A (zh) * | 2004-11-17 | 2006-05-24 | 三洋电机株式会社 | 半导体装置 |
US20140027781A1 (en) * | 2012-07-26 | 2014-01-30 | Cree, Inc. | Monolithic bidirectional silicon carbide switching devices and methods of forming the same |
WO2016064923A1 (en) * | 2014-10-20 | 2016-04-28 | Ideal Power Inc. | Bidirectional power switching with bipolar conduction and with two control terminals gated by two merged transistors |
WO2017049006A1 (en) * | 2015-09-15 | 2017-03-23 | Ideal Power Inc. | Operation of double-base bipolar transistors with additional timing phases at switching transitions |
US20170110448A1 (en) * | 2015-10-15 | 2017-04-20 | Infineon Technologies Austria Ag | Bidirectional Normally-Off Devices and Circuits |
CN106449747A (zh) * | 2016-11-28 | 2017-02-22 | 电子科技大学 | 一种逆阻型氮化镓高电子迁移率晶体管 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113690956A (zh) * | 2021-07-09 | 2021-11-23 | 东莞新能安科技有限公司 | 一种开关电路、电池管理***及电池包 |
Also Published As
Publication number | Publication date |
---|---|
JP2019067796A (ja) | 2019-04-25 |
US10763336B2 (en) | 2020-09-01 |
CN109585557B (zh) | 2024-07-12 |
TW201921686A (zh) | 2019-06-01 |
US20190097008A1 (en) | 2019-03-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6713453B2 (ja) | カスケードされたリサーフ注入及び二重バッファを備えるldmosデバイスのための方法及び装置 | |
TWI412133B (zh) | 短通道橫向金屬氧化物半導體場效應電晶體及其製造方法 | |
KR101332587B1 (ko) | Mos 트랜지스터 형성 방법 및 그 구조 | |
CN109585557A (zh) | 半导体器件及其制造方法 | |
TWI695454B (zh) | 具有背對背場效應電晶體的雙向開關元件及其製造方法 | |
US6876035B2 (en) | High voltage N-LDMOS transistors having shallow trench isolation region | |
US10468402B1 (en) | Trench diode and method of forming the same | |
US20080093641A1 (en) | Method of manufacturing a multi-path lateral high-voltage field effect transistor | |
JP2005510881A (ja) | オン抵抗が向上されたトレンチ金属酸化膜半導体電界効果トランジスタデバイス | |
JP2005510881A5 (zh) | ||
KR20140019913A (ko) | 반도체 소자 및 그 소자의 제조 방법 | |
CN102194873A (zh) | 具有多种厚度的栅极电介质的半导体元件 | |
TWI714237B (zh) | 高壓ldmos器件與共享隔離區的集成 | |
CN103548132B (zh) | 半导体器件的制造方法 | |
KR20080106341A (ko) | 드레인 확장 반도체 장치 및 대칭 드레인 확장 반도체 장치를 제조하는 방법 | |
TW201218284A (en) | Self-aligned body fully isolated device | |
TWI648821B (zh) | 高電壓雙擴散金氧半導體(dmos)裝置及其製造方法 | |
CN106169503A (zh) | 具有垂直浮动环的半导体装置及其制造方法 | |
CN109817714A (zh) | 横向双扩散金属氧化物半导体(ldmos)器件 | |
US9214550B2 (en) | Quasi-vertical structure having a sidewall implantation for high voltage MOS device | |
KR20110078621A (ko) | 반도체 소자 및 그 제조 방법 | |
CN107681002B (zh) | 具有包括两个层的场电极的晶体管装置 | |
KR20090107024A (ko) | Pn접합 및 모스 커패시터 하이브리드 리설프 트랜지스터 | |
CN110323138B (zh) | 一种ldmos器件的制造方法 | |
US9059306B2 (en) | Semiconductor device having DMOS integration |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant |