CN109509747B - 具有标准单元的集成电路 - Google Patents
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Abstract
本发明公开一种具有标准单元的集成电路。此集成电路包含:第一金属线以及一第二金属线沿着一第一方向延伸;第一虚置栅极以及第二虚置栅极,沿着一第二方向延伸;鳍状结构平行于该第一方向;栅极结构位于鳍状结构上且平行于第二方向;两个长接触插栓位于栅极结构的一侧,两个短接触插栓位于栅极结构的另一侧;栅极插栓设置在栅极结构上;通孔插栓设置在长接触插栓、短接触插栓及栅极接触插栓上并与之电连接;金属层包含第一金属线、第二金属线、一第三金属线以及一第四金属线。
Description
技术领域
本发明涉及一种具有标准单元的集成电路,特别来说,是涉及一种具有反相器的标准单元与具有反极栅的标准单元的集成电路。
背景技术
标准单元是一组或多组的晶体管相互结构,用来提供布林逻辑功能(例如AND、OR、XOR、XNOR)或存储功能(触发器或锁存器)。随着先进制作工艺技术(例如鳍状晶体管FinFet技术),标准单元布局的设计也有所不同。
标准单元库是支持数字集成电路设计自动化流程的基础资料之一,标准单元库从前端功能模拟到后端版图实现架构出整个集成电路自动化设计流程。标准单元库包括若干个预先设计好的标准单元,包括了器件的版图图形以及面积、电路功耗、时序和驱动能力等电路性能值,标准单元具有通用的界面实现和规则结构,集成电路设计者或者综合工具根据设计要求,调用标准单元库中需要的标准单元来完成集成电路的版图布图设计。基于标准单元库的集成电路设计可以极大提高电路的设计效率。
发明内容
本发明于是提出了一种具有标准单元的集成电路,以提供设计集成电路设计时使用。
根据本发明的一实施例,是提供了一种具有反向器(Inverter)标准单元的集成电路。此集成电路包含一第一金属线、一第二金属线、一组第一虚置栅极以及一组第二虚置栅极、多个鳍状结构、一栅极结构、多个短接触插栓与长接触插栓、一栅极结构、多个通孔插栓以及一金属层。第一金属线、第二金属线、第一虚置栅极以及第二虚置栅极包围的区域定义为一标准单元区,该标准单元区具有一N型区以及一P型区。第一金属线以及一第二金属线沿着一第一方向延伸。第一虚置栅极以及第二虚置栅极,沿着一第二方向延伸。鳍状结构设置在标准单元区中,且平行于该第一方向。栅极结构设置在标准单元中,位于鳍状结构上且平行于第二方向。两个短接触插栓以及两个长接触插栓设置在标准单元区中,两个长接触插栓位于栅极结构的一侧,两个短接触插栓位于栅极结构的另一侧。栅极接触插栓设置在栅极结构上。通孔插栓设置在长接触插栓、短接触插栓及栅极接触插栓上并与之电连接。金属层设置在通孔插栓上并与之电连接,金属层包含第一金属线、第二金属线、一第三金属线以及一第四金属线。
根据本发明的另一实施例,是提供了一种具有反极栅(NAND)标准单元的集成电路。此集成电路包含一第一金属线、一第二金属线、一组第一虚置栅极以及一组第二虚置栅极、多个鳍状结构、多个短接触插栓与长接触插栓、两栅极结构、多个通孔插栓以及一金属层。第一金属线以及第二金属线沿着一第一方向平行。第一虚置栅极以及第二虚置栅极沿着第二方向延伸。鳍状结构设置在标准单元区中,鳍状结构平行于第一方向。栅极结构设置在标准单元中,位于鳍状结构上且平行于第二方向。三个短接触插栓以及三个长接触差栓设置在标准单元区中,其中两个长接触插栓位于一个栅极结构与第一虚置栅极结构之间,两个短接触插栓位于两个栅极结构之间,一个长接触插栓与一个短接触插栓位于另一个栅极结构与第二虚置栅极之间。栅极接触插栓分别设置在两个栅极结构上。通孔插栓设置在长接触插栓、短接触插栓以及栅极接触插栓上并与之电连接。金属层设置在通孔插栓上,金属层包含第一金属线、第二金属线、一第三金属线、一第四金属线以及一第五金属线。
本发明提供了一种具有标准单元的集成电路布局,在一个实施例中,标准单元为反向器,在另一实施例中,标准单元为反极栅。通过上述标准单元的配置,可以轻易地组合形成各种可逻辑运算的电子电路,用于加快元件运算速度。
附图说明
图1至图3为本发明一种反相器标准单元的集成电路的布局示意图;
图4至图6为本发明一种反极栅标准单元的集成电路的布局示意图。
主要元件符号说明
300 基底 316A 长通孔插栓
302 鳍状结构 316B 短通孔插栓
304,304A,304B 第一虚置栅极 316D 栅极通孔插栓
305,305A,305B 第二虚置栅极 318 第一金属线
306 栅极结构 320 第二金属线
306A 第一栅极 322 第三金属线
306B 第二栅极 324 第四金属线
314 接触插栓 326 第五金属线
314A 长接触插栓 400 第一方向
314B 短接触插栓 402 第二方向
314C 虚置接触插栓 404 标准单元区
314D 栅极接触插栓 408 P型区
316 通孔插栓 410 N型区
具体实施方式
为使本发明的一般技术人员可以进一步了解本发明,在以下的描述中会列出本发明的优选实施例,并配合附图,详细说明本发明的构成内容及希望实现的效果。
请参考图1至图3,所绘示为本发明一种反相器(inverter)标准单元的集成电路的布局示意图,其包含有鳍状结构、虚置栅极、栅极结构、接触插栓、栅极插栓、通孔插栓与金属线等元件。为了能清楚绘示各元件之间的上下相对位置,本实施例反向器的元件共拆为三部分,由上而下分别地呈现在图1、图2与图3中。请先看图1,本发明的反相器是设置在一基底300上。基底300较佳具有含硅材质,例如是硅、单晶硅(single crystal silicon)、单晶硅锗(single crystal silicon germanium)、非晶硅(amorphous silicon)或是上述的组合。在另一实施例中,基底300也可以包含其他半导体材质,例如是锗或III/V族的复合半导体材料,如锗砷等。在另一实施例中,基底300也可以包含其他介电材料,例如是硅覆绝缘基底(silicon on insulator,SOI)。基底300上具有一标准单元区404,在本实施例中其形状为矩型,短边与一第一方向400平行,长边与一第二方向402平行。标准单元区404中具有一P型区408以及一N型区410,分别位于标准单元区404的上下两侧,于一实施例中,P型区408与N型区410在第一方向上的投影略大于标准单元区404在第一方向400上的投影。而于另一实施例中,P型区408与N型区410在第一方向400上的投影也可以等于标准单元区404在第一方向400上的投影。
如图1所示,本实施例反相器的标准单元还具有多个鳍状结构302,设置在基底300上,其沿着第一方向400延伸,且位于P型区408与N型区410中。在一实施例中,共有N根鳍状结构302位于P型区408中,共有M根鳍状结构位于N型区410中,M与N较佳为奇数(oddnumber),且N大于或等于M。在本实施例中,M与N都为3。而于本发明优选实施例中,鳍状结构302会设置在P型区408与N型区410沿着第一方向400平行的边上。位于P型区408中的鳍状结构302中具有P型掺质如硼(B)、铝(Al)、镓(Ga)等,位于N型区410中的鳍状结构302中具有N型掺质如磷(P)、砷(As)、锑(Sb)等,但并不以此为限。鳍状结构302上设置有一组第一虚置栅极304、一组第二虚置栅极305以及一栅极结构306,三者都沿着第二方向402延伸,其中第一虚置栅极304、第二虚置栅极305对应设置在标准单元区404的长边上,栅极结构306设置在第一虚置栅极304、第二虚置栅极305中间。在一实施例中,第一虚置栅极304包含两个彼此不接触的第一虚置栅极304A、304B,其中一个第一虚置栅极304A跨过P型区408,另一第一虚置栅极304B跨过N型区410;第二虚置栅极305包含两个彼此不接触的第二虚置栅极305A、305B,其中一个第二虚置栅极305A跨过P型区408,另一第二虚置栅极305B跨过N型区410。位于中央的栅极结构306则同时跨过P型区408与N型区410,并跨过M+N个鳍状结构302。因此,在P型区408中形成多个P型晶体管,在N型区410则形成多个N型晶体管。于一实施例中,第一虚置栅极304、第二虚置栅极305与栅极结构306可以通过同一道制作工艺形成,例如是传统多晶硅制作工艺,或是较先进的金属栅极制作工艺,而其剖面可包含栅极介电层(图未示)与金属层(图未示)。
请参考图2,在鳍状结构302、第一虚置栅极304、第二虚置栅极305与栅极结构306上设置有多个接触插栓(contact plug)314,以对外形成电连接通路。这些接触插栓314包含:两个长接触插栓314A、两个短接触插栓314B、两个虚置接触插栓314C与一个栅极接触插栓314D。数字电路设计的内部区域电路设计是由不同的标准单元区404所组成。位于标准单元区404外的虚置接触插栓314C不会出现在数字电路区内部,虚置接触插栓314C仅会出现于数字电路区的最***区域。请同时参考图1与图2,在标准单元区404内,两个长接触插栓314A位于第一虚置栅极304与栅极结构306之间,且两者位于第一方向400上的投影完全相同(也就是位于同一行上),而若从第二方向402来看,其中一个长接触插栓314A跨越P型区408并进一步向上延伸至标准单元区404外,因此会跨越并且直接接触位于P型区408内的鳍状结构302上;另一长接触插栓314A跨越N型区410且进一步向下延伸至标准单元区406以外,因此会直接接触位于N型区410的鳍状结构302上。在标准单元区404内,两个短接触插栓314B位于第二虚置栅极305与栅极结构306之间,此两个短接触插栓314B位于第一方向400上的投影完全相同。若从第二方向402来看,短接触插栓314B一个跨越P型区408并直接接触下方的鳍状结构302,另一个跨越N型区410并直接接触下方的鳍状结构302。在本发明优选实施例中,在标准单元区404内,长接触插栓314A与短接触插栓314B是通过一次或多次的光刻及蚀刻制作工艺(photo-etching-process,PEP)技术并搭配两个或两个以上的掩模层来形成,例如先在第一掩模(图未示)上形成如长接触插栓大小的沟槽后,再将图案化的第二掩模(图未示)形成在部分的沟槽之中,因此未被第二掩模隔开的沟槽便对应形成了长接触插栓314A与短接触插栓314B此外,栅极接触插栓314D位于标准单元区404大略中央处,与下方的栅极结构306直接接触并电连接。在一实施例中,栅极接触插栓314D的孔洞(hole)与长接触插栓314A、短接触插栓314B、虚置接触插栓314C的孔洞(hole)是分别以不同的制作工艺形成,但是可以以同一个金属层填入,并经平坦化制作工艺一并形成,因此,栅极接触插栓314D与长接触插栓314A、短接触插栓314B、虚置接触插栓314C具有齐高的顶面(图未示)。接着,在长接触插栓314A、短接触插栓314B与栅极接触插栓314D上对应设置多个通孔插栓(via plug)316,分别是:长通孔插栓316A对应连接于长接触插栓314A、短通孔插栓316B对应连接于短接触插栓314B、栅极通孔插栓316D对应于栅极接触插栓314D。
如图3所示,在标准单元区404内,多个通孔插栓316向上还各自进一步连接至一第一金属线318、一第二金属线320、一第三金属线322以及一第四金属线324,其中第一金属线318与第二金属线320平行延伸于第二方向402,且第一金属线318的中央线恰位于标准单元区404的一个短边上,第二金属线320的中央线恰位于标准单元区404的另一个短边上,而第三金属线322与第四金属线324位于第一金属线318与第二金属线320中间的区域,并且同时跨越P型区408与N型区410。第一金属线318与其中一个长通孔插栓316A电连接,第二金属线320与另外一个长通孔插栓316A电连接,第三金属线322与栅极通孔插栓316D电连接、第四金属线324则同时与两个短通孔插栓316B电连接。当第一金属线318连接一电压VDD,第二金属线320连接一公共连接端VSS,第三金属线322连接一电压VA,第四金属线324连接一电压VZ,则可在标准单元区404中适当的串接起P型区408中的P型晶体管以及N型区410中的N型晶体管,而形成一反向器的电路。因此,位于标准单元区404内(由第一金属线318、第二金属线320、第一虚置栅极304、第二虚置栅极305所定义)的元件,形成一反向器电路模组而与可与其他标准单元搭配形成各种电子电路;位于标准单元区404以外的元件则可视电路或与其他标准单元的搭配设计而进行调整。
请参考图4至图6,所绘示为本发明一种反极栅(NAND)标准单元的集成电路的布局示意图,其是由鳍状结构、虚置栅极、栅极结构、接触插栓、栅极插栓、通孔插栓与金属线等元件所构成。本实施例的反极栅也上下拆分为三个叠层分别对应图4、图5与图6。请首先参考图4,基底300上具有一标准单元区404,且标准单元区404中有一P型区408以及一N型区410,多个鳍状结构302设置在基底300上,其沿着第一方向400延伸,且位于P型区408与N型区410中。一组第一虚置栅极304、一组第二虚置栅极305、第一栅极结构306A与第二栅极结构306B沿着第二方向402延伸,第一虚置栅极304与第二虚置栅极305设置在标准单元区404的两侧,第一栅极结构306A与第二栅极结构306B设置在第一虚置栅极304与第二虚置栅极305的中间,第一栅极结构306A位于靠近第一虚置栅极304的一侧,第二栅极结构306B位于靠近第二虚置栅极305的一侧。本实施例的基底300、标准单元区404、P型区408、N型区410、鳍状结构302、第一虚置栅极304、第二虚置栅极305、第一栅极结构306A与第二栅极结构306B的实施方式,除了前文的叙述以外,其实施方式与前一实施例大致相同,在此不再加以赘述。
请参考图5,在第一栅极结构306A与第二栅极结构306B上设置有多个接触插栓314以及多个通孔插栓316。在一实施例中,接触插栓314包含三个长接触插栓314A、三个短接触插栓314B、三个虚置接触插栓314C与两个栅极接触插栓314D。数字电路设计的内部区域电路设计是由不同的标准单元区404所组成。位于标准单元区404外的虚置接触插栓314C不会出现在数字电路区内部,虚置接触插栓314C仅会出现于数字电路区的最***区域。在标准单元区404内,其中两个长接触插栓314A位于第一虚置栅极304与第一栅极结构306A之间,且彼此位于第一方向400上的投影完全相同;两个短接触插栓314B位于第一栅极结构306A与第二栅极结构306B之间,且彼此位于第一方向400上的投影完全相同;一个长接触插栓314A与一个短接触插栓314B位于第二虚置栅极305与第二栅极结构306B之间,且彼此位于第一方向400上的投影完全相同;两个栅极接触插栓314D位于标准单元区404中央并分别电连接第一栅极结构306A与第二栅极结构306B。通孔插栓316包含三个长通孔插栓316A、两个短通孔插栓316B以及两个栅极通孔插栓316D,分别对应设置在长接触插栓314A、短接触插栓314B与栅极接触插栓314D上。值得注意的是,仅有位于P型区408的短接触插栓314B设置有短通孔插栓316B,而位于N型区410的短接触插栓314B则没有设置有短通孔插栓。接触插栓314与通孔插栓316的实施方式,除了前文的叙述以外,其实施方式与前一实施例大致相同,在此不再加以赘述。
如图6所示,通孔插栓316上具有一第一金属线318、一第二金属线320、一第三金属线322、一第四金属线324以及一第五金属线326,第一金属线318与其中两个长通孔插栓316A电连接,第二金属线322与另外一个长通孔插栓316A电连接,第三金属线322与其中一个栅极通孔插栓316D电连接、第四金属线324与另外一个栅极通孔插栓316D电连接、第五金属线324则同时与两个短通孔插栓316B电连接。当第一金属线318连接一电压VDD,第二金属线320连接一公共连接端VSS,第三金属线322连接一电压VA,第四金属线324连接一电压VB,第四金属线324连接一电压VZ,则可在标准单元区404中适当的串接起P型区408中的P型晶体管以及N型区410中的N型晶体管,而形成一反极栅的电路。
综上所述,本发明是提供了一种具有标准单元的集成电路布局,在一个实施例中,标准单元为反向器,在另一实施例中,标准单元为反极栅。通过上述标准单元的配置,可以轻易地组合形成各种可逻辑运算的电子电路,用于加快元件运算速度。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (20)
1.一种具有标准单元(standard cell)的集成电路,包含:
第一金属线以及第二金属线,两者沿着一第一方向延伸;
一组第一虚置栅极以及一组第二虚置栅极,沿着一第二方向延伸,其中该第一金属线、该第二金属线、该组第一虚置栅极以及该组第二虚置栅极包围的区域定义为一标准单元区,该标准单元区具有N型区以及P型区;
多个鳍状结构,设置在该标准单元区中,该多个鳍状结构平行于该第一方向;
栅极结构,设置在该标准单元区中,位于该鳍状结构上且平行于该第二方向;
两个短接触插栓以及两个长接触插栓,设置在该标准单元区中,该两个长接触插栓位于该栅极结构的一侧,该两个短接触插栓位于该栅极结构的另一侧;
栅极接触插栓,设置在该栅极结构上;
多个通孔插栓,设置在该两个长接触插栓、该两个短接触插栓及该栅极接触插栓上并与之电连接,其中所述多个通孔插栓中的一个电连接至在该N型区或该P型区外的该长接触插栓,且所述多个通孔插栓中的另一个电连接至在该N型区或该P型区内的该短接触插栓,且电连接至该长接触插栓和该短接触插栓的所述两个通孔插栓的位置不互相对称;以及
金属层,设置在该多个通孔插栓上并与之电连接,该金属层包含该第一金属线、该第二金属线、一第三金属线以及一第四金属线。
2.如权利要求1所述的集成电路,其中该组第一虚置栅极包含两个彼此不接触的该第一虚置栅极,该组第二虚置栅极包含两个彼此不接触的该第二虚置栅极。
3.如权利要求1所述的集成电路,其中该P型区具有N个该鳍状结构,该N型区具有M个该鳍状结构,N与M都为奇数,且N大于或等于M。
4.如权利要求1所述的集成电路,其中该两个长接触插栓位于该第一方向上的投影完全重叠,该两个短接触插栓位于该第一方向上的投影完全重叠。
5.如权利要求1所述的集成电路,其中一个该长接触插栓以及一个该短接触插栓穿越过该P型区,另一个该长接触插栓与另一个该短接触插栓穿越该N型区。
6.如权利要求1所述的集成电路,其中该两个长接触插栓还进一步延伸至该标准单元区外。
7.如权利要求1所述的集成电路,其中该多个通孔插栓包含两个短通孔插栓、两个长通孔插栓以及一栅极通孔插栓。
8.如权利要求7所述的集成电路,其中该第一金属线连接其中一个该长通孔插栓,该第二金属线连接另外一个该长通孔插栓。
9.如权利要求8所述的集成电路,其中该第三金属线连接该栅极通孔插栓。
10.如权利要求8所述的集成电路,其中该第四金属线连接该两个短通孔插栓。
11.一种具有标准单元的集成电路,包含:
第一金属线以及第二金属线,两者沿着一第一方向平行;
一组第一虚置栅极以及一组第二虚置栅极,沿着一第二方向延伸,其中该第一金属线、该第二金属线、该组第一虚置栅极以及该组第二虚置栅极包围的区域定义为一标准单元区,该标准单元区包含N型区以及P型区;
多个鳍状结构,设置在该标准单元区中,该多个鳍状结构平行于该第一方向;
两个栅极结构,设置在该标准单元区中,位于该多个鳍状结构上且平行于该第二方向;
三个短接触插栓以及三个长接触插栓,设置在该标准单元区中,其中两个该长接触插栓位于一个该栅极结构与该组第一虚置栅极结构之间,两个该短接触插栓位于两个该栅极结构之间,一个该长接触插栓与一个该短接触插栓位于另一个该栅极结构与该组第二虚置栅极之间;
两个栅极接触插栓,分别设置在该两个栅极结构上;
多个通孔插栓,设置在该三个长接触插栓、该三个短接触插栓以及该两个栅极接触插栓上并与之电连接;以及
金属层,设置在该多个通孔插栓上,该金属层包含该第一金属线、该第二金属线、一第三金属线、一第四金属线以及一第五金属线。
12.如权利要求11所述的集成电路,其中该组第一虚置栅极包含两个彼此不接触的该第一虚置栅极,该组第二虚置栅极包含两个彼此不接触的该第二虚置栅极。
13.如权利要求12所述的集成电路,其中该P型区具有N个鳍状结构,该N型区具有M个鳍状结构,N与M都为奇数,且N大于或等于M。
14.如权利要求11所述的集成电路,其中位于一个该栅极结构与该组第一虚置栅极结构之间的两个该长接触插栓,位于第一方向上的投影完全重叠。
15.如权利要求11所述的集成电路,其中位于两个该栅极结构之间的两个该短接触插栓,位于第一方向上的投影完全重叠。
16.如权利要求11所述的集成电路,其中位于另一个该栅极结构与该组第二虚置栅极结构之间的一个该长接触插栓与一个该短接触插栓,位于该第一方向上的投影完全重叠。
17.如权利要求11所述的集成电路,其中该两个长接触插栓还进一步延伸至该标准单元区外。
18.如权利要求11所述的集成电路,其中该多个通孔插栓包含两个短通孔插栓、三个长通孔插栓以及两个栅极通孔插栓。
19.如权利要求18所述的集成电路,其中该第一金属线连接其中两个该长通孔插栓,该第二金属线连接另外一个该长通孔插栓。
20.如权利要求18所述的集成电路,其中该第三金属线连接一个该栅极通孔插栓,该第四金属线连接另外一个该栅极通孔插栓,该第五金属线连接两个该短通孔插栓。
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