CN109495104A - Phaselocked loop internal delay time circuit and phaselocked loop - Google Patents
Phaselocked loop internal delay time circuit and phaselocked loop Download PDFInfo
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- CN109495104A CN109495104A CN201811353745.0A CN201811353745A CN109495104A CN 109495104 A CN109495104 A CN 109495104A CN 201811353745 A CN201811353745 A CN 201811353745A CN 109495104 A CN109495104 A CN 109495104A
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- phaselocked loop
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- 230000010355 oscillation Effects 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 3
- 230000006641 stabilisation Effects 0.000 abstract description 3
- 238000011105 stabilization Methods 0.000 abstract description 3
- 230000003111 delayed effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a kind of phaselocked loop internal delay time circuits, including the time delay chain being made of delay unit, the grid of PMOS5 adds bias voltage in delay unit, drain electrode is connect with the source electrode of NMOS1 and NMOS2, the drain electrode and the drain electrode of PMOS1 of NMOS1, the drain and gate of PMOS2 is connected to output end, the drain electrode of NMOS2 and the drain electrode of the drain and gate and PMOS4 of PMOS3 are connected to output end, PMOS1, the grid of PMOS4 adds bias voltage respectively, PMOS1, PMOS2, PMOS3, the source electrode of PMOS4 is connected, the grid of NMOS1 and NMOS2 is connect with the output end of other delay units.The phaselocked loop being made of delay circuit is also disclosed.By adjusting bias voltage, it can reduce chip area by frequency stabilization at a required output frequency, reduce cost.
Description
Technical field
The present invention relates to technical field of integrated circuits, are a kind of phaselocked loop internal delay time circuit and phaselocked loop specifically.
Background technique
The spy that phaselocked loop (Phase-Locked Loop, PLL) generates the simulation clock signal of input by frequency multiplication mode
Fixed dagital clock signal, clock signal are widely applied among various circuits.And voltage controlled oscillator is in phaselocked loop
Important component, general described voltage controlled oscillator refers to that output frequency and input control voltage have the oscillation electricity of corresponding relationship
Road.Voltage controlled oscillator is divided into according to structure: LC voltage controlled oscillator, RC voltage controlled oscillator, phase noise.To voltage controlled oscillation
The technology major requirement of device has: frequency stability is good, control high sensitivity, and tuning range is wide etc..And in integrated circuit design,
In contrast, RC voltage controlled oscillator precision is inadequate, and LC voltage controlled oscillator space is excessive, and phase noise, and size is small suitable
For in integrated circuit, and there is high stable output characteristics.And the core component delay circuit in phase noise, then it is
The core of design, the design and parameter setting of circuit also just determine the quality of phase noise.
Summary of the invention
The purpose of the present invention is to provide a kind of phaselocked loop internal delay time circuit and phaselocked loop, it is capable of providing stable controllable
Output frequency, and it is capable of providing specific output frequency.
The present invention is solved the above problems by following technical proposals:
A kind of phaselocked loop internal delay time circuit, the delay circuit include the time delay chain being made of multiple delay units, institute
It states delay unit to be made of PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, NMOS1 and NMOS2, the grid of the PMOS5 adds
The source electrode of bias voltage VN, PMOS5 are grounded, and the drain electrode of PMOS5 is connect with the source electrode of the NMOS1 and NMOS2, the leakage of NMOS1
Pole connect with the grid of the drain electrode of the PMOS1, the drain electrode of PMOS2 and PMOS2 and as the first output end, the drain electrode of NMOS2
It is connect with the drain electrode of the PMOS3, the drain electrode of the grid of PMOS3 and PMOS4 and as second output terminal, the PMOS1,
The grid of PMOS4 adds bias voltage VP respectively, and the source electrode of described PMOS1, PMOS2, PMOS3, PMOS4 are connected, the NMOS1's
Two output ends of previous delay unit are separately connected on the grid and time delay chain of grid and NMOS2.
PMOS1, PMOS2, PMOS3, PMOS4, PMOS5 and NMOS1 and NMOS2 constitute differential vibrating delay circuit.
PMOS5 provides electric current similar to current source, for circuit, and it is controllable time delay that PMOS1 and PMOS4, which are used to change the bias voltage of circuit,
The important composition of circuit controls the frequency range of delay unit work by changing the bias voltage of PMOS1 and PMOS4,
PMOS2 and PMOS3 and NMOS1 and NMOS2 forms two phase inverters, collectively forms difference channel structure, the machine of difference channel
Structure can effectively inhibit common-mode noise and power supply noise bring to influence.NMOS1 and NMOS2 respectively with another delay unit
Output end is connected, to constitute time delay chain.Due to using full-differential circuits structure, the phase inverter for breaching Single-end output is constituted
Time delay chain can only reach the limitation of oscillation purpose by odd number delay unit, odd number or even number can be used in the design
A delay unit achievees the purpose that oscillation.The delay unit used is fewer, and the output frequency that can be obtained is higher, therefore, excellent
Choosing constitutes feed circuit using the make delay chain of three delay units composition, and design structure is simple, it can obtain 10~
600MHz stablizes output frequency.
A kind of phaselocked loop including phaselocked loop internal delay time circuit, the output end by delay circuit and with the delay circuit
Sequentially connected phase discriminator, charge pump and filter circuit, the delay circuit and phase discriminator input identical reference clock signal,
The filter circuit exports the control voltage signal for being used to control delay circuit frequency of oscillation to delay circuit.
Delay circuit carries out in phase discriminator with original reference clock signal after the reference clock signal of input is delayed
Comparison generates phase signal, then is converted into control voltage signal by charge pump and filter circuit, and then control delay circuit
Frequency of oscillation.By adjusting bias voltage, it can be realized the frequency range of 10~600MHz, guarantee output frequency fast and stable.
It compares for RC oscillator and LC oscillator, the topological structure that the design uses has more high integration, more precisely, prolong
When it is controllable the advantages that, lesser area can be applied by it at more aspects.
Compared with prior art, the present invention have the following advantages that and the utility model has the advantages that
(1) present invention uses fully differential structure, is all made of metal-oxide-semiconductor composition, can reduce chip area, reduce cost, together
When stable controllable time delay output frequency is provided, be suitable for full speed USB, have good performance in audio, speech field.
(2) circuit parameter that the present invention counts can obtain the stable output frequency of 10~600MHz, by adjusting bias voltage,
It can be by frequency stabilization in a specific output frequency.Under various techniques, using the argument structure, output can be obtained
It ensures.
Detailed description of the invention
Fig. 1 is the circuit diagram of delay unit；
Fig. 2 is the electrical block diagram of phaselocked loop；
Fig. 3 is time delay chain schematic diagram of the invention.
Specific embodiment
The present invention is described in further detail below with reference to embodiment, embodiments of the present invention are not limited thereto.
Embodiment 1:
In conjunction with shown in attached drawing 1 and Fig. 3, a kind of phaselocked loop internal delay time circuit, the delay circuit includes by multiple delays
The time delay chain of unit composition, the delay unit is by PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, NMOS1 and NMOS2 structure
At the grid of the PMOS5 adds bias voltage VN, the source electrode ground connection of PMOS5, the drain electrode of PMOS5 and the NMOS1 and NMOS2
Source electrode connection, the drain electrode of NMOS1 connect with the grid of the drain electrode of the PMOS1, the drain electrode of PMOS2 and PMOS2 and as the
The drain electrode of one output end, NMOS2 is connect and with the drain electrode of the PMOS3, the drain electrode of the grid of PMOS3 and PMOS4 as second
Output end, the grid of described PMOS1, PMOS4 add bias voltage VP, the source of described PMOS1, PMOS2, PMOS3, PMOS4 respectively
Extremely it is connected, two output ends of previous delay unit connect respectively on the grid of the NMOS1 and the grid of NMOS2 and time delay chain
It connects.
Using smic110nm technique, NMOS and PMOS parameter is adjusted as shown in Figure 1, PMOS1, PMOS2, PMOS3, PMOS4
Parameter are as follows: p12；W=3u；L=400n；fingers:1；M=1；The parameter of PMOS5 are as follows: p12；W=3u；L=700n；
fingers:1；M=2；The grid of NMOS1 and the parameter of NMOS2 are as follows: n12；W=3u；L=700n；fingers:1；M=2.With
The upper physical size for metal-oxide-semiconductor determines the parameter of metal-oxide-semiconductor with software emulation by designing, this parameter is based on, by adjusting inclined
The voltage range of voltage VP and bias voltage VN are set, arbitrarily stable clock frequency within the scope of 10~600MHz can be obtained.
Add bias voltage VN in the grid of PMOS5, so that it is supplied electric current to entire circuit, in the grid of PMOS1, PMOS4
Add the frequency range of bias voltage VP control delay circuit work, and the grid of the grid of NMOS1 and NMOS2 prolong with another respectively
When circuit output end be connected, to constitute time delay chain.PMOS1, PMOS2, PMOS3, PMOS4, PMOS5 and NMOS1 and
NMOS2 constitutes differential vibrating delay circuit.PMOS5 provides electric current similar to current source, for circuit, and PMOS1 and PMOS4 are used to change
The bias voltage of circuit is the important composition of controllable time delay circuit, is controlled by changing the bias voltage of PMOS1 and PMOS4
The frequency range of delay unit work, PMOS2 and PMOS3 and NMOS1 and NMOS2 form two phase inverters, collectively form difference
Parallel circuit structure, the mechanism of difference channel can effectively inhibit common-mode noise and power supply noise bring to influence.NMOS1 and
NMOS2 is connected with the output end of another delay unit respectively, to constitute time delay chain.Due to using full-differential circuits structure,
The time delay chain for breaching the phase inverter composition of Single-end output can only reach the limitation of oscillation purpose by odd number delay unit,
The full-differential circuits structure that the design uses, can achieve the purpose that oscillation using even number delay circuit, using complete
Difference channel structure can preferably inhibit common-mode noise and power supply noise bring to influence.The delay unit used is fewer, energy
The output frequency accessed is higher, it is therefore preferable that the make delay chain formed using three delay units, constitutes feed circuit,
Design structure is simple, can obtain 10~600MHZ and stablize output frequency, by adjusting bias voltage, frequency stabilization can exist
One specific output frequency guarantees output frequency fast and stable.In practical applications, it can be used for full speed USB mode, usually use
In transmission phone, audio, compression video etc., there is good performance in fields such as speech, audios, there is at low cost, hot plug, it can
It the advantages that control delay, can be effectively reduced using the design by circuit bring influence of noise itself.
Embodiment 2:
On the basis of embodiment 1, as shown in connection with fig. 2, a kind of phaselocked loop including phaselocked loop internal delay time circuit, by prolonging
When the circuit and sequentially connected phase discriminator of output end, charge pump and filter circuit with the delay circuit, the delay circuit
Identical reference clock signal is inputted with phase discriminator, the filter circuit will be used to control the control electricity of delay circuit frequency of oscillation
Pressure signal is exported to delay circuit.
Delay circuit carries out in phase discriminator with original reference clock signal after the reference clock signal of input is delayed
Comparison generates phase signal, then is converted into control voltage signal by charge pump and filter circuit, and then control delay circuit
Frequency of oscillation.By adjusting bias voltage VP, it can be realized the frequency range of 10~600MHz, guarantee that output frequency is quickly steady
It is fixed.It comparing for RC oscillator and LC oscillator, the topological structure that the design uses has a more high integration, more precisely,
It is delayed the advantages that controllable, lesser area can be applied by it at more aspects.
Although reference be made herein to invention has been described for explanatory embodiment of the invention, and above-described embodiment is only this hair
Bright preferable embodiment, embodiment of the present invention are not limited by the above embodiments, it should be appreciated that those skilled in the art
Member can be designed that a lot of other modification and implementations, these modifications and implementations will fall in principle disclosed in the present application
Within scope and spirit.
Claims (3)
1. a kind of phaselocked loop internal delay time circuit, which is characterized in that the delay circuit includes being made of multiple delay units
Time delay chain, the delay unit are made of PMOS1, PMOS2, PMOS3, PMOS4, PMOS5, NMOS1 and NMOS2, the PMOS5
Grid add bias voltage VN, the source electrode ground connection of PMOS5, the drain electrode of PMOS5 is connect with the source electrode of the NMOS1 and NMOS2,
The drain electrode of NMOS1 connect with the grid of the drain electrode of the PMOS1, the drain electrode of PMOS2 and PMOS2 and as the first output end,
The drain electrode of NMOS2 is connect and as second output terminal, institute with the drain electrode of the PMOS3, the drain electrode of the grid of PMOS3 and PMOS4
The grid for stating PMOS1, PMOS4 adds bias voltage VP respectively, and the source electrode of described PMOS1, PMOS2, PMOS3, PMOS4 are connected, institute
Two output ends for stating previous delay unit on the grid of NMOS1 and the grid of NMOS2 and time delay chain are separately connected.
2. a kind of phaselocked loop internal delay time circuit according to claim 1, which is characterized in that the delay circuit include by
The time delay chain of three delay unit compositions.
3. a kind of phaselocked loop including phaselocked loop internal delay time circuit as described in claim 1, which is characterized in that by delay electricity
Road and the sequentially connected phase discriminator of output end, charge pump and filter circuit with the delay circuit, the delay circuit and mirror
Phase device inputs identical reference clock signal, and the filter circuit believes the control voltage for being used to control delay circuit frequency of oscillation
Number output is to delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811353745.0A CN109495104A (en) | 2018-11-14 | 2018-11-14 | Phaselocked loop internal delay time circuit and phaselocked loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811353745.0A CN109495104A (en) | 2018-11-14 | 2018-11-14 | Phaselocked loop internal delay time circuit and phaselocked loop |
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| CN109495104A true CN109495104A (en) | 2019-03-19 |
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| CN201811353745.0A Pending CN109495104A (en) | 2018-11-14 | 2018-11-14 | Phaselocked loop internal delay time circuit and phaselocked loop |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0771075A2 (en) * | 1995-10-24 | 1997-05-02 | Vlsi Technology, Inc. | Phase locked loop having voltage controlled oscillator utilizing combinational logic |
| CN102136840A (en) * | 2011-04-22 | 2011-07-27 | 上海宏力半导体制造有限公司 | Automatic biasing phase-locked loop |
| CN205566264U (en) * | 2016-03-18 | 2016-09-07 | 上海诚天智能卡有限公司 | Novel intelligent card |
| CN108306637A (en) * | 2018-01-24 | 2018-07-20 | 北京时代民芯科技有限公司 | A kind of charge pump phase lock loop controlling voltage controlled oscillator using two-way voltage |
-
2018
- 2018-11-14 CN CN201811353745.0A patent/CN109495104A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0771075A2 (en) * | 1995-10-24 | 1997-05-02 | Vlsi Technology, Inc. | Phase locked loop having voltage controlled oscillator utilizing combinational logic |
| CN102136840A (en) * | 2011-04-22 | 2011-07-27 | 上海宏力半导体制造有限公司 | Automatic biasing phase-locked loop |
| CN205566264U (en) * | 2016-03-18 | 2016-09-07 | 上海诚天智能卡有限公司 | Novel intelligent card |
| CN108306637A (en) * | 2018-01-24 | 2018-07-20 | 北京时代民芯科技有限公司 | A kind of charge pump phase lock loop controlling voltage controlled oscillator using two-way voltage |
Non-Patent Citations (1)
| Title |
|---|
| 宋志杰 等: "基于低抖动锁相环的高精度延时电路设计", 《第十九届计算机工程与工艺年会暨第五届微处理器技术论坛论文集》 * |
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Application publication date: 20190319 |