CN109461697B - Etching method and method for manufacturing semiconductor device - Google Patents
Etching method and method for manufacturing semiconductor device Download PDFInfo
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- CN109461697B CN109461697B CN201811332602.1A CN201811332602A CN109461697B CN 109461697 B CN109461697 B CN 109461697B CN 201811332602 A CN201811332602 A CN 201811332602A CN 109461697 B CN109461697 B CN 109461697B
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- 238000000034 method Methods 0.000 title claims abstract description 81
- 238000005530 etching Methods 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 102
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 238000001039 wet etching Methods 0.000 claims abstract description 51
- 238000001035 drying Methods 0.000 claims abstract description 47
- 230000008569 process Effects 0.000 claims abstract description 31
- 238000002955 isolation Methods 0.000 claims description 35
- 238000001312 dry etching Methods 0.000 claims description 32
- 238000003860 storage Methods 0.000 claims description 25
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 229920005591 polysilicon Polymers 0.000 claims description 15
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 238000003486 chemical etching Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 238000004380 ashing Methods 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 4
- 238000002791 soaking Methods 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
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- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
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- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000005596 ionic collisions Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
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- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001694 spray drying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
The invention provides an etching method and a manufacturing method of a semiconductor device, wherein the etching method comprises the following steps: providing a substrate with a patterned photoresist layer; taking the patterned photoresist layer as a mask, and carrying out wet etching on the substrate; drying the substrate after the wet etching, wherein the drying temperature is 25-35 ℃; taking the patterned photoresist layer as a mask, and carrying out subsequent processes on the dried substrate; and removing the patterned photoresist layer. According to the technical scheme, the substrate after wet etching is dried at a low temperature, so that the dried patterned photoresist layer can be continuously used in a subsequent process, the production period is shortened, and the production cost is reduced.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing, and more particularly, to an etching method and a method for manufacturing a semiconductor device.
Background
In the production process of the semiconductor device, as the size of the semiconductor device is smaller and the requirement of technical specification is higher, a part of structure in the semiconductor device has specific requirements on patterns during etching, but the specific patterns cannot be etched by using wet etching or dry etching alone, and the requirements can be met only by combining the isotropy of the wet etching (see fig. 1a) and the anisotropy of the dry etching (see fig. 1 b). The method comprises the following specific steps:
1. firstly, forming a patterned photoresist layer on a device, and carrying out wet etching on a region to be etched;
2. then, carrying out isopropanol atomization drying (IPA drying) on the device after wet etching, and removing the patterned photoresist layer;
3. and finally, forming a patterned photoresist layer on the device again, carrying out dry etching on the region to be etched, and removing the patterned photoresist layer after the etching is finished.
In the above steps, when IPA drying is performed on the device after wet etching, the drying temperature is 75 to 85 ℃, and the patterned photoresist layer is damaged under the action of high temperature, thereby affecting the subsequent etching process. For example, referring to the etching process of the device shown in fig. 2a to 2d, fig. 2a shows a substrate 10 to be etched, the substrate 10 includes a peripheral region 11 and a storage region 12, the peripheral region 11 and the storage region 12 include a plurality of shallow trench isolation structures 13, a gate oxide layer 14 and a polysilicon gate layer 15 are formed on the top surface of the substrate 10 between the shallow trench isolation structures 13, the top surface of the shallow trench isolation structures 13 is flush with the top surface of the polysilicon gate layer 15, and a patterned photoresist layer 16 covers the top of the peripheral region 11; firstly, performing wet etching on the substrate 10, and as can be seen from fig. 2b, performing wet etching on the shallow trench isolation structure 13 on the storage region 12 by using the patterned photoresist layer 16 as a mask, and removing a part of the thickness of the shallow trench isolation structure 13, so that the top surface of the shallow trench isolation structure 13 on the storage region 12 is lower than the top surface of the polysilicon gate layer 15 and higher than the top surface of the gate oxide layer 14; then, IPA drying is performed on the substrate 10 after the wet etching, as can be seen from fig. 2c, the edge region of the patterned photoresist layer 16 after drying is damaged, so that the top surfaces of the shallow trench isolation structures 13 and the polysilicon gate layer 15 on a portion of the peripheral region 11 are exposed, and if the next dry etching process is performed on the storage region 12 by using the damaged patterned photoresist layer 16, as shown in fig. 2d, a situation may occur in which, except for a portion of the thickness of the shallow trench isolation structures 13 on the normal storage region 12, a portion of the thickness of the shallow trench isolation structures 13 on the peripheral region 11 that is not covered by the patterned photoresist layer 16 is also etched during the dry etching, so that the structure of the device is damaged, and the performance of the device is affected. Therefore, before the storage region 12 is dry etched, the patterned photoresist layer 16 needs to be removed, and then a patterned photoresist layer 16 needs to be formed again to completely cover the peripheral region 11, and after the dry etching is completed, the newly formed patterned photoresist layer 16 needs to be removed, so that 2 times of forming the patterned photoresist layer 16 and 2 times of removing the patterned photoresist layer 16 are needed, the production cost is high, and the production cycle is long. Therefore, how to make the patterned photoresist layer after the wet etching continuously usable in the subsequent process to shorten the production period and reduce the production cost is a problem to be solved.
Disclosure of Invention
The invention aims to provide an etching method and a manufacturing method of a semiconductor device, so that a patterned photoresist layer after wet etching can be continuously used in subsequent processes to shorten the production period and reduce the production cost.
In order to achieve the above object, the present invention provides an etching method, comprising:
s1, providing a substrate with a patterned photoresist layer;
s2, taking the patterned photoresist layer as a mask, and carrying out wet etching on the substrate;
s3, drying the substrate after the wet etching, wherein the drying temperature is 25-35 ℃;
s4, taking the patterned photoresist layer as a mask, and carrying out subsequent processes on the dried substrate; and the number of the first and second groups,
and S5, removing the patterned photoresist layer.
Optionally, the substrate is dried by a method including isopropyl alcohol spray drying.
Optionally, the substrate is directly dried on the wet etching machine, and the drying temperature is set on the wet etching machine.
Optionally, the subsequent process includes dry etching or ion implantation.
Optionally, the steps S2 to S4 are executed in a loop until the etching result of the substrate reaches a preset requirement.
Optionally, the step of removing the patterned photoresist layer includes: firstly, carrying out plasma ashing treatment, and then soaking by adopting a mixed solution of sulfuric acid and hydrogen peroxide.
Optionally, the patterned photoresist layer comprises a positive photoresist or a negative photoresist.
The present invention also provides a method for manufacturing a semiconductor device, comprising: the etching method provided by the invention is adopted to etch a substrate so as to manufacture the semiconductor device.
Optionally, the subsequent process in the etching method includes dry etching or ion implantation.
Optionally, the substrate has a peripheral region and a storage region, the substrates in the peripheral region and the storage region are respectively provided with a plurality of shallow trench isolation structures, a gate oxide layer and a polysilicon gate layer are formed on the top surface of the substrate between adjacent shallow trench isolation structures, and the top surfaces of the shallow trench isolation structures are flush with the top surface of the polysilicon gate layer; and performing back etching on the shallow trench isolation structures in the storage region by sequentially adopting wet etching and dry etching in the etching method, so that the top surface of each shallow trench isolation structure in the storage region is flush with the bottom surface of the gate oxide layer.
Optionally, the etchant used in the wet etching includes hydrofluoric acid or phosphoric acid.
Optionally, the dry etching includes physical etching, chemical etching or physical chemical etching.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the etching method, the substrate after wet etching is dried at low temperature, so that the dried patterned photoresist layer can be continuously used in the subsequent process, and the patterned photoresist layer does not need to be removed and remanufactured, thereby shortening the production period and reducing the production cost.
2. According to the manufacturing method of the semiconductor device, the substrate is etched by adopting the etching method, so that the patterned photoresist layer after wet etching and drying can be continuously used in the process of manufacturing the semiconductor device, the production period is further shortened, and the production cost is reduced.
Drawings
FIGS. 1 a-1 b are schematic directional diagrams of wet and dry etching;
FIGS. 2 a-2 d are schematic diagrams of prior art devices using a patterned photoresist layer for etching;
FIG. 3 is a flow chart of an etching method according to an embodiment of the present invention;
fig. 4a to 4d are device diagrams in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Wherein the reference numerals of figures 1a to 4d are as follows:
10. 20-a substrate; 11. 21-a peripheral region; 12. 22-a storage area; 13. 23-shallow trench isolation structures; 14. 24-a gate oxide layer; 15. 25-a polysilicon gate layer; 16. 26-patterned photoresist layer.
Detailed Description
In order to make the objects, advantages and features of the present invention more clear, the etching method and the manufacturing method of the semiconductor device proposed by the present invention are further described in detail with reference to fig. 3 to 4 d. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides an etching method, and referring to fig. 3, fig. 3 is a flowchart of the etching method according to the embodiment of the present invention, where the etching method includes:
step S1, providing a substrate with a patterned photoresist layer;
step S2, taking the patterned photoresist layer as a mask, and carrying out wet etching on the substrate;
s3, drying the substrate after the wet etching, wherein the drying temperature is 25-35 ℃;
step S4, taking the patterned photoresist layer as a mask, and carrying out subsequent processes on the dried substrate;
and step S5, removing the patterned photoresist layer.
The etching method provided by the embodiment is described in more detail as follows:
first, according to step S1, a substrate having a patterned photoresist layer is provided. The material of the substrate may include silicon, germanium, silicon carbide, and the like. The patterned photoresist layer may be formed by photolithography, and specifically, a layer of photoresist may be formed on the substrate, and the photoresist may be a positive photoresist or a negative photoresist; and then, irradiating the photoresist by ultraviolet rays through a mask, wherein a pre-designed circuit pattern is printed on the mask, if the photoresist is a positive photoresist, the photoresist irradiated by the ultraviolet rays reacts and is dissolved, and after the dissolved photoresist is removed, the pattern of the remained photoresist is consistent with the pattern on the mask, so that the patterned photoresist layer is obtained. If the photoresist is a negative photoresist, the photoresist irradiated by ultraviolet rays is not dissolved, and after the dissolved photoresist is removed, the pattern of the photoresist left is opposite to the pattern on the mask, so that the patterned photoresist layer is obtained.
Then, according to step S2, the substrate is wet etched using the patterned photoresist layer as a mask. Specifically, the substrate may be immersed in an etchant, and the portion of the substrate not covered by the patterned photoresist layer is removed by a chemical reaction with the etchant. The wet etching is isotropic, i.e. the width of the lateral etching is close to the depth of the vertical etching. The time of the wet etching and the concentration of the etchant can be adjusted according to the width and the depth of the substrate to be etched. An appropriate etchant, such as hydrofluoric acid or phosphoric acid, may be selected depending on the material of the substrate.
Then, the substrate after the wet etching is dried at a temperature of 25 to 35 ℃ (for example, 28 ℃, 30 ℃, 33 ℃ and the like) in step S3. The method for drying the substrate comprises isopropyl alcohol atomization drying (IPA drying), the substrate can be directly dried on a wet etching machine, and the drying temperature is set on the wet etching machine. Specifically, one or more drying boxes are arranged on the wet etching machine, the substrate is placed in the drying boxes, and the temperature in the drying boxes is set; then, introducing isopropanol into the drying box, and replacing the moisture with higher surface tension on the surface of the substrate by utilizing the characteristics of low surface tension and easy volatilization of the isopropanol; then, exhausting the drying box, and taking the water vapor and the isopropanol out of the drying box; finally, nitrogen gas was introduced into the dry box to completely dry the surface of the substrate. Because the drying temperature is set to be 25-35 ℃ (for example, 28 ℃, 30 ℃, 33 ℃ and the like), the drying temperature is low, and the patterned photoresist layer is not damaged in the drying process, so that the patterned photoresist layer can be continuously used in the subsequent process, and the patterned photoresist layer does not need to be re-manufactured after being removed, thereby shortening the production period and reducing the production cost.
Then, according to step S4, the dried substrate is subjected to a subsequent process using the patterned photoresist layer as a mask. The subsequent process may include dry etching or ion implantation, wherein if the dry etching is performed on the dried substrate with the patterned photoresist layer as a mask, since the dry etching has anisotropy, that is, substantially only vertical etching but almost no lateral undercutting, and thus a pattern completely identical to the patterned photoresist layer can be reproduced on the substrate, a structure having a specific pattern can be etched on the substrate by combining isotropy of the wet etching and the anisotropy of the dry etching; further, when the substrate after drying is subjected to ion implantation using the patterned photoresist layer as a mask, a graded junction or the like can be formed in the substrate.
Finally, the patterned photoresist layer is removed, as per step S5. Preferably, the step of removing the patterned photoresist layer comprises: firstly, carrying out plasma ashing treatment, and then soaking by adopting a mixed solution of sulfuric acid and hydrogen peroxide. Wherein, the plasma ashing treatment is to react oxygen atoms with the photoresist in a plasma environment to generate carbon monoxide, carbon dioxide, water vapor and the like, and then the generated substances are pumped away by a vacuum-pumping system to remove most of the photoresist; the mixed solution of sulfuric acid and hydrogen peroxide is used for soaking and removing the photoresist which is not completely removed and other residual substances generated in the photoresist removing process so as to completely remove the patterned photoresist layer.
In addition, in other embodiments of the present invention, the steps S2 to S4 may be executed in a loop according to the etching effect on the substrate after each execution of the step S4 until the etching result of the substrate reaches a preset requirement.
Aiming at the process of obtaining the substrate with a specific pattern by wet etching and then dry etching, in the prior art, because the drying temperature adopted by the substrate after the wet etching is high, the patterned photoresist layer is damaged, so that the photoresist needs to be formed twice and the photoresist needs to be removed twice, but the technical scheme of the invention adopts low drying temperature to dry the substrate, although the drying time at low temperature is increased by 2 minutes compared with the drying time at high temperature, the patterned photoresist layer can not be damaged in the low-temperature drying process and can be continuously used in the dry etching process, and further the photoresist needs to be formed once and the photoresist needs to be removed once, so that the production period is shortened by at least 8 hours, the shortened time greatly exceeds the increased drying time, and the technical scheme of the invention greatly shortens the production period, the production cost is reduced.
In summary, the etching method provided by the present invention includes: providing a substrate with a patterned photoresist layer; taking the patterned photoresist layer as a mask, and carrying out wet etching on the substrate; drying the substrate after the wet etching, wherein the drying temperature is 25-35 ℃; taking the patterned photoresist layer as a mask, and carrying out subsequent processes on the dried substrate; and removing the patterned photoresist layer. According to the technical scheme, the substrate after wet etching is dried at a low temperature, so that the dried patterned photoresist layer can be continuously used in the subsequent process, the patterned photoresist layer does not need to be removed and manufactured again, the production period is shortened, and the production cost is reduced.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, in which a substrate is etched by using the etching method described in the above step S1 to step S5 to manufacture the semiconductor device. The subsequent process in the etching method may include dry etching or ion implantation. When the subsequent process in the etching method is dry etching, the semiconductor device may be manufactured by sequentially adopting the wet etching and the dry etching, and the semiconductor device may be a memory, for example, refer to fig. 4a to 4d, and fig. 4a to 4d are device schematic diagrams in the manufacturing method of the semiconductor device according to the embodiment of the present invention. The concrete description is as follows:
referring to fig. 4a, as can be seen from fig. 4a, the substrate 20 has a peripheral region 21 and a storage region 22, a plurality of shallow trench isolation structures 23 are respectively disposed in the substrate 20 in the peripheral region 21 and the storage region 22, a gate oxide layer 24 and a polysilicon gate layer 25 are formed on the top surface of the substrate 20 between adjacent shallow trench isolation structures 23, and the top surface of the shallow trench isolation structures 23 is flush with the top surface of the polysilicon gate layer 25. The patterned photoresist layer 26 completely buries the shallow trench isolation structures 23 and the polysilicon gate layer 25 on the periphery region 21, while exposing the top surfaces of the shallow trench isolation structures 23 and the polysilicon gate layer 25 on the storage region 22. And performing back etching on the shallow trench isolation structures 23 in the storage region 22 by sequentially adopting the wet etching and the dry etching in the etching method, so that the top surface of each shallow trench isolation structure 23 in the storage region 22 is flush with the bottom surface of the gate oxide layer 24. The specific process steps are as follows:
referring to fig. 4b, with the patterned photoresist layer 26 as a mask, wet etching is performed on the shallow trench isolation structure 23 in the storage region 22 to remove a portion of the thickness of the shallow trench isolation structure 23, as can be seen from fig. 4b, after the wet etching, the top surface of the shallow trench isolation structure 23 in the storage region 22 is lower than the top surface of the polysilicon gate layer 25 and higher than the bottom surface of the polysilicon gate layer 25, and an etchant used in the wet etching may include hydrofluoric acid or phosphoric acid.
Then, referring to fig. 4b, the substrate 20 after the wet etching is dried, and the drying temperature is 25 ℃ to 35 ℃ (for example, 28 ℃, 30 ℃, 33 ℃, etc.), and since the drying temperature is low, the patterned photoresist layer 26 is not damaged after drying, and can be continuously used in the subsequent process, thereby shortening the production period and reducing the production cost.
Then, referring to fig. 4c, with the patterned photoresist layer 26 as a mask, performing dry etching on the dried shallow trench isolation structures 23 in the storage region 22 to remove a portion of the thickness of the shallow trench isolation structures 23, and as can be seen from fig. 4c, after the dry etching, the top surface of each shallow trench isolation structure 23 in the storage region 22 is flush with the bottom surface of the gate oxide layer 24, and meanwhile, because the dry etching has anisotropy, the structure of the gate oxide layer 24 is not affected by the dry etching process. The dry etching includes physical etching, chemical etching or physical chemical etching. The physical etching is realized by utilizing the sputtering effect generated by the ion collision on the surface of the etched structure; the chemical etching is realized by generating volatile compounds through the chemical action of activated etching gas and an etched structure; the physical chemical etching is realized by physical and chemical interaction between ions or active groups in plasma and etched structures. The physical chemical etching and the anisotropy effect of the physical etching are superior to the chemical etching, and a proper dry etching method can be selected according to a structure to be etched. For example, a trench required for forming a shallow trench isolation structure is etched in the substrate by using a physical chemical etching method.
Finally, referring to fig. 4d, the patterned photoresist layer 26 is removed.
In addition, a method combining wet etching and dry etching in the etching method described in the above step S1 to step S5 may also be adopted, and in the process of forming the shallow trench isolation structure, the silicon nitride mask layer and the pad oxide layer on the substrate are removed by etching.
In addition, when the subsequent process in the etching method is ion implantation, according to the steps S1 to S5, after wet etching is performed on the substrate with the patterned photoresist layer as a mask, the substrate is dried at a low temperature, and then the ion implantation is performed on the substrate with the patterned photoresist layer as a mask, so as to form a graded junction in the substrate, thereby obtaining the semiconductor device with a high operating voltage.
In summary, the method for manufacturing a semiconductor device provided by the present invention includes: the etching method provided by the invention is adopted to etch a substrate so as to manufacture the semiconductor device. According to the technical scheme, the substrate after wet etching is dried at a low temperature, so that the dried patterned photoresist layer can be continuously used in the process of manufacturing the semiconductor device, the production period is shortened, and the production cost is reduced.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (11)
1. An etching method, comprising:
s1, providing a substrate with a patterned photoresist layer;
s2, taking the patterned photoresist layer as a mask, and carrying out wet etching on the substrate;
s3, placing the substrate subjected to wet etching into a drying box, introducing atomized isopropanol into the drying box to replace the moisture on the surface of the substrate, then exhausting the drying box to bring the water vapor and the atomized isopropanol out of the drying box, and then introducing nitrogen into the drying box to dry the substrate, wherein the drying temperature in the drying box is 25-35 ℃;
s4, taking the patterned photoresist layer as a mask, and carrying out subsequent processes on the dried substrate; and the number of the first and second groups,
and S5, removing the patterned photoresist layer.
2. The etching method according to claim 1, wherein the substrate is directly dried on the wet etching machine, and the drying temperature is set on the wet etching machine.
3. The etching method according to claim 1, wherein the subsequent process comprises dry etching or ion implantation.
4. The etching method according to any one of claims 1 to 3, wherein the steps S2 to S4 are performed in a loop until the etching result of the substrate reaches a preset requirement.
5. The etching method of claim 1, wherein removing the patterned photoresist layer comprises: firstly, carrying out plasma ashing treatment, and then soaking by adopting a mixed solution of sulfuric acid and hydrogen peroxide.
6. The etching method of claim 1, wherein the patterned photoresist layer comprises a positive photoresist or a negative photoresist.
7. A method of manufacturing a semiconductor device, comprising: etching a substrate by using the etching method according to any one of claims 1 to 6 to manufacture the semiconductor device.
8. The method for manufacturing a semiconductor device according to claim 7, wherein a subsequent process in the etching method comprises dry etching or ion implantation.
9. The method of manufacturing a semiconductor device according to claim 8, wherein the substrate has a peripheral region and a storage region, the peripheral region and the storage region having a plurality of shallow trench isolation structures respectively provided therein, a gate oxide layer and a polysilicon gate layer being formed on a top surface of the substrate between adjacent ones of the shallow trench isolation structures, the shallow trench isolation structures having top surfaces flush with a top surface of the polysilicon gate layer; and performing back etching on the shallow trench isolation structures in the storage region by sequentially adopting wet etching and dry etching in the etching method, so that the top surface of each shallow trench isolation structure in the storage region is flush with the bottom surface of the gate oxide layer.
10. The method for manufacturing a semiconductor device according to claim 9, wherein an etchant used for the wet etching includes hydrofluoric acid or phosphoric acid.
11. The manufacturing method of a semiconductor device according to claim 9, wherein the dry etching includes physical etching, chemical etching, or physicochemical etching.
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| CN109461697A (en) | 2019-03-12 |
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