CN103972075A - Etching method and array substrate - Google Patents
Etching method and array substrate Download PDFInfo
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- CN103972075A CN103972075A CN201410187181.3A CN201410187181A CN103972075A CN 103972075 A CN103972075 A CN 103972075A CN 201410187181 A CN201410187181 A CN 201410187181A CN 103972075 A CN103972075 A CN 103972075A
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- etching
- ito
- photoresist layer
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- ito rete
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- 238000005530 etching Methods 0.000 title claims abstract description 90
- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000000758 substrate Substances 0.000 title claims abstract description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 59
- 238000001039 wet etching Methods 0.000 claims abstract description 41
- 238000005516 engineering process Methods 0.000 claims abstract description 29
- 238000001312 dry etching Methods 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 239000007788 liquid Substances 0.000 claims description 6
- 230000001143 conditioned effect Effects 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910003437 indium oxide Inorganic materials 0.000 claims description 4
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000059 patterning Methods 0.000 abstract description 20
- 230000000694 effects Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000001020 plasma etching Methods 0.000 description 7
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000012940 design transfer Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 208000007578 phototoxic dermatitis Diseases 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000935 solvent evaporation Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Weting (AREA)
- Manufacturing Of Electric Cables (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The embodiment of the invention provides an etching method and an array substrate. According to the etching method and the array substrate, the problems that when ITO patterning etching is conducted according to existing array substrate manufacturing scheme, etching is not complete and etching speed is low are solved, the ITO patterning etching effect and practicality of a display panel are improved, the etching rate is increased, and etching cost is reduced. The etching method comprises the steps of forming an ITO film on the substrate; forming a photoresist layer on the ITO film; arranging a mask plate above the photoresist layer, wherein part of the photoresist layer is covered with the mask plate; removing photoresist, not covered with the mask plate, in the photoresist layer; etching off the part, not covered with the photoresist layer, of the ITO film with the wet etching technology; etching off the part, left after the part, not covered with the photoresist layer, of the ITO film is etched off with the wet etching method, of the ITO film with the dry etching technology. The etching method and the array substrate are used in manufacturing of display panels.
Description
Technical field
The present invention relates to display floater manufacture technology field, relate in particular to a kind of lithographic method and array base palte.
Background technology
Along with thin film transistor liquid crystal display screen (Thin Film Transistor Liquid CrystalDisplay, be called for short TFT-LCD) etc. the high speed development of display device, the demand of the transparency electrode to high light transmission rate, super-low resistance is increasing.At present, the most frequently used transparent conductive oxide (Transparent Conducting Oxide during plane shows, being called for short TCO) thin-film material is tin indium oxide (indium tin oxid, be called for short ITO), this is a kind of N type semiconductor material, conductivity and transparent aspect have extremely superior performance.And this material is applied in display device, its patterning is very important factor.
In existing technical scheme, the method for conventional a kind of ITO patterning is wet chemical etch method.But wet chemical etch method is greater than at etching thickness
iTO time, usually there will be etching unclean, there will be even the phenomenon of image short circuit; If adopt the measure such as prolongation etch period, raising etching concentration to solve the sordid problem of etching in wet etching, can affect the useful life of etching apparatus etc.; Meanwhile, extend etch period and there will be the problem that etching is inhomogeneous or etching is excessive, affect the performance of product.Another kind of feasible scheme is to use plasma dry etching.But the etching cost that plasma dry etching method needs in actual application is larger, and etch rate is slower, operate for large-area display floater more difficult, practicality is poor.
Summary of the invention
Embodiments of the invention provide a kind of lithographic method and array base palte, solve and while carrying out ITO patterning etching in existing array base palte production program, occurred the clean and slower problem of etching speed of etching because ITO thickness is excessive, the etching effect of ITO patterning of display floater and practicality are in actual applications strengthened, improve etch rate, meanwhile, reduced etching cost.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, provide a kind of lithographic method, described method comprises:
On substrate, form indium oxide layer tin ITO rete;
On described ITO rete, form one deck photoresist layer;
Above described photoresist layer, mask plate is set, described mask plate not exclusively covers described photoresist layer;
Dispel the photoresist not covered by described mask plate in described photoresist layer;
Adopt wet-etching technology to etch away the described ITO rete not covered by described photoresist layer in described ITO rete;
Adopt dry etch process to etch away in the described ITO rete not covered by described photoresist layer in described ITO rete by ITO rete residual after described wet-etching technology etching.
Optionally, described method also comprises:
Dispel in described photoresist layer by remaining photoresist after described wet-etching technology and described dry etch process etching.
Optionally, described method also comprises:
The etching apparatus adopting according to dry etching, the etching condition arranging in the described etching apparatus while adopting ITO rete described in dry etch process etching meets pre-conditioned.
Optionally, the thickness of the described ITO rete on described substrate is greater than default thickness.
Optionally, described method also comprises:
While adopting described in wet-etching technology etching ITO rete, the concentration that the etching liquid of described wet etching is set is less than or equal to preset concentration.
On the other hand, provide a kind of array base palte, described array base palte comprises:
Substrate;
Cover the ITO pixel electrode layer of described substrate, described ITO pixel electrode layer is to adopt the manufacturing process that wet-etching technology and dry etch process combine to make formation.
The lithographic method that embodiments of the invention provide and array base palte, by adopting the scheme that wet-etching technology and dry etch process combine to form ITO pixel electrode layer in the time making the array base palte of display floater, solve and while carrying out ITO patterning etching in existing array base palte production program, occurred the clean and slower problem of etching speed of etching because ITO thickness is excessive, the etching effect of ITO patterning of display floater and practicality are in actual applications strengthened, improve etch rate, meanwhile, reduced etching cost.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The schematic flow sheet of a kind of lithographic method that Fig. 1 provides for embodiments of the invention;
The schematic flow sheet of the another kind of lithographic method that Fig. 2 provides for embodiments of the invention;
Structure one schematic diagram in ITO pixel electrode layer manufacturing process in a kind of array base palte that Fig. 3 provides for embodiments of the invention;
Structure two schematic diagrames in ITO pixel electrode layer manufacturing process in a kind of array base palte that Fig. 4 provides for embodiments of the invention;
Structure three schematic diagrames in ITO pixel electrode layer manufacturing process in a kind of array base palte that Fig. 5 provides for embodiments of the invention;
Structure four schematic diagrames in ITO pixel electrode layer manufacturing process in a kind of array base palte that Fig. 6 provides for embodiments of the invention;
Structure five schematic diagrames in ITO pixel electrode layer manufacturing process in a kind of array base palte that Fig. 7 provides for embodiments of the invention;
Structure six schematic diagrames in ITO pixel electrode layer manufacturing process in a kind of array base palte that Fig. 8 provides for embodiments of the invention.
Reference numeral: 1-substrate; 2-ITO rete; 3-photoresist layer; 4-mask plate; The ITO that 21-is residual.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Embodiments of the invention provide a kind of lithographic method, and shown in Fig. 1, the method comprises the following steps:
101, on substrate, form indium oxide layer tin ITO rete.
102, on ITO rete, form one deck photoresist layer.
Wherein, this photoresist can be to form by the mode of even coating.
103, mask plate is set above photoresist layer.
Wherein, mask plate not exclusively covers photoresist layer.
Wherein, mask plate can independently carry in equipment, does not produce and contacts with photoresist layer.
104, dispel the photoresist not covered by mask plate in photoresist layer.
105, adopt wet-etching technology to etch away the ITO rete not covered by photoresist layer in ITO rete.
106, adopt dry etch process to etch away in the ITO rete not covered by photoresist layer in ITO rete by residual ITO rete after wet-etching technology etching.
The lithographic method that embodiments of the invention provide, by adopting the scheme that wet-etching technology and dry etch process combine to form ITO pixel electrode layer in the time making the array base palte of display floater, solve and while carrying out ITO patterning etching in existing array base palte production program, occurred the clean and slower problem of etching speed of etching because ITO thickness is excessive, the etching effect of ITO patterning of display floater and practicality are in actual applications strengthened, improve etch rate, meanwhile, reduced etching cost.
Embodiments of the invention provide a kind of lithographic method, and shown in Fig. 2, the method comprises the following steps:
201, on substrate, form indium oxide layer tin ITO rete.
Concrete, on substrate 1, form the process of ITO rete 2 as shown in Figure 3, can be on for example glass substrate of preprepared substrate or quartz base plate, to form the ITO rete 2 that covers this substrate 1 in the mode of magnetron sputtering by vacuum coating equipment.Certainly, just illustrate herein and form the mode of ITO rete and the type of substrate, be not limited to form by the mode of magnetron sputtering the type of ITO rete and substrate, in actual application, can select applicable substrate and appropriate mode to form ITO rete according to concrete implementation environment.Wherein, substrate can be the substrate of display pannel, or the substrate of color filer, or glass substrate or flexible base, board etc., does not do concrete restriction herein.
The thickness of the ITO rete on substrate is greater than default thickness, and generally the thickness of default thickness can be
.Certainly just illustrate the thickness of default thickness herein, specifically do not limit ITO thickness and can only be
.In concrete application, can select optimum ITO thicknesses of layers numerical value as default thickness with application scenarios according to the actual needs.
202, on ITO rete, form one deck photoresist layer.
Wherein, form the process of photoresist layer 3 as shown in Figure 4, can be on ITO rete 2, to form one deck by the mode of coating to cover the photonasty photoresist of this ITO rete 2, and then form photoresist layer 3.
On ITO rete, be evenly coated with photonasty photoresist, this photonasty photoresist is positive photoresist, is formed on ITO rete with the mode adequate relief of rotary coating.The thicknesses of layers of photonasty photoresist need be taken into account protection and the etch period to ITO, is generally 1.0-1.2 μ m.The coating procedure of photoresist needs front baking and rear baking, and object is by the solvent evaporation in this photonasty photoresist, increases the bonding force of ITO rete and this photonasty photoresist simultaneously.
203, mask plate is set above photoresist layer.
Wherein, mask plate not exclusively covers photoresist layer.
204, dispel the photoresist not covered by mask plate in photoresist layer.
Concrete, be illustrated in figure 5 the schematic diagram using after mask plate 4 patterning photoresist layers 3, can be use mask plate 4 by composition art pattern CAD allelopathic photosensitiveness photoresist layers 3 such as exposure, development and etchings with formation patterning photosensitive layer.
205,, while adopting wet-etching technology etching ITO rete, the concentration that the etching liquid of wet etching is set is less than or equal to preset concentration.
Etching liquid concentration in the wet etching of the ITO lithographic method providing in the present embodiment can be than little 5% left and right of concentration of etching liquid in general existing wet etching, etch period can reduce about 3 seconds than the etch period of existing volume wet-etching technology, and the temperature of etching apparatus can adopt the arbitrary Temperature numerical that can complete wet etching in existing scheme.
206, adopt wet-etching technology to etch away the ITO rete not covered by photoresist layer in ITO rete.
Be illustrated in figure 6 and remove after mask plate, with wet-etching technology by the design transfer of patterning photosensitive layer to ITO rete.Wherein, as shown in Figure 6 can residual a part of ITO21 after wet-etching technology etching.
Wherein, a kind of etch mode of feasible wet etching is spray model.
207, the etching apparatus adopting according to dry etching, the etching condition arranging in the etching apparatus while adopting dry etch process etching ITO rete meets pre-conditioned.
Wherein, in the present embodiment, the equipment of available dry etching comprises: inductively coupled plasma (Inductively Coupled Plasma, be called for short ICP) equipment, plasma etching (plasmaetching, be called for short PE) equipment, reactive ion etching (Reactive Ion Etching is called for short RIE) equipment etc.Because the etching injury of ICP equipment is larger, the etch rate of PE equipment is slower, and therefore, in the present embodiment, preferably the etching apparatus of dry etching is RIE equipment.
When adopting RIE equipment to carry out dry etching, can be set: etching power is 100-1000w pre-conditioned comprising, pressure is 10-400 millitorr mtorr, and the gas of use can comprise below the combination of or Arbitrary Term: He, CHF
3, Cl
2, Ar, C
2h
4.For example, etching effect preferably the etching condition of feasible dry etching can comprise: power is 1000W, and pressure is 40mtorr, gas flow ratio He/Cl
2=100/300sccm; Power is 1000W, and pressure is 40mtorr, gas flow ratio He/Cl
2=50/300sccm.Now the etch rate of corresponding amorphous ITO is respectively
etching homogeneity is respectively 8.5% and 6.8%.When power is 1000W, pressure is 40mtorr, gas flow ratio He/Cl
2under=100/300sccm condition, corresponding to the etch rate of the ITO of polycrystalline state be
etching homogeneity is 11.1%.It should be noted that and just illustrate the etching condition that adopts dry etching herein, can select applicable etching condition as pre-conditioned according to concrete running environment in actual applications.
It should be noted that etching condition that step 207 arranges dry etching can be that arbitrary step before step 208 adopts the step of dry etch process etching residue ITO is carried out, and also can carry out with step 208 simultaneously.Concrete enforcement order can select suitable order to carry out according to the needs of actual motion environment.
208, adopt dry etch process to etch away in the ITO rete not covered by photoresist layer in ITO rete by residual ITO rete after wet-etching technology etching.
As shown in Figure 7 for adopting dry etch process to etch away completely in ITO rete by the structure chart of ITO residual after wet-etching technology etching.
209, dispel in photoresist layer by remaining photoresist after wet-etching technology and dry etch process etching.
Wherein, as shown in Figure 8, can dispel remaining photonasty photoresist layer on substrate with stripper.
The time that it should be noted that wet etching in the present embodiment can be to determine according to the residual thickness of the ITO thickness of etching and the wet-etch rate of selecting, and generally adopts the remaining ITO thickness of wet etching should be less than 5% of original I TO thickness; The time of dry etching can be according to calculating by the thickness of remaining ITO after wet etching and the etch rate of dry etching in ITO rete.
ITO lithographic method in this enforcement, unwanted ITO in the patterning ITO rete that adopts first wet etching to fall need to obtain, then after adopting dry etch process to etch away by wet etching, remain in all ITO of relevant position, the final ITO rete that forms the patterning needing, the quality of improving product greatly, the etching homogeneity of avoiding single employing wet etching to occur is not high, the especially larger problem of key size deviation control difficulty.Lithographic method in employing this programme can obtain the ITO rete of the patterning needing, the service time that can improve equipment very easily.Meanwhile, the plasma gas of the lithographic method in the present embodiment in adopting when dry etching can be had an effect with photoresist, make follow-up while carrying out photoresist lift off more fast, easily and thoroughly.
The lithographic method that embodiments of the invention provide, by adopting the scheme that wet-etching technology and dry etch process combine to form ITO pixel electrode layer in the time making the array base palte of display floater, solve and while carrying out ITO patterning etching in existing array base palte production program, occurred the clean and slower problem of etching speed of etching because ITO thickness is excessive, the etching effect of ITO patterning of display floater and practicality are in actual applications strengthened, improve etch rate, meanwhile, reduced etching cost.And then, can enhance productivity.
Embodiments of the invention provide a kind of array base palte, and this array base palte comprises: the ITO pixel electrode layer of substrate and covered substrate.
Wherein, this ITO pixel electrode layer is to adopt the manufacturing process that wet-etching technology and dry etch process combine to make formation.
The array base palte that embodiments of the invention provide, by the scheme that adopts wet-etching technology and dry etch process to combine when the ITO pixel electrode layer forming in array base palte, solve and while carrying out ITO patterning etching in existing array base palte production program, occurred the clean and slower problem of etching speed of etching because ITO thickness is excessive, the etching effect of ITO patterning of display floater and practicality are in actual applications strengthened, improve etch rate, meanwhile, reduced etching cost.And then, can enhance productivity.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (6)
1. a lithographic method, is characterized in that, described method comprises:
On substrate, form indium oxide layer tin ITO rete;
On described ITO rete, form one deck photoresist layer;
Above described photoresist layer, mask plate is set, described mask plate not exclusively covers described photoresist layer;
Dispel the photoresist not covered by described mask plate in described photoresist layer;
Adopt wet-etching technology to etch away the described ITO rete not covered by described photoresist layer in described ITO rete;
Adopt dry etch process to etch away in the described ITO rete not covered by described photoresist layer in described ITO rete by ITO rete residual after described wet-etching technology etching.
2. method according to claim 1, is characterized in that, described method also comprises:
Dispel in described photoresist layer by remaining photoresist after described wet-etching technology and described dry etch process etching.
3. method according to claim 1 and 2, is characterized in that, described method also comprises:
The etching apparatus adopting according to dry etching, the etching condition arranging in the described etching apparatus while adopting ITO rete described in dry etch process etching meets pre-conditioned.
4. method according to claim 1 and 2, is characterized in that,
The thickness of the described ITO rete on described substrate is greater than default thickness.
5. method according to claim 1 and 2, is characterized in that, described method also comprises:
While adopting described in wet-etching technology etching ITO rete, the concentration that the etching liquid of described wet etching is set is less than or equal to preset concentration.
6. an array base palte, is characterized in that, described array base palte comprises:
Substrate;
Cover the ITO pixel electrode layer of described substrate, described ITO pixel electrode layer is to adopt the manufacturing process that wet-etching technology and dry etch process combine to make formation.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410187181.3A CN103972075A (en) | 2014-05-05 | 2014-05-05 | Etching method and array substrate |
| PCT/CN2014/091708 WO2015169081A1 (en) | 2014-05-05 | 2014-11-19 | Ito film etching method and array substrate comprising electrode layers formed by same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410187181.3A CN103972075A (en) | 2014-05-05 | 2014-05-05 | Etching method and array substrate |
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|---|---|
| CN103972075A true CN103972075A (en) | 2014-08-06 |
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| WO (1) | WO2015169081A1 (en) |
Cited By (9)
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| WO2015169081A1 (en) * | 2014-05-05 | 2015-11-12 | 京东方科技集团股份有限公司 | Ito film etching method and array substrate comprising electrode layers formed by same |
| CN105511176A (en) * | 2016-01-29 | 2016-04-20 | 京东方科技集团股份有限公司 | Preparation method of array substrate |
| CN105914577A (en) * | 2016-06-28 | 2016-08-31 | 杭州华锦电子有限公司 | Etching method of laser multi-electrode tube packaging base |
| CN109461697A (en) * | 2018-11-09 | 2019-03-12 | 武汉新芯集成电路制造有限公司 | The manufacturing method of lithographic method and semiconductor devices |
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| CN111752017A (en) * | 2019-03-28 | 2020-10-09 | 合肥精显电子科技有限公司 | ITO pattern etching process for LCD production |
| CN113341070A (en) * | 2021-05-26 | 2021-09-03 | Tcl华星光电技术有限公司 | Method for evaluating etching solution |
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| WO2015169081A1 (en) * | 2014-05-05 | 2015-11-12 | 京东方科技集团股份有限公司 | Ito film etching method and array substrate comprising electrode layers formed by same |
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| CN105914577B (en) * | 2016-06-28 | 2019-05-03 | 杭州华锦电子有限公司 | Etching method of laser multi-electrode tube packaging base |
| CN109461697A (en) * | 2018-11-09 | 2019-03-12 | 武汉新芯集成电路制造有限公司 | The manufacturing method of lithographic method and semiconductor devices |
| CN109713159A (en) * | 2018-12-26 | 2019-05-03 | 上海晶合光电科技有限公司 | A kind of top electrode is patterned with the preparation method of organic electroluminescence devices |
| CN111384184A (en) * | 2018-12-27 | 2020-07-07 | 北京铂阳顶荣光伏科技有限公司 | Preparation method of electrode of solar cell |
| CN111384185A (en) * | 2018-12-28 | 2020-07-07 | 北京铂阳顶荣光伏科技有限公司 | Electrode machining method |
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| CN113341070A (en) * | 2021-05-26 | 2021-09-03 | Tcl华星光电技术有限公司 | Method for evaluating etching solution |
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