CN100479118C - Method for removing photoresist, and method for fabricating semiconductor component - Google Patents
Method for removing photoresist, and method for fabricating semiconductor component Download PDFInfo
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- CN100479118C CN100479118C CNB2005101193290A CN200510119329A CN100479118C CN 100479118 C CN100479118 C CN 100479118C CN B2005101193290 A CNB2005101193290 A CN B2005101193290A CN 200510119329 A CN200510119329 A CN 200510119329A CN 100479118 C CN100479118 C CN 100479118C
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Abstract
The method carries out pre-processing procedure for substrate before photoresist layer is formed. The said pre-processing procedure is a plasma technical procedure for example. Being applicable to preparation of semiconductor element, the method prevents photoresist from cracking, maintains integrality of semiconductor element, and promotes rate for removing photoresist layer in use for ion implantation mask.
Description
Technical field
The present invention relates to a kind of semiconductor device manufacturing method, relate in particular to a kind of semiconductor device manufacturing method that photoresist is removed efficient of promoting.
Background technology
Photoetching (Photolithography) technology is in the whole integrated circuit technology, one of the most very important key.The employed photoresist layer of photoetching process behind the dry-etching, behind the Wet-type etching or after the ion implantation technology, must be removed totally, up hill and dale to avoid influencing follow-up technology.
Yet there is different influences in the characteristic regular meeting of photoresist because of the difference of the technology of being carried out.For instance, in ion implantation technology, the photoresist surface makes its surface hardening because of ion implantation technology, making photoresist remove is difficult for, and because its surface hardening in ashing (Ashing) process, easily causes photoresist to split (Popping) cruelly.Generally speaking, be difficult for to take place, can in podzolic process, add carbon tetrafluoride usually, or in wet-cleaned subsequently, utilize high temperature (70 degree Celsius) or in RCA solution, add dilute hydrofluoric acid (DHF) and achieve the goal for making photoresist split phenomenon cruelly.Yet these two kinds of methods also can consume the partial oxidation layer on the substrate when removing photoresist, and influence the performance of element.
The problem that causes for fear of above-mentioned high temperature RCA solution with the performance of control element effectively, after ion implantation technology, does not extensively have the ashing of carbon tetrafluoride, and adopts the low temperature RCA solution that does not add DHF to remove photoresist.Yet the efficient or the removing speed that remove photoresist with the ashing of no carbon tetrafluoride and the low temperature RCA solution that do not add DHF are relatively poor, and often photoresist can't be removed fully.Therefore, the removal of the photoresist after ion implantation technology technology still must be improved.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of semiconductor element is to improve the photoresist elimination efficiency after ion injects.
A further object of the present invention provides a kind of manufacture method of semiconductor element, to increase the process margin (Process Window) that photoresist is removed.
The present invention proposes a kind of manufacture method of semiconductor element.The method is to form grid on substrate, and forms light dope source electrode/drain region in substrate.Afterwards, the sidewall at grid forms clearance wall.Then, grid structure, clearance wall and the substrate that is exposed carried out pre-treating technology.Afterwards, forming patterning photoresist layer on substrate, then, is mask with this patterning photoresist layer, grid structure and clearance wall, carries out ion implantation technology, to form source/drain regions in substrate.Afterwards, remove this patterning photoresist layer.
Described according to one embodiment of the invention, pre-treating technology for example is a plasma process, the employed gas of this plasma process be selected from group that hydrogen, oxygen, nitrogen, nitrous oxide, water and combination thereof form one of them.The temperature range of this plasma process is between 100 to 260 degree.
Described according to one embodiment of the invention, after above-mentioned sidewall at grid forms the step of clearance wall, also comprise a cleaning step before the pre-treating technology, to remove formed polymer in the process that forms clearance wall.
Described according to one embodiment of the invention, the step of this patterning photoresist layer of above-mentioned removal for example is ashing (Ashing) technology and the cleaning of cleaning with cleaning fluid.This cineration technics comprises the plasma process that does not contain carbon tetrafluoride.In addition, this cleaning fluid does not contain the hydrofluoric acid of dilution.
The present invention carried out pre-treating technology before patterning photoresist layer forms, can avoid patterning photoresist layer to produce photoresist when ashing and split (Popping), the component structure that is kept perfectly and performance cruelly and make the removing technology of patterning photoresist layer have higher process margin and higher efficient.
The present invention reintroduces a kind of method of promoting the clearance of the photoresist layer that the ion injecting mask uses, and the method is that substrate is provided earlier, before forming a photoresist layer, this substrate is carried out a pre-treating technology then.
Described according to one embodiment of the invention, wherein pre-treating technology for example is a plasma process.The employed gas of this plasma process be selected from group that hydrogen, oxygen, nitrogen, nitrous oxide, water and combination thereof form one of them.The temperature range of this plasma process is between 100 to 260 degree.
The present invention promptly handled the efficient that this pre-treating technology can avoid photoresist to produce the phenomenon of splitting cruelly, the component structure that is kept perfectly and performance and increase follow-up removal photoresist when ashing to substrate surface with pre-treating technology before the photoresist pattern that the ion implantation technology mask is used forms.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the manufacture method flow chart of steps of semiconductor element of the present invention;
Fig. 2 A to Fig. 2 C is the section flow chart of the manufacture method of semiconductor element of the present invention;
Fig. 3 is applied to the photo of an example for pre-treating technology of the present invention;
Fig. 4 is applied to the photo of another example for pre-treating technology of the present invention;
Fig. 5 is the photo of comparative example 1.
The main element symbol description
100,102,104,106,108: step
200: substrate
201: isolation structure
202: grid oxic horizon
204: grid
205: the compensate for clearance wall
206: light dope source electrode/drain region
207,210: patterning photoresist layer
209,214: ion implantation technology
208: clearance wall
212: source/drain regions
Embodiment
The method step flow chart of the clearance of the photoresist layer that Fig. 1 uses for enhancement ion injecting mask of the present invention.Please refer to Fig. 1, carry out step 100, a substrate is provided, this substrate for example is a silicon substrate, or disposes the member of logic element or memory component, for example grid structure, grid oxic horizon and various light doping sections etc.
Afterwards, carry out step 102, this substrate is carried out pre-treating technology.Pre-treating technology for example is a plasma process.The employed gas of this plasma process be selected from group that hydrogen, oxygen, nitrogen, nitrous oxide, water and combination thereof form one of them.The temperature range of this plasma process is between 100 to 260 degree.This plasma process can form one deck resilient coating on substrate, the photoresist of substrate and follow-up formation is separated, and increased the efficient that photoresist is removed.
Then, carry out step 104, on this substrate, form patterning photoresist layer.Then, carry out step 106, is mask with this patterning photoresist layer, carries out ion implantation technology, forms doped region in substrate.This doped region for example is a source/drain regions.Because the existence of above-mentioned resilient coating, the bubble in the photoresist can be derived to the external world via resilient coating in podzolic process subsequently, and that therefore can avoid bubble in the photoresist to discharge being produced splits phenomenon cruelly.
Afterwards, carry out step 108, remove this patterning photoresist layer.The removal method of this patterning photoresist layer for example is to utilize earlier the oxygen plasma that does not contain carbon tetrafluoride to carry out ashing (Ashing), utilizes cleaning of the RCA solution that do not conform to dilute hydrofluoric acid then.The clean method of this RCA solution for example cleans with the mixed solution of Celsius 20 to 30 ammonium hydroxide, hydrogen peroxide and the deionized waters of spending, and the mixed solution with Celsius 20 to 30 hydrochloric acid, hydrogen peroxide and the deionized waters of spending cleans again.
The present invention carried out pre-treating technology before patterning photoresist layer forms, can avoid patterning photoresist layer to produce in cineration technics and split phenomenon, the component structure that is kept perfectly and performance cruelly and make the removing technology of patterning photoresist layer have higher process margin and higher efficient.
Fig. 2 A to Fig. 2 C is the section flow chart of semiconductor device manufacturing method of the present invention, is that example illustrates at this with general MOS element.Please refer to Fig. 2 A, at first on the substrate 200 that forms isolation structure 201, form grid oxic horizon 202 and grid 204.The material of grid oxic horizon 202 for example is a silica, and its formation method for example is a thermal oxidation method.The material of grid 204 for example is a polysilicon, and its formation method for example is Low Pressure Chemical Vapor Deposition (LPCVD).Then, on the sidewall of grid 204, form compensate for clearance wall 205.The formation method of compensate for clearance wall 205 for example is to form one dielectric layer with chemical vapour deposition technique on substrate 200, carries out an anisotropic etching process then with this dielectric layer of etch-back.Afterwards, carry out the thin oxygen annealing in process of a high temperature, so that when making grid 204 with compensate for clearance wall 205, the defective that is produced on grid 204 and substrate 200 surfaces makes lattice rearrange the back by the thin oxygen annealing in process of this high temperature and eliminates.Then, in substrate 200, form light dope source electrode/drain region 206.Light dope source electrode/drain region 206 for example is a N type light doping section, its formation method for example is to be mask with a patterning photoresist layer 207, carries out an ion implantation technology 209 to form.
Then, remove patterning photoresist layer 207.The method of removing patterning photoresist layer 207 for example is to remove most of patterning photoresist layer 207 with oxygen gas plasma earlier, removes patterning photoresist layer 207 with low temperature RCA sweep-out method again.This low temperature RCA sweep-out method for example is to clean with the mixed solution of ammonium hydroxide, hydrogen peroxide and deionized water earlier at 20 to 30 degree Celsius, cleans in the mixed solution of 20 to 30 degree Celsius with hydrochloric acid, hydrogen peroxide and deionized water again.
Afterwards, please refer to Fig. 2 B, form clearance wall 208 in grid 204 both sides.The formation method of clearance wall 208 is earlier to form silica or silicon nitride or aforementioned both composite bed with chemical vapour deposition technique on substrate 200, carries out anisotropic etching process then, up to exposing grid 204 and part substrate 200.Above-mentioned anisotropic etching process can be followed the reaction of formation of high molecular polymer, then carries out a cleaning step, to remove formed polymer in the process that forms clearance wall 208.This cleaning step for example is the clean method that utilizes RCA solution.The clean method of this RCA solution for example cleans with the mixed solution of ammonium hydroxide, hydrogen peroxide and deionized water earlier at 70 to 80 degree Celsius, cleans in the mixed solution of 70 to 80 degree Celsius with hydrochloric acid, hydrogen peroxide and deionized water again.
Then, grid 204, clearance wall 208 and the substrate 200 that is exposed carried out a pre-treating technology.This pre-treating technology for example is a plasma process.The employed gas of this plasma process be selected from group that hydrogen, oxygen, nitrogen, nitrous oxide, water and combination thereof form one of them, and the temperature range of technology is between 100 to 260 degree.This plasma process can form the resilient coating (not illustrating) of one deck stealth on substrate 200, the substrate 200 and the photoresist of follow-up formation are separated, and increased the efficient that photoresist is removed.
On substrate 200, form patterning photoresist layer 210.This patterning photoresist layer 210 is cover gate 204, light dope source electrode/drain region 206 and clearance wall 208 not.Afterwards, be mask with patterning photoresist layer 210, grid 204 and clearance wall 208, in substrate 200, form source/drain regions 212.Source/drain regions 212 for example is with ion implantation technology 214 formed N type heavily doped regions.
Afterwards, removing photoresist layer 210, for example is to clean with oxygen gas plasma earlier, removes this patterning photoresist layer 210 with low temperature RCA sweep-out method again, and forms the MOS component structure that is illustrated as Fig. 2 C.This low temperature RCA sweep-out method can adopt aforesaid low temperature RCA sweep-out method, so repeat no more.
Example 1
On a substrate, form a shallow slot isolation structure (STI), then, before carrying out pre-treating technology, measure the thickness of height, the degree of depth and the clearance wall of shallow slot isolation structure on substrate earlier, then, carry out pre-treating technology with the hydrogen and the nitrogen gas plasma of 100 to 260 degree; Then, measure the thickness of height, the degree of depth and the clearance wall of shallow slot isolation structure on substrate once more, its result is as shown in table 1.Then, form patterning photoresist layer, and be that mask carries out ion implantation technology, in substrate, to form doped region with this patterning photoresist layer.Then, clean with the RCA cleaning fluid that does not contain dilute hydrofluoric acid of the ashing that do not contain carbon tetrafluoride and room temperature, to remove this patterning photoresist layer, its result as shown in Figure 3.
Example 2
2 employing methods of example are identical with example 1, but pre-treating technology is to carry out its result such as table 1 and shown in Figure 4 with the oxygen gas plasma that 100 to 260 is spent.
Table 1
The result of table 1 show before the above-mentioned pre-treating technology with afterwards each dimension measurement result all within the error in measurement scope, the expression pre-treating technology can not influence each scantling on this MOS transistor surface.The photo of Fig. 3 and Fig. 4 shows employing method of the present invention, and it is residual not have photic resist.
Comparative example 1
Comparative example 1 is a control experiment, and it adopts the method identical with example 1, but, before injecting the ion step, not passing through pre-treating technology of the present invention, its result is as shown in Figure 5.Please refer to Fig. 5, still have photoresist residual in its demonstration doped region.
It is residual that the result of example 1 and example 2 and comparative example 1 shows that method of the present invention not only can thoroughly be removed photoresist, and can promote the removal efficient of the photoresist layer that the ion injecting mask uses.In addition, the present invention carried out pre-treating technology before patterning photoresist layer forms, can adopt the cleaning fluid of low temperature to remove photoresist, and can finish the technology of removing photoresist in the short period of time, and can improve the nargin of technology.What in addition, the present invention can avoid photoresist splits phenomenon and component structure that is kept perfectly and performance cruelly.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (8)
1. the manufacture method of a semiconductor element comprises:
On a substrate, form a grid;
In this substrate, form a light dope source electrode/drain region;
Sidewall at this grid forms a clearance wall;
This grid, this clearance wall and this substrate that is exposed carried out a pre-treating technology, and wherein this pre-treating technology comprises a plasma process;
On this substrate, form a patterning photoresist layer;
With this patterning photoresist layer, this grid and this clearance wall is mask, carries out ion implantation technology, to form source in this substrate; And
Remove this patterning photoresist layer.
2. the manufacture method of semiconductor element as claimed in claim 1, wherein the employed gas of this plasma process be selected from group that hydrogen, oxygen, nitrogen, nitrous oxide, water and combination thereof form one of them.
3. the manufacture method of semiconductor element as claimed in claim 1, wherein the temperature range of this plasma process is between 100 to 260 degree.
4. the manufacture method of semiconductor element as claimed in claim 1 wherein after the sidewall of this grid forms the step of this clearance wall, also comprises a cleaning step, to remove formed polymer in the technology that forms this clearance wall.
5. the manufacture method of semiconductor element as claimed in claim 4, wherein this pre-treating technology be after this cleaning step and form this patterning photoresist layer step before carry out.
6. the manufacture method of semiconductor element as claimed in claim 1, the step of wherein removing this patterning photoresist layer comprises the cleaning of a cineration technics and a cleaning fluid.
7. the manufacture method of semiconductor element as claimed in claim 6, wherein this cineration technics comprises plasma process, this plasma process does not contain carbon tetrafluoride.
8. the manufacture method of semiconductor element as claimed in claim 6, wherein this cleaning fluid does not contain the hydrofluoric acid of dilution.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005101193290A CN100479118C (en) | 2005-11-03 | 2005-11-03 | Method for removing photoresist, and method for fabricating semiconductor component |
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| CNB2005101193290A CN100479118C (en) | 2005-11-03 | 2005-11-03 | Method for removing photoresist, and method for fabricating semiconductor component |
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| CN101593697B (en) * | 2008-05-30 | 2012-01-18 | 中芯国际集成电路制造(北京)有限公司 | Doped region and well region forming method and substrate imaging method |
| CN109712872B (en) * | 2018-12-29 | 2021-02-02 | 上海华力集成电路制造有限公司 | Method for enhancing ion implantation photoetching process window of semiconductor device |
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