CN109413356A - A kind of HDMI high image quality synchronization de interlacing system and method - Google Patents
A kind of HDMI high image quality synchronization de interlacing system and method Download PDFInfo
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- CN109413356A CN109413356A CN201811502909.1A CN201811502909A CN109413356A CN 109413356 A CN109413356 A CN 109413356A CN 201811502909 A CN201811502909 A CN 201811502909A CN 109413356 A CN109413356 A CN 109413356A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
- H04N7/012—Conversion between an interlaced and a progressive signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The present invention relates to a kind of synchronous de interlacing system and methods of HDMI high image quality, and MCU control module is connected the first FPGA module by synchronised clock bus and realizes the synchronization of multi-channel video signal to provide synchronised clock for the first FPGA module；Meanwhile first FPGA module open interlace signal memory block and progressive signal memory block, to realize the conversion of interlace signal to progressive signal, complete de-interlace operation.It can be realized the synchronization between multiple HDMI input signals and de interlacing, guarantee the quality of rear end output video pictures.
Description
Technical field
The present invention relates to video processor technical fields, and in particular to a kind of synchronous de interlacing system of HDMI high image quality and side
Method.
Background technique
Video processor is a kind of with a variety of inputs letters such as support VGA, composite video, sdi signal and number HDMI
The video data processing device of number function.Hitachi, Panasonic, Philip, Silicon Image, Sony, Thomson, east in 2002
Totally seven companies have set up HDMI tissue to sesame, have promulgated High-definition Digital Multimedia Interface HDMI standard.HDMI agreement passes through
To vision signal, audio signal and the time-division control for controlling signal, transmission while realizing audio-video.The signal of HDMI transmits
During process includes 3: video data transmission phase, island data transfer period and control data transfer period are transmitted in island data
There is audio data and auxiliary data (information frame and field line synchronising signal) on HDMI data line in phase, and synchronization signal can be very
Single channel HDMI audio-visual synchronization is realized well.But each input interface of tradition HDMI input module is without unified synchronous sequence, this is just
Lead to multiple HDMI signals ununified synchronizing information each other, can not just be synchronized between multiple HDMI input signals, this is just
The picture video for causing video processor to be spliced into is asynchronous, influences customer experience.
In addition, tradition HDMI system does not have de-interlacing Deinterlace algorithm function, de-interlacing is by alternating expression
(interlace) method that vision signal is converted to gradual (progressive) progressive-scan video signal.And it is now novel
Display equipment be all directly to play alternating expression image in progressive scan equipment using progressive scan and can generate serious flashing
Phenomenon, and because two row of alternating expression signal only has a line to have image, another row is then completely black, so progressive signal is compared in brightness
Half can be reduced.
In view of this, the present inventor carries out going deep into design for problems existing for above-mentioned HDMI system, and then propose
The present invention.
Summary of the invention
The purpose of the present invention is to provide a kind of synchronous de interlacing system and methods of HDMI high image quality, can be realized multiple
Synchronization and de interlacing between HDMI input signal guarantee the quality of rear end output video pictures.
To achieve the above object, the technical solution adopted by the present invention is that:
A kind of HDMI high image quality synchronization de interlacing system comprising balanced and module of unstringing, the first FPGA module, the 2nd FPGA mould
Block, MCU control module, clock IC, synchronised clock bus and backboard transmission module,
Described balanced and module of unstringing realizes that input terminal connects HDMI input interface using IT6604 chip, and output end then connects
The signal input part of the first FPGA module is connect, the input end of clock of first FPGA module then passes through synchronised clock bus and connects
MCU control module, output end then connect the signal input part of the second FPGA module；The input end of clock of second FPGA module
MCU control module and backboard transmission module are connected by synchronised clock bus, output end then connects the driving of TMDS high speed signal
Module；The TDMS high speed signal drive module realizes that input terminal connects the second FPGA module, defeated using SIL9134 chip
Outlet then connects backboard transmission module；
First FPGA module has opened up interlace signal memory block and progressive signal memory block, the interlace signal memory block packet
Include interlacing Y-signal memory block, the signal storage interlacing UV；Progressive signal memory block include line by line Y-signal memory block, line by line UV believe
Number memory block；
Interlacing Y-signal memory block is used to store the Y-signal of even number line and the Y-signal of odd-numbered line, the Y-signal and odd number of the even number line
Capable Y-signal is stored in interlacing Y-signal memory block in the way of being stored separately；The interlacing UV stores idol in signal storage
Several rows of UV signal and the UV signal of odd-numbered line, the UV signal of the even number line and the UV signal of odd-numbered line are in the way of being stored separately
It is stored in the signal storage interlacing UV；The Y-signal arranged line by line is stored in the memory block of Y-signal line by line；The UV line by line
The UV signal arranged line by line is stored in signal storage.
Described balanced and module of unstringing is realized using IT6604 chip.
The TDMS high speed signal drive module is realized using SIL9134 chip.
A kind of HDMI high image quality synchronization interlace-removing method uses a kind of synchronous de interlacing system of above-mentioned HDMI high image quality
System, specifically includes the following steps:
High speed HDMI signal of at least two-way after transmitting at a distance is sent into balanced and module of unstringing by step 1, is carried out balanced
Processing and format conversion, obtain the TTL signal of the yuv format of low speed signal；
The TTL signal of the yuv format of at least two-way is sent into the first FPGA module by step 2, synchronizes processing and de interlacing
Processing, specific as follows:
When first FPGA module receives multichannel TTL signal, judge whether the synchronised clock for receiving MCU control module output,
If being not received by synchronised clock, the input of synchronised clock is continued waiting for；When receiving synchronised clock, the first FPGA module
Processing is synchronized to multichannel TTL signal according to synchronised clock；
After the completion of synchronization process, de interlacing processing is carried out to the TTL signal after synchronizing:
First FPGA module hews out interlace signal memory block and progressive signal memory block, wherein interlace signal memory block includes
Interlacing Y-signal memory block, the signal storage interlacing UV；Progressive signal memory block includes Y-signal memory block, line by line UV signal line by line
Memory block.
It will be sequentially stored in interlacing Y-signal memory block per the even number line of the Y-signal of the TTL signal after synchronizing all the way, until
The Y-signal of all even number lines is stored and is finished；The odd-numbered line of Y-signal is stored in interlacing Y-signal memory block, until all odd numbers
Capable Y-signal is stored and is finished；Interlacing UV signal will be sequentially stored in per the even number line of the UV signal of the TTL signal after synchronizing all the way
In memory block, until the UV signal of all even number lines is stored and is finished；The odd-numbered line of UV signal is sequentially stored in interlacing Y-signal to deposit
In storage area, until the UV signal of all even number lines is stored and is finished；
The even number line Y-signal of interlacing Y-signal memory block and odd-numbered line Y-signal are read, and are stored in Y-signal memory block line by line,
When storage, even number line Y-signal is sequentially stored in the even address of Y-signal memory block line by line, and odd-numbered line Y-signal is sequentially stored in line by line
In the odd address of Y-signal memory block；The even number line UV signal of the signal storage interlacing UV and odd-numbered line UV signal are read, and
Deposit is line by line in the signal storage UV, and when storage, even number line UV signal is sequentially stored in the even address of the signal storage UV line by line
In, odd-numbered line UV signal is sequentially stored in the odd address of the signal storage UV line by line；Y-signal and UV signal are all stored in line by line
Behind Y-signal memory block and the line by line signal storage UV, the conversion of interlace signal to progressive signal is completed；
After the completion of de interlacing processing, judges whether to need to carry out motion compensation to vision signal: first determining whether out that vision signal is
It is no then to continue to judge slow motion video or rapid movement video signal if motion video for motion video,
When for microinching vision signal or rapid movement video signal, the time domain noise reduction factor is introduced in video signals, thus into
The motion compensation of row vision signal；
After the completion of step 3, de interlacing processing, the first FPGA module reads TTL signal from progressive signal memory block, then converts
It exports for LVDS signal to the second FPGA module；Second FPGA module carries out high speed signal recovery to LVDS signal and is converted to low
Fast TTL signal, and synchronized according to the external synchronization clock of the internal synchronizing clock of MCU control module output or backboard transmission
It handles, is sent into TMDS high speed signal drive module after synchronization process；
Its received TTL signal is formatted as TMDS signal, and conveyed by step 4, TMDS high speed signal drive module
To backboard transmission module.
After adopting the above scheme, MCU control module is connected the first FPGA module by synchronised clock bus by the present invention, from
And synchronised clock is provided for the first FPGA module, realize the synchronization of multi-channel video signal；Meanwhile first FPGA module open every
De-interlace operation is completed to realize the conversion of interlace signal to progressive signal in row signal storage and progressive signal memory block.Energy
It enough realizes the synchronization between multiple HDMI input signals and de interlacing, guarantees the quality of rear end output video pictures.
Detailed description of the invention
Fig. 1 is system principle diagram of the invention；
Fig. 2 is flow chart of the method for the present invention；
Fig. 3 is that the video information in the first FPGA of the present invention stores schematic diagram.
Specific embodiment
As shown in Figure 1, present invention discloses a kind of synchronous de interlacing systems of HDMI high image quality comprising the balanced and mould that unstrings
Block, the first FPGA module, the second FPGA module, MCU control module, clock IC, synchronised clock bus and backboard transmission module.
Wherein, balanced and module of unstringing realizes that input terminal connects HDMI input interface, so as to defeated using IT6604 chip
High speed HDMI signal after entering remote transmission, output end then connect the first FPGA module.The equilibrium and module of unstringing for pair
High speed HDMI module carries out equilibrium treatment, and the yuv format TTL that the high speed HDMI signal after equilibrium treatment is converted to low speed is believed
Number, and the TTL signal is transmitted to the first FPGA module.
The signal input part connection equilibrium of first FPGA module and the output end for module of unstringing, input end of clock then pass through together
It walks clock bus and connects MCU control module, output end then connects the second FPGA module.First FPGA module is controlled according to MCU
The synchronised clock of module output synchronizes processing to the multichannel TTL signal of input, and the first FPGA module has opened up interlace signal
Memory block and progressive signal memory block, for storing the TTL signal of yuv format.Wherein, interlace signal memory block includes interlacing Y
Signal storage, the signal storage interlacing UV；Progressive signal memory block includes Y-signal memory block, the line by line storage of UV signal line by line
Area.
Store the Y-signal of even number line and the Y-signal of odd-numbered line in interlacing Y-signal memory block, the Y-signal of the even number line and
The Y-signal of odd-numbered line is stored in interlacing Y-signal memory block in the way of being stored separately.Interlacing UV stores idol in signal storage
Several rows of UV signal and the UV signal of odd-numbered line, the UV signal of the even number line and the UV signal of odd-numbered line are in the way of being stored separately
It is stored in the signal storage interlacing UV.The Y-signal arranged line by line is stored in Y-signal memory block line by line.UV signal stores line by line
The UV signal arranged line by line is stored in area.First FPGA module will Y-signal memory block and the line by line signal storage UV line by line
Y-signal, after UV signal is sequentially read out, be converted to LVDS signal, and be transmitted in the second FPGA module.
The signal input part of second FPGA module connects the output end of the first FPGA module, when input end of clock passes through synchronous
Clock bus connection MCU control module and backboard transmission module, output end then connect TMDS high speed signal drive module.This second
The multichannel LVDS signal that the synchronised clock that FPGA module is exported according to MCU control module receives it synchronizes processing and more pictures
Surface treatment, and LVDS signal is converted into TTL signal, it is then transmit to TDMS high speed signal drive module.
TDMS high speed signal drive module realizes that input terminal connects the second FPGA module, output using SIL9134 chip
End then connects backboard transmission module.The TDMS high speed signal drive module is used to being converted to its received TTL signal into TMDS letter
Number, and it is transmitted to backboard transmission module.
As shown in Figures 2 and 3, it is based on above system, present invention further teaches a kind of synchronous de interlacing sides of HDMI high image quality
Method, this method specifically includes the following steps:
High speed HDMI signal of at least two-way after transmitting at a distance is sent into balanced and module of unstringing by step 1, is carried out balanced
Processing and format conversion, obtain the TTL signal of the yuv format of low speed signal.
The TTL signal of the yuv format of at least two-way is sent into the first FPGA module by step 2, is synchronized processing and is gone
Interlacing processing, specific as follows:
When first FPGA module receives multichannel TTL signal, judge whether the synchronised clock for receiving MCU control module output,
If being not received by synchronised clock, the input of synchronised clock is continued waiting for.When receiving synchronised clock, the first FPGA module
Processing is synchronized to multichannel TTL signal according to synchronised clock.
After the completion of synchronization process, de interlacing processing is carried out to the TTL signal after synchronizing:
First FPGA module hews out interlace signal memory block and progressive signal memory block, wherein interlace signal memory block includes
Interlacing Y-signal memory block, the signal storage interlacing UV；Progressive signal memory block includes Y-signal memory block, line by line UV signal line by line
Memory block.
It will be stored in interlacing Y-signal memory block per the even number line of the Y-signal of the TTL signal after synchronizing all the way, i.e., by the 0th row
Y-signal be stored in the address 0 of the interlacing Y-signal memory block, the Y-signal of the 2nd row is stored in the address of the interlacing Y-signal memory block
In 1, and so on, until the Y-signal of all even number lines is stored and is finished；After the Y-signal storage of even number line, continue Y
In the odd-numbered line deposit interlacing Y-signal memory block of signal.As shown, the last one even number line of Y-signal is stored in interlacing Y-signal
In the address 1023 of memory block, then, the odd-numbered line of Y-signal is then stored since address 1024.
It will be stored in the signal storage interlacing UV per the even number line of the UV signal of the TTL signal after synchronizing all the way, i.e., by the 0th
Capable UV signal is stored in the address 0 of the signal storage interlacing UV, and the Y-signal of the 2nd row is stored in the signal storage interlacing UV
Address 1 in, and so on, until the UV signal of all even number lines is stored and is finished；After the UV signal storage of even number line,
Continue in the odd-numbered line deposit interlacing Y-signal memory block by UV signal.As shown, the last one even number line of UV signal is stored in
In the address 1023 of the signal storage interlacing UV, then, the odd-numbered line of UV signal is then stored since address 1024.
The even number line Y-signal of interlacing Y-signal memory block and odd-numbered line Y-signal are read, and are stored in Y-signal memory block line by line
In, when storage, even number line Y-signal is sequentially stored in the even address of Y-signal memory block line by line, and odd-numbered line Y-signal is sequentially stored in
Line by line in the odd address of Y-signal memory block.For example, reading the Y-signal in interlacing Y-signal memory block by sequence of addresses, first
What is read is even number line Y-signal, is stored as follows: Y[0000] it is stored in the address 0 of Y-signal memory block line by line, Y
[0002] it is stored in the address 2 of Y-signal memory block line by line, and so on, until all Y believes line by line for deposit by even number line Y-signal
Number memory block.Then what is read is odd-numbered line Y-signal, is stored as follows: Y[0001] Y-signal stores line by line for deposit
In the address 1 in area, Y[0003] it is stored in the address 3 of Y-signal memory block line by line, and so on, until odd-numbered line Y-signal is complete
Portion is stored in Y-signal memory block line by line, that is, completes the storage of Y-signal line by line.
The even number line UV signal of the signal storage interlacing UV and odd-numbered line UV signal are read, and is stored in UV signal line by line and deposits
In storage area, when storage, even number line UV signal is sequentially stored in the even address of the signal storage UV line by line, and odd-numbered line UV signal is pressed
Sequence deposit is line by line in the odd address of the signal storage UV.For example, reading the UV in the signal storage interlacing UV by sequence of addresses
Signal, what is first read out is even number line UV signal, is stored as follows: UV[0000] it is stored in the signal storage UV line by line
Address 0 in, UV[0002] deposit is line by line in the address 2 of the signal storage UV, and so on, until even number line UV signal is complete
Portion is stored in the signal storage UV line by line.Then what is read is odd-numbered line UV signal, is stored as follows: UV[0001] it deposits
Enter in the address 1 of the signal storage UV line by line, UV[0003] it is stored in the address 3 of the signal storage UV line by line, and so on, directly
It is all stored in the signal storage UV line by line to by odd-numbered line UV signal, that is, completes the storage of UV signal line by line.
The whole deposit Y-signal memory block and line by line behind the signal storage UV line by line of Y-signal and UV signal, that is, complete interlacing
Conversion of the signal to progressive signal.
Deinterlacing is not only only completed the problem of simple interlace signal turns progressive signal, for picture and static letter
Number, interlace signal, which is switched to progressive signal, can not tell difference, and for the image of movement, if will will affect without compensation
The image quality of rear end video output.For this purpose, invention introduces the time domain noise reduction factor, to solve the problems, such as motion compensation, tool
Body is as follows:
First determine whether out whether vision signal is motion video, if motion video, then continues to judge to move view slowly
Frequency signal or rapid movement video signal, when for microinching vision signal or rapid movement video signal, in vision signal
The middle introducing time domain noise reduction factor, to carry out the motion compensation of vision signal.
After the completion of step 3, de interlacing processing, the first FPGA module reads TTL signal from progressive signal memory block, then
LVDS signal is converted to export to the second FPGA module.Second FPGA module carries out high speed signal recovery to LVDS signal and converts
External synchronization clock for low speed TTL signal, and the internal synchronizing clock or backboard transmission exported according to MCU control module carries out
Synchronization process is sent into TMDS high speed signal drive module after synchronization process.
Step 4, TMDS high speed signal drive module format its received TTL signal for TMDS signal, and
It is delivered to backboard transmission module.
It is of the invention it is critical that MCU control module is connected the first FPGA module by synchronised clock bus by the present invention,
To provide synchronised clock for the first FPGA module, the synchronization of multi-channel video signal is realized；Meanwhile first FPGA module open
De-interlace operation is completed to realize the conversion of interlace signal to progressive signal in interlace signal memory block and progressive signal memory block.
It can be realized the synchronization between multiple HDMI input signals and de interlacing, guarantee the quality of rear end output video pictures.In addition,
The present invention connects the second FPGA module with background transmission module by MCU control module, to provide for the second FPGA module interior
Portion's synchronised clock and external synchronization clock further ensure the synchronization between multi-channel video signal or multi-channel video signal
It is synchronous between external signal, it ensure that the image quality of multi-picture splicing.
The above is only the embodiment of the present invention, is not intended to limit the scope of the present invention, therefore all
Any subtle modifications, equivalent variations and modifications to the above embodiments according to the technical essence of the invention still fall within this
In the range of inventive technique scheme.
Claims (4)
1. a kind of synchronous de interlacing system of HDMI high image quality, it is characterised in that: including equilibrium and module of unstringing, the first FPGA mould
Block, the second FPGA module, MCU control module, clock IC, synchronised clock bus and backboard transmission module,
Described balanced and module of unstringing realizes that input terminal connects HDMI input interface using IT6604 chip, and output end then connects
The signal input part of the first FPGA module is connect, the input end of clock of first FPGA module then passes through synchronised clock bus and connects
MCU control module, output end then connect the signal input part of the second FPGA module；The input end of clock of second FPGA module
MCU control module and backboard transmission module are connected by synchronised clock bus, output end then connects the driving of TMDS high speed signal
Module；The TDMS high speed signal drive module realizes that input terminal connects the second FPGA module, defeated using SIL9134 chip
Outlet then connects backboard transmission module；
First FPGA module has opened up interlace signal memory block and progressive signal memory block, the interlace signal memory block packet
Include interlacing Y-signal memory block, the signal storage interlacing UV；Progressive signal memory block include line by line Y-signal memory block, line by line UV believe
Number memory block；
Interlacing Y-signal memory block is used to store the Y-signal of even number line and the Y-signal of odd-numbered line, the Y-signal and odd number of the even number line
Capable Y-signal is stored in interlacing Y-signal memory block in the way of being stored separately；The interlacing UV stores idol in signal storage
Several rows of UV signal and the UV signal of odd-numbered line, the UV signal of the even number line and the UV signal of odd-numbered line are in the way of being stored separately
It is stored in the signal storage interlacing UV；The Y-signal arranged line by line is stored in the memory block of Y-signal line by line；The UV line by line
The UV signal arranged line by line is stored in signal storage.
2. a kind of HDMI high image quality according to claim 1 synchronizes de interlacing system, it is characterised in that: described balanced and solution
Module of going here and there is realized using IT6604 chip.
3. a kind of HDMI high image quality according to claim 1 synchronizes de interlacing system, it is characterised in that: the TDMS high speed
Signal driver module is realized using SIL9134 chip.
4. a kind of synchronous interlace-removing method of HDMI high image quality, it is characterised in that: the method uses as described in claim 1 one
The synchronous de interlacing system of kind HDMI high image quality, specifically includes the following steps:
High speed HDMI signal of at least two-way after transmitting at a distance is sent into balanced and module of unstringing by step 1, is carried out balanced
Processing and format conversion, obtain the TTL signal of the yuv format of low speed signal；
The TTL signal of the yuv format of at least two-way is sent into the first FPGA module by step 2, synchronizes processing and de interlacing
Processing, specific as follows:
When first FPGA module receives multichannel TTL signal, judge whether the synchronised clock for receiving MCU control module output,
If being not received by synchronised clock, the input of synchronised clock is continued waiting for；When receiving synchronised clock, the first FPGA module
Processing is synchronized to multichannel TTL signal according to synchronised clock；
After the completion of synchronization process, de interlacing processing is carried out to the TTL signal after synchronizing:
First FPGA module hews out interlace signal memory block and progressive signal memory block, wherein interlace signal memory block includes
Interlacing Y-signal memory block, the signal storage interlacing UV；Progressive signal memory block includes Y-signal memory block, line by line UV signal line by line
Memory block；
It will be sequentially stored in interlacing Y-signal memory block per the even number line of the Y-signal of the TTL signal after synchronizing all the way, until all
The Y-signal of even number line is stored and is finished；The odd-numbered line of Y-signal is stored in interlacing Y-signal memory block, until all odd-numbered lines
Y-signal is stored and is finished；The storage of interlacing UV signal will be sequentially stored in per the even number line of the UV signal of the TTL signal after synchronizing all the way
Qu Zhong, until the UV signal of all even number lines is stored and finished；The odd-numbered line of UV signal is sequentially stored in interlacing Y-signal memory block
In, until the UV signal of all even number lines is stored and is finished；
The even number line Y-signal of interlacing Y-signal memory block and odd-numbered line Y-signal are read, and are stored in Y-signal memory block line by line,
When storage, even number line Y-signal is sequentially stored in the even address of Y-signal memory block line by line, and odd-numbered line Y-signal is sequentially stored in line by line
In the odd address of Y-signal memory block；The even number line UV signal of the signal storage interlacing UV and odd-numbered line UV signal are read, and
Deposit is line by line in the signal storage UV, and when storage, even number line UV signal is sequentially stored in the even address of the signal storage UV line by line
In, odd-numbered line UV signal is sequentially stored in the odd address of the signal storage UV line by line；Y-signal and UV signal are all stored in line by line
Behind Y-signal memory block and the line by line signal storage UV, the conversion of interlace signal to progressive signal is completed；
After the completion of de interlacing processing, judges whether to need to carry out motion compensation to vision signal: first determining whether out that vision signal is
It is no then to continue to judge slow motion video or rapid movement video signal if motion video for motion video,
When for microinching vision signal or rapid movement video signal, the time domain noise reduction factor is introduced in video signals, thus into
The motion compensation of row vision signal；
After the completion of step 3, de interlacing processing, the first FPGA module reads TTL signal from progressive signal memory block, then converts
It exports for LVDS signal to the second FPGA module；Second FPGA module carries out high speed signal recovery to LVDS signal and is converted to low
Fast TTL signal, and synchronized according to the external synchronization clock of the internal synchronizing clock of MCU control module output or backboard transmission
It handles, is sent into TMDS high speed signal drive module after synchronization process；
Its received TTL signal is formatted as TMDS signal, and conveyed by step 4, TMDS high speed signal drive module
To backboard transmission module.
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| CN203243440U (en) * | 2013-03-08 | 2013-10-16 | 珠海英图电子科技有限公司 | Video signal conversion apparatus for converting HDMI to VGA |
| CN103745683A (en) * | 2013-09-27 | 2014-04-23 | 中傲智能科技（苏州）有限公司 | LED display screen control system based on HDMI interface |
| CN209120335U (en) * | 2018-12-10 | 2019-07-16 | 厦门视诚科技有限公司 | A kind of HDMI high image quality synchronization de interlacing system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102142236A (en) * | 2010-02-03 | 2011-08-03 | 胡志强 | Liquid crystal display driver for high-resolution interlacing scanned video signals |
| CN203243440U (en) * | 2013-03-08 | 2013-10-16 | 珠海英图电子科技有限公司 | Video signal conversion apparatus for converting HDMI to VGA |
| CN103745683A (en) * | 2013-09-27 | 2014-04-23 | 中傲智能科技（苏州）有限公司 | LED display screen control system based on HDMI interface |
| CN209120335U (en) * | 2018-12-10 | 2019-07-16 | 厦门视诚科技有限公司 | A kind of HDMI high image quality synchronization de interlacing system |
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