CN109413356B - HDMI high-image-quality synchronous de-interlacing system and method - Google Patents
HDMI high-image-quality synchronous de-interlacing system and method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
- H04N7/012—Conversion between an interlaced and a progressive signal
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- H04N5/00—Details of television systems
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- H04N5/00—Details of television systems
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Abstract
The invention relates to an HDMI high-quality synchronous de-interlacing system and a method, wherein an MCU control module is connected with a first FPGA module through a synchronous clock bus, so that a synchronous clock is provided for the first FPGA module, and the synchronization of multiple paths of video signals is realized; meanwhile, the first FPGA module opens up an interlaced signal storage area and a progressive signal storage area to realize conversion from interlaced signals to progressive signals and finish de-interlacing operation. Synchronization and de-interlacing among a plurality of HDMI input signals can be realized, and the quality of a video picture output by the rear end is ensured.
Description
Technical Field
The invention relates to the technical field of video processors, in particular to an HDMI high-image-quality synchronous de-interlacing system and method.
Background
The video processor is a video data processing apparatus having a function of supporting various input signals such as VGA, composite video, SDI signal, and digital HDMI. Seven companies of Hitachi, ping Po, philips, silicon Image, sony, thomson and Toshiba in 2002 establish HDMI organization, and promulgate HDMI standard of high-definition digital multimedia interface. The HDMI protocol realizes simultaneous transmission of audio and video through time division control of video signals, audio signals and control signals. The signal transmission process of HDMI includes 3 periods: video data transmission period, island data transmission period and control data transmission period, in island data transmission period, audio data and auxiliary data (information frame and field line synchronizing signals) appear on HDMI data line, and the synchronizing signals can well realize single-channel HDMI audio-video synchronization. However, the input interfaces of the conventional HDMI input module have no uniform synchronization timing sequence, which results in that the HDMI signals have no uniform synchronization information, and the HDMI input signals cannot be synchronized, which results in that the picture and video spliced by the video processor are not synchronized, and the customer experience is affected.
In addition, the conventional HDMI system has no de-interlacing function, which is a method of converting an interlaced (interlace) video signal into a progressive (progressive) progressive video signal. The current new display devices all use progressive scanning, and the direct playing of interlaced images on the progressive scanning device generates serious flicker phenomenon, and because the interlaced signals have images in two lines and the other line is completely black, the brightness is reduced by half compared with the progressive signals.
In view of the above, the present inventors have made an in-depth conception for many problems of the HDMI system, and have further proposed the present invention.
Disclosure of Invention
The invention aims to provide an HDMI high-quality synchronous de-interlacing system and method, which can realize synchronization and de-interlacing among a plurality of HDMI input signals and ensure the quality of a rear-end output video picture.
In order to achieve the above purpose, the invention adopts the following technical scheme:
an HDMI high-quality synchronous de-interlacing system comprises an equalization and de-serialization module, a first FPGA module, a second FPGA module, an MCU control module, a clock IC, a synchronous clock bus and a backboard transmission module,
the equalization and deserialization module is realized by an IT6604 chip, the input end of the equalization and deserialization module is connected with an HDMI input interface, the output end of the equalization and deserialization module is connected with the signal input end of the first FPGA module, the clock input end of the first FPGA module is connected with the MCU control module through the synchronous clock bus, and the output end of the equalization and deserialization module is connected with the signal input end of the second FPGA module; the clock input end of the second FPGA module is connected with the MCU control module and the backboard transmission module through the synchronous clock bus, and the output end of the second FPGA module is connected with the TMDS high-speed signal driving module; the TDMS high-speed signal driving module is realized by adopting an SIL9134 chip, the input end of the TDMS high-speed signal driving module is connected with the second FPGA module, and the output end of the TDMS high-speed signal driving module is connected with the backboard transmission module;
the first FPGA module opens up an interlaced signal storage area and a progressive signal storage area, and the interlaced signal storage area comprises an interlaced Y signal storage area and an interlaced UV signal storage area; the progressive signal storage area comprises a progressive Y signal storage area and a progressive UV signal storage area;
the interlaced Y signal storage area is used for storing Y signals of even lines and Y signals of odd lines, and the Y signals of the even lines and the Y signals of the odd lines are stored in the interlaced Y signal storage area in a separated storage mode; the UV signals of even lines and the UV signals of odd lines are stored in the interlaced UV signal storage area, and the UV signals of the even lines and the UV signals of the odd lines are stored in the interlaced UV signal storage area in a separated storage mode; y signals arranged row by row are stored in the row by row Y signal storage area; the row-by-row UV signal storage area stores UV signals arranged row by row.
The equalization and deserialization module is realized by an IT6604 chip.
And the TDMS high-speed signal driving module is realized by adopting an SIL9134 chip.
An HDMI high-quality synchronous de-interlacing method adopts the HDMI high-quality synchronous de-interlacing system, which specifically comprises the following steps:
step 1, sending at least two paths of high-speed HDMI signals subjected to remote transmission into an equalization and deserialization module, performing equalization processing and format conversion, and obtaining a TTL signal in a YUV format of a low-speed signal;
step 2, sending TTL signals in YUV format of at least two paths into a first FPGA module for synchronous processing and de-interlacing processing, specifically as follows:
when the first FPGA module receives the multipath TTL signals, judging whether the synchronous clock output by the MCU control module is received or not, and if the synchronous clock is not received, continuing to wait for the input of the synchronous clock; when receiving the synchronous clock, the first FPGA module carries out synchronous processing on the multipath TTL signals according to the synchronous clock;
after the synchronization process is completed, de-interlacing is performed on the synchronized TTL signals:
the first FPGA module opens up an interlaced signal storage area and a progressive signal storage area, wherein the interlaced signal storage area comprises an interlaced Y signal storage area and an interlaced UV signal storage area; the progressive signal storage area includes a progressive Y signal storage area and a progressive UV signal storage area.
Storing even lines of Y signals of each path of synchronized TTL signals into an interlaced Y signal storage area in sequence until Y signals of all even lines are stored; storing odd lines of the Y signals into an interlaced Y signal storage area until all the Y signals of the odd lines are stored; the even lines of the UV signals of each path of synchronized TTL signals are sequentially stored in an interlaced UV signal storage area until the UV signals of all the even lines are stored; sequentially storing odd lines of the UV signals into an interlaced Y signal storage area until all the UV signals of even lines are stored;
reading out even-line Y signals and odd-line Y signals of an interlaced Y signal storage area, storing the even-line Y signals into a progressive Y signal storage area, and sequentially storing the even-line Y signals into even addresses of the progressive Y signal storage area and the odd-line Y signals into odd addresses of the progressive Y signal storage area during storage; reading out even-line UV signals and odd-line UV signals of the interlaced UV signal storage area, storing the even-line UV signals and the odd-line UV signals into the progressive UV signal storage area, and sequentially storing the even-line UV signals into even addresses of the progressive UV signal storage area and the odd-line UV signals into odd addresses of the progressive UV signal storage area during storage; after the Y signals and the UV signals are all stored in the progressive Y signal storage area and the progressive UV signal storage area, the conversion from the interlaced signals to the progressive signals is completed;
after the de-interlacing process is completed, judging whether motion compensation is needed to be performed on the video signal: firstly judging whether a video signal is a motion video signal, if so, continuing to judge a slow motion video signal or a fast motion video signal, and introducing a time domain noise reduction factor into the video signal when the video signal is a slow motion video signal or a fast motion video signal so as to perform motion compensation of the video signal;
step 3, after de-interlacing processing is completed, the first FPGA module reads TTL signals from the progressive signal storage area, and then converts the TTL signals into LVDS signals to be output to the second FPGA module; the second FPGA module recovers the high-speed signal of the LVDS signal and converts the high-speed signal into a low-speed TTL signal, performs synchronous processing according to an internal synchronous clock output by the MCU control module or an external synchronous clock transmitted by the backboard, and sends the synchronous processing into the TMDS high-speed signal driving module;
and 4, the TMDS high-speed signal driving module performs format conversion on the TTL signals received by the TMDS high-speed signal driving module into TMDS signals and transmits the TMDS signals to the backboard transmission module.
After the scheme is adopted, the MCU control module is connected with the first FPGA module through the synchronous clock bus, so that a synchronous clock is provided for the first FPGA module, and the synchronization of multiple paths of video signals is realized; meanwhile, the first FPGA module opens up an interlaced signal storage area and a progressive signal storage area to realize conversion from interlaced signals to progressive signals and finish de-interlacing operation. Synchronization and de-interlacing among a plurality of HDMI input signals can be realized, and the quality of a video picture output by the rear end is ensured.
Drawings
FIG. 1 is a schematic block diagram of a system of the present invention;
FIG. 2 is a flow chart of the method of the present invention;
fig. 3 is a schematic diagram of video information storage in the first FPGA of the present invention.
Detailed Description
As shown in fig. 1, the invention discloses an HDMI high-quality synchronous de-interlacing system, which includes an equalization and de-serialization module, a first FPGA module, a second FPGA module, an MCU control module, a clock IC, a synchronous clock bus, and a backplane transmission module.
The equalization and deserializing module is realized by an IT6604 chip, the input end of the equalization and deserializing module is connected with an HDMI input interface so as to input a high-speed HDMI signal after long-distance transmission, and the output end of the equalization and deserializing module is connected with the first FPGA module. The equalization and deserialization module is used for performing equalization processing on the high-speed HDMI module, converting the high-speed HDMI signal after the equalization processing into a low-speed YUV format TTL signal, and transmitting the TTL signal to the first FPGA module.
The signal input end of the first FPGA module is connected with the output end of the equalization and deserialization module, the clock input end is connected with the MCU control module through the synchronous clock bus, and the output end is connected with the second FPGA module. The first FPGA module performs synchronous processing on the input multipath TTL signals according to the synchronous clock output by the MCU control module, and opens up an interlaced signal storage area and a progressive signal storage area for storing the TTL signals in YUV format. The interlaced signal storage area comprises an interlaced Y signal storage area and an interlaced UV signal storage area; the progressive signal storage area includes a progressive Y signal storage area and a progressive UV signal storage area.
The interlaced Y signal memory area stores Y signals of even lines and Y signals of odd lines, which are stored in the interlaced Y signal memory area in a separate storage manner. The interlaced UV signal storage area stores UV signals of even lines and UV signals of odd lines, and the UV signals of the even lines and the UV signals of the odd lines are stored in the interlaced UV signal storage area in a separated storage mode. The Y signals arranged row by row are stored in the Y signal storage area row by row. The row-by-row UV signal storage area stores UV signals arranged row by row. The first FPGA module reads Y signals and UV signals of the progressive Y signal storage area and the progressive UV signal storage area in sequence, converts the Y signals and the UV signals into LVDS signals and transmits the LVDS signals to the second FPGA module.
The signal input end of the second FPGA module is connected with the output end of the first FPGA module, the clock input end is connected with the MCU control module and the backboard transmission module through the synchronous clock bus, and the output end is connected with the TMDS high-speed signal driving module. The second FPGA module performs synchronous processing and multi-picture processing on the received multi-channel LVDS signals according to the synchronous clock output by the MCU control module, converts the LVDS signals into TTL signals and then transmits the TTL signals to the TDMS high-speed signal driving module.
The TDMS high-speed signal driving module is realized by adopting an SIL9134 chip, the input end of the TDMS high-speed signal driving module is connected with the second FPGA module, and the output end of the TDMS high-speed signal driving module is connected with the backboard transmission module. The TDMS high-speed signal driving module is used for converting the received TTL signals into TMDS signals and transmitting the TMDS signals to the backboard transmission module.
Based on the above system, as shown in fig. 2 and fig. 3, the invention also discloses an HDMI high-quality synchronous de-interlacing method, which specifically comprises the following steps:
and step 1, sending at least two paths of high-speed HDMI signals subjected to remote transmission into an equalization and deserialization module, and performing equalization processing and format conversion to obtain a TTL signal in a YUV format of a low-speed signal.
Step 2, sending TTL signals in YUV format of at least two paths into a first FPGA module for synchronous processing and de-interlacing processing, specifically as follows:
when the first FPGA module receives the multipath TTL signals, judging whether the synchronous clock output by the MCU control module is received or not, and if the synchronous clock is not received, continuing to wait for the input of the synchronous clock. When the synchronous clock is received, the first FPGA module carries out synchronous processing on the multipath TTL signals according to the synchronous clock.
After the synchronization process is completed, de-interlacing is performed on the synchronized TTL signals:
the first FPGA module opens up an interlaced signal storage area and a progressive signal storage area, wherein the interlaced signal storage area comprises an interlaced Y signal storage area and an interlaced UV signal storage area; the progressive signal storage area includes a progressive Y signal storage area and a progressive UV signal storage area.
Storing even lines of Y signals of each path of synchronized TTL signals into an interlaced Y signal storage area, namely storing Y signals of a 0 th line into an address 0 of the interlaced Y signal storage area, storing Y signals of a 2 nd line into an address 1 of the interlaced Y signal storage area, and the like until Y signals of all even lines are stored; after the Y signals of the even lines are stored, the odd lines of the Y signals are stored in an interlaced Y signal storage area. As shown, the last even row of the Y signal is stored in address 1023 of the interlaced Y signal memory area, and then the odd row of the Y signal is stored starting at address 1024.
Storing even lines of UV signals of each path of synchronized TTL signals into an interlaced UV signal storage area, namely storing UV signals of the 0 th line into an address 0 of the interlaced UV signal storage area, storing Y signals of the 2 nd line into an address 1 of the interlaced UV signal storage area, and the like until all UV signals of the even lines are stored; after the UV signals of even lines are stored, the odd lines of the UV signals are stored in the interlaced Y signal storage area continuously. As shown, the last even row of UV signals is stored in address 1023 of the interlaced UV signal memory area, then the odd row of UV signals is stored beginning at address 1024.
And reading out the even-line Y signals and the odd-line Y signals of the interlaced Y signal storage area, storing the even-line Y signals into the even-line Y signal storage area in sequence, and storing the odd-line Y signals into the odd-line Y signal storage area in sequence when storing the even-line Y signals. For example, the Y signals in the interlaced Y signal memory area are read out in the address order, and the even-line Y signals are read out first, and are stored as follows: y [ 0000 ] is stored in address 0 of the progressive Y signal memory area, Y [ 0002 ] is stored in address 2 of the progressive Y signal memory area, and so on until the even-numbered Y signals are all stored in the progressive Y signal memory area. Then, the odd-numbered row Y signal is read out and stored as follows: y [ 0001 ] is stored in the address 1 of the progressive Y signal storage area, Y [ 0003 ] is stored in the address 3 of the progressive Y signal storage area, and the like until all the odd-numbered Y signals are stored in the progressive Y signal storage area, namely the storage of the progressive Y signals is completed.
And reading out the even-line UV signals and the odd-line UV signals of the interlaced UV signal storage area, storing the even-line UV signals and the odd-line UV signals into the progressive UV signal storage area, and sequentially storing the even-line UV signals into even addresses of the progressive UV signal storage area and the odd-line UV signals into odd addresses of the progressive UV signal storage area during storage. For example, the UV signals in the interlaced UV signal storage area are read out in address order, and the even-numbered row UV signals are read out first, and stored as follows: UV [ 0000 ] is stored in address 0 of the progressive UV signal memory area, UV [ 0002 ] is stored in address 2 of the progressive UV signal memory area, and so on until the even-numbered UV signals are all stored in the progressive UV signal memory area. Then the odd row UV signals are read out and stored as follows: UV [ 0001 ] is stored in the address 1 of the progressive UV signal storage area, UV [ 0003 ] is stored in the address 3 of the progressive UV signal storage area, and the like until all odd-numbered UV signals are stored in the progressive UV signal storage area, namely the storage of the progressive UV signals is completed.
After the Y signals and the UV signals are all stored in the progressive Y signal storage area and the progressive UV signal storage area, the conversion from the interlaced signals to the progressive signals is completed.
The de-interlacing not only completes the problem of converting a simple interlaced signal into a progressive signal, but also can not distinguish the difference between the picture and a still signal by converting the interlaced signal into the progressive signal, and the picture quality of the rear-end video output can be affected if the compensation is not performed for a moving image. Therefore, the invention introduces a time domain noise reduction factor to solve the problem of motion compensation, and specifically comprises the following steps:
firstly judging whether the video signal is a motion video signal, if so, continuing to judge the slow motion video signal or the fast motion video signal, and introducing a time domain noise reduction factor into the video signal when the video signal is the slow motion video signal or the fast motion video signal, thereby performing motion compensation of the video signal.
And 3, after de-interlacing processing is completed, the first FPGA module reads TTL signals from the progressive signal storage area, and then converts the TTL signals into LVDS signals to be output to the second FPGA module. The second FPGA module recovers the high-speed signal of the LVDS signal and converts the LVDS signal into a low-speed TTL signal, performs synchronous processing according to an internal synchronous clock output by the MCU control module or an external synchronous clock transmitted by the backboard, and sends the synchronous processing into the TMDS high-speed signal driving module.
And 4, the TMDS high-speed signal driving module performs format conversion on the TTL signals received by the TMDS high-speed signal driving module into TMDS signals and transmits the TMDS signals to the backboard transmission module.
The MCU control module is connected with the first FPGA module through the synchronous clock bus, so that a synchronous clock is provided for the first FPGA module, and the synchronization of multiple paths of video signals is realized; meanwhile, the first FPGA module opens up an interlaced signal storage area and a progressive signal storage area to realize conversion from interlaced signals to progressive signals and finish de-interlacing operation. Synchronization and de-interlacing among a plurality of HDMI input signals can be realized, and the quality of a video picture output by the rear end is ensured. In addition, the MCU control module and the background transmission module are connected with the second FPGA module, so that an internal synchronous clock and an external synchronous clock are provided for the second FPGA module, the synchronization between multiple paths of video signals or the synchronization between the multiple paths of video signals and the external signal is further ensured, and the picture quality of multi-picture splicing is ensured.
The foregoing embodiments of the present invention are not intended to limit the technical scope of the present invention, and therefore, any minor modifications, equivalent variations and modifications made to the above embodiments according to the technical principles of the present invention still fall within the scope of the technical proposal of the present invention.
Claims (1)
1. An HDMI high-quality synchronous de-interlacing method is characterized in that: the method adopts an HDMI high-quality synchronous de-interlacing system, the system comprises an equalization and de-serialization module, a first FPGA module, a second FPGA module, an MCU control module, a clock IC, a synchronous clock bus and a backboard transmission module,
the equalization and deserialization module is realized by an IT6604 chip, the input end of the equalization and deserialization module is connected with an HDMI input interface, the output end of the equalization and deserialization module is connected with the signal input end of the first FPGA module, the clock input end of the first FPGA module is connected with the MCU control module through the synchronous clock bus, and the output end of the equalization and deserialization module is connected with the signal input end of the second FPGA module; the clock input end of the second FPGA module is connected with the MCU control module and the backboard transmission module through the synchronous clock bus, and the output end of the second FPGA module is connected with the TMDS high-speed signal driving module; the TMDS high-speed signal driving module is realized by adopting an SIL9134 chip, the input end of the TMDS high-speed signal driving module is connected with the second FPGA module, and the output end of the TMDS high-speed signal driving module is connected with the backboard transmission module;
the first FPGA module opens up an interlaced signal storage area and a progressive signal storage area, and the interlaced signal storage area comprises an interlaced Y signal storage area and an interlaced UV signal storage area; the progressive signal storage area comprises a progressive Y signal storage area and a progressive UV signal storage area;
the interlaced Y signal storage area is used for storing Y signals of even lines and Y signals of odd lines, and the Y signals of the even lines and the Y signals of the odd lines are stored in the interlaced Y signal storage area in a separated storage mode; the UV signals of even lines and the UV signals of odd lines are stored in the interlaced UV signal storage area, and the UV signals of the even lines and the UV signals of the odd lines are stored in the interlaced UV signal storage area in a separated storage mode; y signals arranged row by row are stored in the row by row Y signal storage area; the progressive UV signal storage area stores progressive UV signals;
the method specifically comprises the following steps:
step 1, sending at least two paths of high-speed HDMI signals subjected to remote transmission into an equalization and deserialization module, performing equalization processing and format conversion, and obtaining a TTL signal in a YUV format of a low-speed signal;
step 2, sending TTL signals in YUV format of at least two paths into a first FPGA module for synchronous processing and de-interlacing processing, specifically as follows:
when the first FPGA module receives the multipath TTL signals, judging whether the synchronous clock output by the MCU control module is received or not, and if the synchronous clock is not received, continuing to wait for the input of the synchronous clock; when receiving the synchronous clock, the first FPGA module carries out synchronous processing on the multipath TTL signals according to the synchronous clock;
after the synchronization process is completed, de-interlacing is performed on the synchronized TTL signals:
the first FPGA module opens up an interlaced signal storage area and a progressive signal storage area, wherein the interlaced signal storage area comprises an interlaced Y signal storage area and an interlaced UV signal storage area; the progressive signal storage area comprises a progressive Y signal storage area and a progressive UV signal storage area;
storing even lines of Y signals of each path of synchronized TTL signals into an interlaced Y signal storage area in sequence until Y signals of all even lines are stored; storing odd lines of the Y signals into an interlaced Y signal storage area until all the Y signals of the odd lines are stored; the even lines of the UV signals of each path of synchronized TTL signals are sequentially stored in an interlaced UV signal storage area until the UV signals of all the even lines are stored; sequentially storing odd lines of the UV signals into an interlaced Y signal storage area until all the UV signals of even lines are stored;
reading out even-line Y signals and odd-line Y signals of an interlaced Y signal storage area, storing the even-line Y signals into a progressive Y signal storage area, and sequentially storing the even-line Y signals into even addresses of the progressive Y signal storage area and the odd-line Y signals into odd addresses of the progressive Y signal storage area during storage; reading out even-line UV signals and odd-line UV signals of the interlaced UV signal storage area, storing the even-line UV signals and the odd-line UV signals into the progressive UV signal storage area, and sequentially storing the even-line UV signals into even addresses of the progressive UV signal storage area and the odd-line UV signals into odd addresses of the progressive UV signal storage area during storage; after the Y signals and the UV signals are all stored in the progressive Y signal storage area and the progressive UV signal storage area, the conversion from the interlaced signals to the progressive signals is completed;
after the de-interlacing process is completed, judging whether motion compensation is needed to be performed on the video signal: firstly judging whether a video signal is a motion video signal, if so, continuing to judge a slow motion video signal or a fast motion video signal, and introducing a time domain noise reduction factor into the video signal when the video signal is a slow motion video signal or a fast motion video signal so as to perform motion compensation of the video signal;
step 3, after de-interlacing processing is completed, the first FPGA module reads TTL signals from the progressive signal storage area, and then converts the TTL signals into LVDS signals to be output to the second FPGA module; the second FPGA module recovers the high-speed signal of the LVDS signal and converts the high-speed signal into a low-speed TTL signal, performs synchronous processing according to an internal synchronous clock output by the MCU control module or an external synchronous clock transmitted by the backboard, and sends the synchronous processing into the TMDS high-speed signal driving module;
and 4, the TMDS high-speed signal driving module performs format conversion on the TTL signals received by the TMDS high-speed signal driving module into TMDS signals and transmits the TMDS signals to the backboard transmission module.
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| CN109413356A (en) | 2019-03-01 |
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