CN109065539B - 一种bcd半导体器件及其制造方法 - Google Patents

一种bcd半导体器件及其制造方法 Download PDF

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CN109065539B
CN109065539B CN201810958772.4A CN201810958772A CN109065539B CN 109065539 B CN109065539 B CN 109065539B CN 201810958772 A CN201810958772 A CN 201810958772A CN 109065539 B CN109065539 B CN 109065539B
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voltage
region
conduction type
conductive type
layer
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CN109065539A (zh
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乔明
赖春兰
何林蓉
叶力
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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Abstract

本发明提供一种BCD半导体器件及其制造方法，包括集成于同一芯片上的第一高压nLIGBT器件、第二高压nLIGBT器件、第一高压nLDMOS器件、第二高压nLDMOS器件、第三高压nLDMOS器件、第一高压pLDMOS器件、低压NMOS器件、低压PMOS器件、PNP器件和diode器件，高压nLIGBT器件、高压nLDMOS器件、高压pLDMOS器件均采用介质隔离，实现高低压器件完全隔离，本发明在衬底上实现nLIGBT、nLDMOS、低压NMOS、低压PMOS和低压NPN的单片集成，由介质、第二导电类型埋层、介质槽以及第一导电类型注入区组成的隔离区域实现集成芯片上的高低压全介质隔离，避免了高低压的串扰问题，在六类的高压管子中均采用了多沟道设计，可有效增加高压管的电流输出能力。

Description

一种BCD半导体器件及其制造方法
技术领域
本发明属于半导体功率器件技术领域，涉及一种BCD(Bipolar CMOS DMOS)器件及其制造方法。
背景技术
高压功率集成电路常利用Bipolar晶体管的高模拟精度、CMOS的高集成度以及DMOS(Double-diffused MOSFET)的高功率或电压特性，将Bipolar模拟电路、CMOS逻辑电路、CMOS模拟电路和DMOS高压功率器件单片集成在一起(简称BCD工艺)。横向高压器件由于漏极、栅极、源极都在芯片表面，易于通过内部连接与低压信号电路集成，被广泛应用于高压功率集成电路中。在一般的功率集成芯片中，会采用高压LDMOS器件(Lateral Double-diffused MOSFET)作为输出级，但在简单的一维分析下，DMOS器件的比导通电阻(Specificon-resistance,Ron,sp)与器件击穿电压(Breakdown Voltage,BV)存在Ron,sp∝BV2.3～2.6的关系，使得器件在高压应用时，导通电阻急剧上升，这就限制了横向高压DMOS器件在高压功率集成电路中的应用，尤其是在要求低导通损耗和小芯片面积的电路中。为了克服高导通电阻的问题，J.A.APPLES等人提出了RESURF(Reduced SURface Field)降低表面场技术，被广泛应用于高压器件的设计中。除此之外，还有人提出了如Double-RESURF、Triple-RESURFLDMOS器件以及双极型器件IGBT(Insulated-Gate Bipolar Transistor)等概念。基于RESURF耐压原理，我们已经发明了BCD半导体器件及其制造技术(专利号：ZL200810148118.3)，在单晶衬底上实现nLIGBT、nLDMOS、低压NMOS、低压PMOS和低压NPN的单片集成，得到性能优良的高压、高速、低导通损耗的功率器件，由于没有采用外延工艺，芯片具有较低的制造成本。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种BCD半导体器件及其制造方法。
为实现上述发明目的，本发明技术方案如下：
1、一种BCD半导体器件，包括集成于同一芯片上的第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6、低压NMOS器件7、低压PMOS器件8、PNP器件9和diode器件10，所述第一高压nLIGBT器件1、第二高压nLIGBT器件2和第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6均采用介质隔离，实现高低压器件完全隔离，第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5采用多沟道设计。
作为优选方式，所述的BCD半导体器件进一步为：
所述第一高压nLIGBT器件1，位于包括介质301、第二导电类型埋层205、介质槽302、填充物402以及第一导电类型注入区105的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第二导电类型外延层201中并延伸至衬底101、且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第二导电类型埋层205位于介质301上方，所述高压nLIGBT器件1还包括：位于器件两侧的多沟道发射极，多沟道发射极包括按照左元胞2(0)、第一右元胞1(1)、第一左元胞2(1)、第二右元胞1(2)、第二左元胞2(2)、……第n右元胞1(n)、第n左元胞2(n)…的顺序交替排列的多个元胞，所述高压nLIGBT器件1还包括：由第二导电类型外延层201构成的漂移区，由第二导电类型缓冲区203和与金属501直接相连的第一导电类型接触区103组成的集电极，位于第二导电类型外延层201表面的场氧化层303、金属层501以及金属前介质层305，其中，发射极的每一个元胞包括第二导电类型阱区206、位于第二导电类型阱区206中的第一导电类型区域102、与金属501直接相连且位于第一导电类型区域102中的第一导电类型接触区103、第二导电类型接触区202、位于第一导电类型区域102上表面的薄介质层304以及栅电极401；
所述第二高压nLIGBT器件2与第一高压nLIGBT器件1的差别在于：所述第二类高压nLIGBT器件2的多沟道发射极包括多个按照第一右元胞1(1)、第一左元胞2(1)、第二右元胞1(2)、第二左元胞2(2)、……第n右元胞1(n)、第n左元胞2(n)…的顺序交替排列的多个元胞；
所述第一高压nLDMOS器件3，位于包括介质301、第二导电类型埋层205、介质槽302、填充物402以及第一导电类型注入区105的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第二导电类型外延层201中并延伸至衬底101且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第二导电类型埋层205位于介质301上方，第一高压nLDMOS器件3还包括：位于器件两侧的多沟道源极，多沟道源极包括按照左元胞2(0)、第一右元胞1(1)、第一左元胞2(1)、第二右元胞1(2)、第二左元胞2(2)、……第n右元胞1(n)、第n左元胞2(n)的顺序交替排列的多个元胞，所述第一高压nLDMOS器件3还包括：第二导电类型外延层201构成的漂移区、由第二导电类型缓冲区203和与金属层501直接相连的第二导电类型接触区202组成的漏电极、位于第二导电类型外延层201表面的场氧化层303、金属层501以及金属前介质层305，其中，源极的每一个元胞包括第二导电类型阱区206、位于第二导电类型阱区206中的第一导电类型区域102、与金属层501直接相连且位于第一导电类型区域102中的第一导电类型接触区103、第二导电类型接触区202、位于第一导电类型区域102上表面的薄介质层304以及栅电极401；
所述第二高压nLDMOS器件4和第一高压nLDMOS器件3的差别在于：薄层介质层304与第二导电类型阱区206上表面之间设有第二导电类型注入区207；
所述第三高压nLDMOS器件5和第一高压nLDMOS器件3的差别在于：第二导电类型外延层201表面无场氧化层303；
所述第一高压pLDMOS器件6，位于包括介质301、第二导电类型埋层205、介质槽302、填充物402以及第一导电类型注入区105组成的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第二导电类型外延层201中并延伸至衬底101且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第二导电类型埋层205位于介质301上方，所述高压pLDMOS器件6还包括：由位于器件两侧的左元胞2(0)构成的源极、由位于第二导电类型外延层201中的第一导电类型区域102构成的漂移区、由位于第一导电类型区域102中的一个第一导电类型接触区103构成的漏极、位于第二导电类型外延层201上方场氧化层303、金属层501以及金属前介质层305，构成源极的左元胞2(0)包括第二导电类型阱区206、位于第二导电类型阱区206中且与金属层501直接相连的另一第一导电类型接触区103以及第二导电类型接触区202、位于第二导电类型阱区206区域上表面的薄介质层304以及栅电极401；
所述低压NMOS器件7设置在第一导电类型区域102中，第一导电类型区域102位于第二导电类型外延层201中，第二导电类型接触区202和一个第一导电类型接触区103作为源极，位于第一导电类型区域102的一侧且分别与金属层501相连；另一第一导电类型接触区103作为漏极，位于第一导电类型区域102的另一侧且与金属层501相连，栅电极401处于薄介质层304上、金属前介质层305下；栅电极401和金属层501通过金属前介质层305相互隔离；
所述低压PMOS器件8设置在第二导电类型阱区206中，第二导电类型阱区206位于第二导电类型外延层201中，第二导电类型接触区202和一个第一导电类型接触区103作为源极位于第一导电类型区域102的一侧且与金属层501相连；另一第一导电类型接触区103作为漏极，位于第一导电类型区域102的另一侧且与金属层501相连，栅电极401处于薄介质层304上、金属前介质层305下；金属层501和栅电极401通过金属前介质层305相互隔离；
所述PNP器件9设置在第一导电类型区域102中金属前介质层305之下，第一导电类型接触区103集电极置于第一导电类型区域102中，第一导电类型接触区103发射极与第二导电类型接触区202基极位于第二导电类型缓冲区203基区中，第二导电类型缓冲区203位于第一导电类型区域102中，其中第一导电类型接触区103集电极、第一导电类型接触区103发射极、第二导电类型接触区202基极均与金属层501相接；
所述diode器件10设置在第一导电类型区域102中金属前介质层305之下，第一导电类型接触区103阳极置于第一导电类型区域102中，第二导电类型接触区202阴极位于第一导电类型区域102中，其中第一导电类型接触区103阳极、第二导电类型接触区202阴极与金属层501相接。
作为优选方式，所述的BCD半导体器件进一步为：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5，第一高压pLDMOS器件6，其介质301上方第二导电类型埋层205换成第一导电类型耐压结构106，第一导电类型耐压结构106与介质槽302侧壁的第一导电类型注入区105相连。
作为优选方式，所述的BCD半导体器件进一步为：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5，第一高压pLDMOS器件6，其介质槽302侧壁左右第一导电类型注入区105换成第二导电类型介质电场增强结构208。
作为优选方式，所述的BCD半导体器件进一步为：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5，第一高压pLDMOS器件6，其介质槽302侧壁左右第一导电类型注入区105替换成第二导电类型介质电场增强结构208，同时其介质301上方第二导电类型埋层205替换成第一导电类型耐压结构106。
作为优选方式，所述的BCD半导体器件进一步为：所述第一高压nLIGBT器件1的发射极结构与第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6的源极结构，当器件的边缘以第n左元胞2(n)结束时，其沟道数量为2n+1；当n＝0时，器件为单沟道器件；当器件的边缘以第n右元胞1(n)结束，其沟道数量为2n，且n≥1；所述第二高压nLIGBT器件2的发射极结构为：当器件的边缘以第n左元胞2(n)结束时，其沟道数量为2n，且n≥1；当器件的边缘以第n右元胞1(n)结束，其沟道数量为2n+1，当n＝0时，器件为单沟道器件。
作为优选方式，所述的BCD半导体器件进一步为：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2的发射极结构，与第三高压nLDMOS器件5、第一高压pLDMOS器件6的源极结构还包含位于薄层介质层304与第二导电类型阱区206上表面之间的第二导电类型注入区207，此时上述的高压器件为耗尽型器件。
作为优选方式，所述的BCD半导体器件进一步为：所述第一高压nLIGBT器件1的发射极结构与第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6的源极结构中没有左元胞2(0)。
作为优选方式，所述的BCD半导体器件进一步为：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5中，第二导电类型阱区206不存在。
作为优选方式，所述的BCD半导体器件进一步为：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6中，介质槽302左右两侧的第一导电类型注入区105不存在，介质301上方第二导电类型埋层205也不存在。
作为优选方式，所述的BCD半导体器件进一步为：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6中，介质槽302中填充物402为多晶硅、或二氧化硅、或空气。
作为优选方式，所述的BCD半导体器件进一步为：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6中的第一导电类型区域102以及第二导电类型阱区206触及衬底101或者介质301，此时，所述的这些器件为单沟道器件。
作为优选方式，所述的BCD半导体器件进一步为：采用介质隔离，把高压器件做于介质岛内，或者把低压器件做在隔离岛之内。
作为优选方式，所述的BCD半导体器件进一步为：栅电极401为槽栅结构。
2、为实现上述发明目的，本发明还提供一种上述的BCD半导体器件的制造方法，包括以下步骤：
第一步，采用光刻和离子注入工艺，在衬底101中注入一定数量的氧离子，退火形成介质301；
第二步，采用光刻和离子注入工艺，在衬底101中注入第二导电类型杂质；
第三步，外延形成第二导电类型外延层201，同时利用此高温过程形成介质301上方的第二导电类型埋层205；
第四步，采用光刻和刻蚀工艺，在第二导电类型外延层201上电极刻蚀屏蔽层后进行深槽刻蚀，采用斜角注入的方式在深槽的侧壁形成第一导电类型注入区105；
第五步，通过热生长的方式在槽侧壁以及第二导电类型外延层201上表面生长氧化层，形成介质槽302，淀积多晶硅以填充深槽剩余空隙，第二导电类型外延层201上表面的多晶以及氧化物；
第六步，采用光刻和离子注入工艺，在第二导电类型外延层201上以不同的能量分别注入第一导电类型杂质以及第二导电类型杂质，退火形成第一导电类型区域102以及第二导电类型阱区206；
第七步，光刻出有源区，然后通过热生长的方式第二导电类型外延层201上表面生长场氧化层303；
第八步，采用光刻和离子注入工艺，在第二导电类型外延层201上注入第二导电类型杂质，退火形成第二导电类型缓冲区203；
第九步，热氧生长形成薄介质层304，淀积多晶硅，光刻以及离子注入，形成第一导电类型接触区103以及第二导电类型接触区202；
第十步，淀积金属前介质层305，打孔后淀积金属层501。
作为优选方式，所述的BCD半导体器件制造方法进一步为：第三步与第四步之间添加退火过程以确保形成第二导电类型埋层205；第六步采用淀积的方法先填充槽，然后再在进行场氧化层的生长。
3、为实现上述发明目的，本发明还提供一种BCD半导体器件，包括集成于同一芯片上的第三高压nLIGBT器件11；第四高压nLDMOS器件12、第五高压nLDMOS器件13、第六高压nLDMOS器件14、第二高压pLDMOS器件15、第二低压PMOS器件16、第二低压NMOS器件17、NPN器件18、第二PNP器件19和第二diode器件20，所述第三高压nLIGBT器件11和第四高压nLDMOS器件12、第五高压nLDMOS器件13、第六高压nLDMOS器件14、第二高压pLDMOS器件15均采用介质隔离，实现高低压器件完全隔离。
作为优选方式，所述的BCD半导体器件进一步为：
所述第三高压nLIGBT器件11，位于包括介质301、第一导电类型耐压结构106、介质槽302、填充物402以及第一导电类型注入区105的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第一导电类型外延层104中并延伸至衬底101且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第一导电类型耐压结构106位于介质301上方，所述第三高压nLIGBT器件11还包括：位于第一导电类型外延层104中的作为漂移区的第二导电类型阱区206，第二导电类型缓冲区203作为场阻区位于第二导电类型阱区206之中；一个第一导电类型接触区103作为集电极位于第二导电类型缓冲区203之中并且与金属层501相连；场氧化层303位于第二导电类型阱区206的上方，栅电极401以及薄介质层304位于场氧化层303靠近发射极的一侧，并且位于第一导电类型区域102的上表面；另一第一导电类型接触区103以及第二导电类型接触区202位于栅电极401远离场氧化层303的一侧且与金属层501相连；金属层501与栅电极401通过金属前介质层305隔离；
所述第四高压nLDMOS器件12，位于包括介质301、第一导电类型耐压结构106、介质槽302、填充物402以及第一导电类型注入区105的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第一导电类型外延层104中并延伸至衬底101且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第一导电类型耐压结构106位于介质301上方，所述第四高压nLDMOS器件12还包括：位于第一导电类型外延层104中的作为漂移区的第二导电类型阱区206；第二导电类型缓冲区203作为场阻区位于第二导电类型阱区206之中；一个第二导电类型接触区202作为漏极位于第二导电类型缓冲区203之中并且与金属层501相连；场氧化层303位于第二导电类型阱区206的上方，栅电极401以及薄介质层304位于场氧化层303靠近源极的一侧，并且位于第一导电类型区域102的上表面；第一导电类型接触区103以及另一第二导电类型接触区202位于栅电极401远离场氧化层303的一侧且与金属层501相连；金属层501与栅电极401通过金属前介质层305隔离；
所述第五高压nLDMOS器件13，和第四高压nLDMOS器件12的差别在于：第二导电类型注入区207位于第一导电类型区域102的上表面；栅电极401以及薄介质层304位于第二导电类型注入区207上表面；
所述第六高压nLDMOS器件14，和第四高压nLDMOS器件12的差别在于：第二导电类型阱区206的上方没有场氧化层303；
所述第二高压pLDMOS器件15，位于包括介质301、第二导电类型埋层205、介质槽302、填充物402以及第一导电类型注入区105的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第一导电类型外延层104中并延伸至衬底101且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第二导电类型埋层205位于介质301上方，所述第二高压pLDMOS器件15还包括：位于第一导电类型外延层104中的作为漏极的一个第一导电类型接触区103，并且与金属层501相连；栅电极401以及薄介质层304位于第二导电类型阱区206的上表面；场氧化层303位于第一导电类型外延层104上表面且在第二导电类型阱区206与上述第一导电类型接触区103之间，另一第一导电类型接触区103以及第二导电类型接触区202位于栅电极401远离场氧化层303的一侧且分别与金属层501相连；金属层501与栅电极401通过金属前介质层305隔离；
所述第二低压PMOS器件16设置在第二导电类型阱区206中，第二导电类型阱区206位于第一导电类型外延层104中，其中第二导电类型接触区202和一个第一导电类型接触区103分别与金属层501相连作为源极，位于第二导电类型阱区206内部的一侧，另一第一导电类型接触区103与金属层501相连作为漏极，位于第二导电类型阱区206内部的另一侧栅电极401处于薄介质层304上、金属前介质层305下；栅电极401、金属层501与栅电极4011通过金属前介质305相互隔离；
所述第二低压NMOS器件17设置在第一导电类型区域102中，第一导电类型区域102位于第一导电类型外延层104中，其一个第二导电类型接触区202和第一导电类型接触区103分别与金属层501相连作为源极，位于第一导电类型区域102内部的一侧，另一第二导电类型接触区202与金属层501相连作为漏极，位于第一导电类型区域102内部的另一侧；栅电极401处于薄介质层304上、金属前介质层305下；栅电极401和金属层501通过金属前介质层305相互隔离；
所述NPN器件18设置在第二导电类型阱区206中金属前介质层305之下，第二导电类型接触区202集电极置于第二导电类型阱区206中，第二导电类型接触区202发射极与第一导电类型接触区103基极位于第一导电类型区域102基区中，其中第二导电类型接触区202发射极、第二导电类型接触区202集电极、第一导电类型接触区103基极均与金属层501相接；
所述第二PNP器件19设置于第一导电类型外延层104中、金属前介质层305之下，第一导电类型接触区103集电极以及发射极分别位于第一导电类型区域102中，第二导电类型接触区202基极位于第二导电类型阱区206基区中，第一导电类型区域102也位于第二导电类型阱区206中，其中第一导电类型接触区103集电极、第一导电类型接触区103发射极、第二导电类型区域202基极均与金属层501相接；
所述第二diode器件20设置在第二导电类型阱区206中、金属前介质层305之下，第一导电类型接触区103阳极置于第二导电类型阱区206中，第二导电类型接触区202阴极位于第二导电类型阱区206中，其中第一导电类型接触区103阳极、第二导电类型接触区202阴极与金属层501相接。
4、为实现上述发明目的，本发明还提供一种BCD半导体器件的制造方法，包括以下步骤：
第一步，采用光刻和离子注入工艺，在衬底101中注入一定数量的氧离子，退火形成介质301；
第二步，采用光刻和离子注入工艺，在衬底101中注入第一导电类型杂质；
第三步，外延形成第一导电类型外延层104，同时利用此高温退火过程形成介质301上方的第一导电类型耐压结构106；
第四步，采用光刻和刻蚀工艺，在第一导电类型外延层104上电极刻蚀屏蔽层后进行深槽刻蚀，采用斜角注入的方式在深槽的侧壁形成第一导电类型注入区105；
第五步，通过热生长的方式在槽侧壁以及第一导电类型外延层104上表面生长氧化层，形成介质槽302，淀积多晶硅以填充深槽剩余空隙，CMP去掉第二导电类型外延层201上表面的多晶硅以及氧化层；
第六步，采用光刻和离子注入工艺，在第一导电类型外延层104上以不同的能量分别注入第一导电类型杂质以及第二导电类型杂质，退火形成第一导电类型区域102以及第二导电类型阱区206；
第七步，光刻出有源区，通过热生长的方式在第一导电类型外延层104上表面生长氧化层，形成场氧化层303，去掉光刻胶；
第八步，采用光刻和离子注入工艺，在第一导电类型外延层104上注入第二导电类型杂质，退火形成第二导电类型缓冲区203；热氧生长形成薄介质层304，淀积栅电极401，光刻；
第九步，光刻以及离子注入，形成第一导电类型接触区103以及第二导电类型接触区202；
第十步，淀积金属前介质层305，打孔后淀积金属层501。
作为优选方式，第三步与第四步之间添加退火过程以确保形成第一导电类型耐压结构106；第六步采用淀积的方法先填充槽，然后再在进行场氧化层的生长。
本发明的优点是：本发明在衬底上实现nLIGBT、nLDMOS、低压NMOS、低压PMOS和低压NPN的单片集成。一方面，由介质、第二导电类型埋层、介质槽以及第一导电类型注入区组成的隔离区域实现集成芯片上的高低压全介质隔离，避免了高低压的串扰问题，另一方面，在六类的高压管子中均采用了多沟道设计，可以有效增加高压管的电流输出能力。工艺上，该工艺属于体硅工艺，成本相对较低，却可以达到与SOI工艺比拟的可靠水平。
附图说明
图1是本发明实施例1提供的BCD半导体器件的结构示意图。
图2是本发明实施例2提供的BCD半导体器件的结构示意图。
图3是本发明实施例3提供的BCD半导体器件的结构示意图。
图4是本发明实施例5提供的BCD半导体器件的结构示意图。
图5是本发明实施例6提供的BCD半导体器件的结构示意图。
图6是本发明实施例7提供的BCD半导体器件的结构示意图。
图7是本发明实施例8提供的BCD半导体器件的结构示意图。
图8是本发明实施例1提供的BCD器件的工艺流程图。
图9是本发明实施例1的一种BCD器件的工艺流程图。
图10是本发明实施例8的一种BCD器件的工艺流程图。
其中，1为第一高压nLIGBT器件，2为第二高压nLIGBT器件，3为第一高压nLDMOS器件，4为第二高压nLDMOS器件，5为第三高压nLDMOS器件，6为第一高压pLDMOS器件，7为低压NMOS器件，8为低压PMOS器件，9为PNP器件，10为diode器件，11为第三高压nLIGBT器件，12为第四高压nLDMOS器件，13为第五高压nLDMOS器件，14为第六高压nLDMOS器件，15为第二高压pLDMOS器件，16为第二低压PMOS器件，17为第二低压NMOS器件，18为NPN器件，19为第二PNP器件，20为第二diode器件；
101为衬底，102为第一导电类型区域、103为第一导电类型接触区，104为第一导电类型外延层，105为第一导电类型注入区，106为第一导电类型耐压结构；201为第二导电类型外延层，202为第二导电类型接触区，203为第二导电类型缓冲区，205为第二导电类型埋层，206为第二导电类型阱区，207为第二导电类型注入区，208为第二导电类型介质电场增强结构，301为介质，302为介质槽，303为场氧化层，304为薄介质层，305为金属前介质层，401为栅电极，402为填充物，501为金属层。
2(0)为左元胞，2(1)第一左元胞，2(2)为第二左元胞…2(n)为第n左元胞；1(1)为第一右元胞，1(2)为第二右元胞…1(n)为第n右元胞。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
实施例1
如图1所示，一种BCD半导体器件，包括集成于同一芯片上的第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6、低压NMOS器件7、低压PMOS器件8、PNP器件9和diode器件10，所述第一高压nLIGBT器件1、第二高压nLIGBT器件2和第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6均采用介质隔离，实现高低压器件完全隔离，第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5采用多沟道设计。
所述第一高压nLIGBT器件1，位于包括介质301、第二导电类型埋层205、介质槽302、填充物402以及第一导电类型注入区105的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第二导电类型外延层201中并延伸至衬底101、且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第二导电类型埋层205位于介质301上方，所述高压nLIGBT器件1还包括：位于器件两侧的多沟道发射极，多沟道发射极包括按照左元胞2(0)、第一右元胞1(1)、第一左元胞2(1)、第二右元胞1(2)、第二左元胞2(2)、……第n右元胞1(n)、第n左元胞2(n)…的顺序交替排列的多个元胞，所述高压nLIGBT器件1还包括：由第二导电类型外延层201构成的漂移区，由第二导电类型缓冲区203和与金属501直接相连的第一导电类型接触区103组成的集电极，位于第二导电类型外延层201表面的场氧化层303、金属层501以及金属前介质层305，其中，发射极的每一个元胞包括第二导电类型阱区206、位于第二导电类型阱区206中的第一导电类型区域102、与金属501直接相连且位于第一导电类型区域102中的第一导电类型接触区103、第二导电类型接触区202、位于第一导电类型区域102上表面的薄介质层304以及栅电极401；通过栅电极401与薄层介质304对第一导电类型区域102表面的导电类型进行控制从而实现器件的开启与关断。
所述第二高压nLIGBT器件2与第一高压nLIGBT器件1的差别在于：所述第二类高压nLIGBT器件2的多沟道发射极包括多个按照第一右元胞1(1)、第一左元胞2(1)、第二右元胞1(2)、第二左元胞2(2)、……第n右元胞1(n)、第n左元胞2(n)…的顺序交替排列的多个元胞；
所述第一高压nLDMOS器件3，位于包括介质301、第二导电类型埋层205、介质槽302、填充物402以及第一导电类型注入区105的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第二导电类型外延层201中并延伸至衬底101且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第二导电类型埋层205位于介质301上方，第一高压nLDMOS器件3还包括：位于器件两侧的多沟道源极，多沟道源极包括按照左元胞2(0)、第一右元胞1(1)、第一左元胞2(1)、第二右元胞1(2)、第二左元胞2(2)、……第n右元胞1(n)、第n左元胞2(n)的顺序交替排列的多个元胞，所述第一高压nLDMOS器件3还包括：第二导电类型外延层201构成的漂移区、由第二导电类型缓冲区203和与金属层501直接相连的第二导电类型接触区202组成的漏电极、位于第二导电类型外延层201表面的场氧化层303、金属层501以及金属前介质层305，其中，源极的每一个元胞包括第二导电类型阱区206、位于第二导电类型阱区206中的第一导电类型区域102、与金属层501直接相连且位于第一导电类型区域102中的第一导电类型接触区103、第二导电类型接触区202、位于第一导电类型区域102上表面的薄介质层304以及栅电极401；通过栅电极401与薄层介质304对第一导电类型区域102表面的导电类型进行控制从而实现器件的开启与关断。
所述第二高压nLDMOS器件4和第一高压nLDMOS器件3的差别在于：薄层介质层304与第二导电类型阱区206上表面之间设有第二导电类型注入区207；
所述第三高压nLDMOS器件5和第一高压nLDMOS器件3的差别在于：第二导电类型外延层201表面无场氧化层303；
所述第一高压pLDMOS器件6，位于包括介质301、第二导电类型埋层205、介质槽302、填充物402以及第一导电类型注入区105组成的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第二导电类型外延层201中并延伸至衬底101且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第二导电类型埋层205位于介质301上方，所述高压pLDMOS器件6还包括：由位于器件两侧的左元胞2(0)构成的源极、由位于第二导电类型外延层201中的第一导电类型区域102构成的漂移区、由位于第一导电类型区域102中的一个第一导电类型接触区103构成的漏极、位于第二导电类型外延层201上方场氧化层303、金属层501以及金属前介质层305，构成源极的左元胞2(0)包括第二导电类型阱区206、位于第二导电类型阱区206中且与金属层501直接相连的另一第一导电类型接触区103以及第二导电类型接触区202、位于第二导电类型阱区206区域上表面的薄介质层304以及栅电极401；通过栅电极401与薄介质层304对第二导电类型阱区206表面的导电类型进行控制从而实现器件的开启与关断。
所述低压NMOS器件7设置在第一导电类型区域102中，第一导电类型区域102位于第二导电类型外延层201中，第二导电类型接触区202和一个第一导电类型接触区103作为源极，位于第一导电类型区域102的一侧且分别与金属层501相连；另一第一导电类型接触区103作为漏极，位于第一导电类型区域102的另一侧且与金属层501相连，栅电极401处于薄介质层304上、金属前介质层305下；栅电极401和金属层501通过金属前介质层305相互隔离；
所述低压PMOS器件8设置在第二导电类型阱区206中，第二导电类型阱区206位于第二导电类型外延层201中，第二导电类型接触区202和一个第一导电类型接触区103作为源极位于第一导电类型区域102的一侧且与金属层501相连；另一第一导电类型接触区103作为漏极，位于第一导电类型区域102的另一侧且与金属层501相连，栅电极401处于薄介质层304上、金属前介质层305下；金属层501和栅电极401通过金属前介质层305相互隔离；
所述PNP器件9设置在第一导电类型区域102中金属前介质层305之下，第一导电类型接触区103集电极置于第一导电类型区域102中，第一导电类型接触区103发射极与第二导电类型接触区202基极位于第二导电类型缓冲区203基区中，第二导电类型缓冲区203位于第一导电类型区域102中，其中第一导电类型接触区103集电极、第一导电类型接触区103发射极、第二导电类型接触区202基极均与金属层501相接；
所述diode器件10设置在第一导电类型区域102中金属前介质层305之下，第一导电类型接触区103阳极置于第一导电类型区域102中，第二导电类型接触区202阴极位于第一导电类型区域102中，其中第一导电类型接触区103阳极、第二导电类型接触区202阴极与金属层501相接。
所述的BCD半导体器件中，一方面，由介质301、第二导电类型埋层205、介质槽302以及第一导电类型注入区105组成的隔离区域实现集成芯片上的高低压全介质隔离，避免了高低压的串扰问题，另一方面，在六类的高压管子中均采用了多沟道设计，可以有效增加高压管的电流输出能力。工艺上，该工艺属于体硅工艺，成本相对较低，却可以达到与SOI工艺比拟的可靠水平。
所述第一高压nLIGBT器件1的发射极结构与第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6的源极结构，当器件的边缘以第n左元胞2(n)结束时，其沟道数量为2n+1；当n＝0时，器件为单沟道器件；当器件的边缘以第n右元胞1(n)结束，其沟道数量为2n，且n≥1；所述第二高压nLIGBT器件2的发射极结构：当器件的边缘以第n左元胞2(n)结束时，其沟道数量为2n，且n≥1；当器件的边缘以第n右元胞1(n)结束，其沟道数量为2n+1，当n＝0时，器件为单沟道器件。
优选的，所述第一高压nLIGBT器件1、第二高压nLIGBT器件2的发射极结构，与第三高压nLDMOS器件5、第一高压pLDMOS器件6的源极结构还包含位于薄层介质层304与第二导电类型阱区206上表面之间的第二导电类型注入区207，此时上述的高压器件为耗尽型器件。
优选的，所述第一高压nLIGBT器件1的发射极结构与第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6的源极结构中没有左元胞2(0)。
优选的，所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5中，载流子存储层206不存在。
优选的，所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6中，介质槽302左右两侧的第一导电类型注入区105不存在，介质301上方第二导电类型埋层205也不存在。
优选的，所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6中，介质槽302中填充物402为多晶硅、或二氧化硅、或空气。
如图8所示，上述BCD半导体器件的制造方法，包括以下步骤：
第一步，采用光刻和离子注入工艺，在衬底101中注入一定数量的氧离子，退火形成介质301；
第二步，采用光刻和离子注入工艺，在衬底101中注入第二导电类型杂质；
第三步，外延形成第二导电类型外延层201，同时利用此高温过程形成介质301上方的第二导电类型埋层205；
第四步，采用光刻和刻蚀工艺，在第二导电类型外延层201上电极刻蚀屏蔽层后进行深槽刻蚀，采用斜角注入的方式在深槽的侧壁形成第一导电类型注入区105；
第五步，通过热生长的方式在槽侧壁以及第二导电类型外延层201上表面生长氧化层，形成介质槽302，淀积多晶硅以填充深槽剩余空隙，第二导电类型外延层201上表面的多晶以及氧化物；
第六步，采用光刻和离子注入工艺，在第二导电类型外延层201上以不同的能量分别注入第一导电类型杂质以及第二导电类型杂质，退火形成第一导电类型区域102以及第二导电类型阱区206；
第七步，光刻出有源区，然后通过热生长的方式第二导电类型外延层201上表面生长场氧化层303；
第八步，采用光刻和离子注入工艺，在第二导电类型外延层201上注入第二导电类型杂质，退火形成第二导电类型缓冲区203；
第九步，热氧生长形成薄介质层304，淀积多晶硅，光刻以及离子注入，形成第一导电类型接触区103以及第二导电类型接触区202；
第十步，淀积金属前介质层305，打孔后淀积金属层501。
优选的，第三步与第四步之间添加退火过程以确保形成第二导电类型埋层205；第六步采用淀积的方法先填充槽，然后再在进行场氧化层的生长。
实施例2
如图2所示，本实施例的BCD半导体器件，和实施例1的区别在于：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5，第一高压pLDMOS器件6，其介质301上方第二导电类型埋层205换成第一导电类型耐压结构106，第一导电类型耐压结构106与介质槽302侧壁的第一导电类型注入区105相连。
实施例3
如图3所示，本实施例的BCD半导体器件，和实施例1的区别在于：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5，第一高压pLDMOS器件6，其介质槽302侧壁左右第一导电类型注入区105换成第二导电类型介质电场增强结构208。
实施例4
本实施例的BCD半导体器件，和实施例1的区别在于：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5，第一高压pLDMOS器件6，其介质槽302侧壁左右第一导电类型注入区105替换成第二导电类型介质电场增强结构208，同时其介质301上方第二导电类型埋层205替换成第一导电类型耐压结构106。
实施例5
如图4所示，本实施例的BCD半导体器件，和实施例1的区别在于：所述第一高压nLIGBT器件1、第二高压nLIGBT器件2、第一高压nLDMOS器件3、第二高压nLDMOS器件4、第三高压nLDMOS器件5、第一高压pLDMOS器件6中的第一导电类型区域102以及第二导电类型阱区206触及衬底101或者介质301，此时，所述的这些器件为单沟道器件。
实施例6
如图5所示，本实施例的BCD半导体器件，和实施例1的区别在于：采用介质隔离，把高压器件做于介质岛内，或者把低压器件做在隔离岛之内。
实施例7
如图6所示，本实施例的BCD半导体器件，和实施例1的区别在于：栅电极401为槽栅结构。
实施例8
如图7所示，一种BCD半导体器件，包括集成于同一芯片上的第三高压nLIGBT器件11；第四高压nLDMOS器件12、第五高压nLDMOS器件13、第六高压nLDMOS器件14、第二高压pLDMOS器件15、第二低压PMOS器件16、第二低压NMOS器件17、NPN器件18、第二PNP器件19和第二diode器件20，所述第三高压nLIGBT器件11和第四高压nLDMOS器件12、第五高压nLDMOS器件13、第六高压nLDMOS器件14、第二高压pLDMOS器件15均采用介质隔离，实现高低压器件完全隔离。
所述第三高压nLIGBT器件11，位于包括介质301、第一导电类型耐压结构106、介质槽302、填充物402以及第一导电类型注入区105的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第一导电类型外延层104中并延伸至衬底101且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第一导电类型耐压结构106位于介质301上方，所述第三高压nLIGBT器件11还包括：位于第一导电类型外延层104中的作为漂移区的第二导电类型阱区206，第二导电类型缓冲区203作为场阻区位于第二导电类型阱区206之中；一个第一导电类型接触区103作为集电极位于第二导电类型缓冲区203之中并且与金属层501相连；场氧化层303位于第二导电类型阱区206的上方，栅电极401以及薄介质层304位于场氧化层303靠近发射极的一侧，并且位于第一导电类型区域102的上表面；另一第一导电类型接触区103以及第二导电类型接触区202位于栅电极401远离场氧化层303的一侧且与金属层501相连；金属层501与栅电极401通过金属前介质层305隔离；
所述第四高压nLDMOS器件12，位于包括介质301、第一导电类型耐压结构106、介质槽302、填充物402以及第一导电类型注入区105的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第一导电类型外延层104中并延伸至衬底101且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第一导电类型耐压结构106位于介质301上方，所述第四高压nLDMOS器件12还包括：位于第一导电类型外延层104中的作为漂移区的第二导电类型阱区206；第二导电类型缓冲区203作为场阻区位于第二导电类型阱区206之中；一个第二导电类型接触区202作为漏极位于第二导电类型缓冲区203之中并且与金属层501相连；场氧化层303位于第二导电类型阱区206的上方，栅电极401以及薄介质层304位于场氧化层303靠近源极的一侧，并且位于第一导电类型区域102的上表面；第一导电类型接触区103以及另一第二导电类型接触区202位于栅电极401远离场氧化层303的一侧且与金属层501相连；金属层501与栅电极401通过金属前介质层305隔离；
所述第五高压nLDMOS器件13，和第四高压nLDMOS器件12的差别在于：第二导电类型注入区207位于第一导电类型区域102的上表面；栅电极401以及薄介质层304位于第二导电类型注入区207上表面；
所述第六高压nLDMOS器件14，和第四高压nLDMOS器件12的差别在于：第二导电类型阱区206的上方没有场氧化层303；
所述第二高压pLDMOS器件15，位于包括介质301、第二导电类型埋层205、介质槽302、填充物402以及第一导电类型注入区105的隔离区域内，其中，介质301位于衬底101中，介质槽302位于第一导电类型外延层104中并延伸至衬底101且与介质301相接形成完全隔离，第一导电类型注入区105位于介质槽302左右两侧，填充物402位于介质槽302中间，第二导电类型埋层205位于介质301上方，所述第二高压pLDMOS器件15还包括：位于第一导电类型外延层104中的作为漏极的一个第一导电类型接触区103，并且与金属层501相连；栅电极401以及薄介质层304位于第二导电类型阱区206的上表面；场氧化层303位于第一导电类型外延层104上表面且在第二导电类型阱区206与上述第一导电类型接触区103之间，另一第一导电类型接触区103以及第二导电类型接触区202位于栅电极401远离场氧化层303的一侧且分别与金属层501相连；金属层501与栅电极401通过金属前介质层305隔离；
所述第二低压PMOS器件16设置在第二导电类型阱区206中，第二导电类型阱区206位于第一导电类型外延层104中，其中第二导电类型接触区202和一个第一导电类型接触区103分别与金属层501相连作为源极，位于第二导电类型阱区206内部的一侧，另一第一导电类型接触区103与金属层501相连作为漏极，位于第二导电类型阱区206内部的另一侧栅电极401处于薄介质层304上、金属前介质层305下；栅电极401、金属层501与栅电极4011通过金属前介质305相互隔离；
所述第二低压NMOS器件17设置在第一导电类型区域102中，第一导电类型区域102位于第一导电类型外延层104中，其一个第二导电类型接触区202和第一导电类型接触区103分别与金属层501相连作为源极，位于第一导电类型区域102内部的一侧，另一第二导电类型接触区202与金属层501相连作为漏极，位于第一导电类型区域102内部的另一侧；栅电极401处于薄介质层304上、金属前介质层305下；栅电极401和金属层501通过金属前介质层305相互隔离；
所述NPN器件18设置在第二导电类型阱区206中金属前介质层305之下，第二导电类型接触区202集电极置于第二导电类型阱区206中，第二导电类型接触区202发射极与第一导电类型接触区103基极位于第一导电类型区域102基区中，其中第二导电类型接触区202发射极、第二导电类型接触区202集电极、第一导电类型接触区103基极均与金属层501相接；
所述第二PNP器件19设置于第一导电类型外延层104中、金属前介质层305之下，第一导电类型接触区103集电极以及发射极分别位于第一导电类型区域102中，第二导电类型接触区202基极位于第二导电类型阱区206基区中，第一导电类型区域102也位于第二导电类型阱区206中，其中第一导电类型接触区103集电极、第一导电类型接触区103发射极、第二导电类型区域202基极均与金属层501相接；
所述第二diode器件20设置在第二导电类型阱区206中、金属前介质层305之下，第一导电类型接触区103阳极置于第二导电类型阱区206中，第二导电类型接触区202阴极位于第二导电类型阱区206中，其中第一导电类型接触区103阳极、第二导电类型接触区202阴极与金属层501相接。
所述的BCD半导体器件的制造方法，包括以下步骤：
第一步，采用光刻和离子注入工艺，在衬底101中注入一定数量的氧离子，退火形成介质301；
第二步，采用光刻和离子注入工艺，在衬底101中注入第一导电类型杂质；
第三步，外延形成第一导电类型外延层104，同时利用此高温退火过程形成介质301上方的第一导电类型耐压结构106；
第四步，采用光刻和刻蚀工艺，在第一导电类型外延层104上电极刻蚀屏蔽层后进行深槽刻蚀，采用斜角注入的方式在深槽的侧壁形成第一导电类型注入区105；
第五步，通过热生长的方式在槽侧壁以及第一导电类型外延层104上表面生长氧化层，形成介质槽302，淀积多晶硅以填充深槽剩余空隙，CMP去掉第二导电类型外延层201上表面的多晶硅以及氧化层；
第六步，采用光刻和离子注入工艺，在第一导电类型外延层104上以不同的能量分别注入第一导电类型杂质以及第二导电类型杂质，退火形成第一导电类型区域102以及第二导电类型阱区206；
第七步，光刻出有源区，通过热生长的方式在第一导电类型外延层104上表面生长氧化层，形成场氧化层303，去掉光刻胶；
第八步，采用光刻和离子注入工艺，在第一导电类型外延层104上注入第二导电类型杂质，退火形成第二导电类型缓冲区203；热氧生长形成薄介质层304，淀积栅电极401，光刻；
第九步，光刻以及离子注入，形成第一导电类型接触区103以及第二导电类型接触区202；
第十步，淀积金属前介质层305，打孔后淀积金属层501。
优选的，第三步与第四步之间添加退火过程以确保形成第一导电类型耐压结构106；第六步采用淀积的方法先填充槽，然后再在进行场氧化层的生长。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (18)

1.一种BCD半导体器件，其特征在于：包括集成于同一芯片上的第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)、第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)、第一高压pLDMOS器件(6)、低压NMOS器件(7)、低压PMOS器件(8)、PNP器件(9)和diode器件(10)，所述第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)和第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)、第一高压pLDMOS器件(6)均采用介质隔离，实现高压器件完全隔离，第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)、第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)采用多沟道设计；
所述第一高压nLIGBT器件(1)，位于包括介质(301)、第二导电类型埋层(205)、介质槽(302)、填充物(402)以及第一导电类型注入区(105)的隔离区域内，其中，介质(301)位于衬底(101)中，介质槽(302)位于第二导电类型外延层(201)中并延伸至衬底(101)、且与介质(301)相接形成完全隔离，第一导电类型注入区(105)位于介质槽(302)左右两侧，填充物(402)位于介质槽(302)中间，第二导电类型埋层(205)位于介质(301)上方，所述高压nLIGBT器件(1)还包括：位于器件两侧的多沟道发射极，多沟道发射极包括按照左元胞2(0)、第一右元胞1(1)、第一左元胞2(1)、第二右元胞1(2)、第二左元胞2(2)、……第n右元胞1(n)、第n左元胞2(n)…的顺序交替排列的多个元胞，所述高压nLIGBT器件(1)还包括：由第二导电类型外延层(201)构成的漂移区，由第二导电类型缓冲区(203)和与金属(501)直接相连的第一导电类型接触区(103)组成的集电极，位于第二导电类型外延层(201)表面的场氧化层(303)、金属层(501)以及金属前介质层(305)，其中，发射极的每一个元胞包括第二导电类型阱区(206)、位于第二导电类型阱区(206)中的第一导电类型区域(102)、与金属(501)直接相连且位于第一导电类型区域(102)中的第一导电类型接触区(103)、第二导电类型接触区(202)、位于第一导电类型区域(102)上表面的薄介质层(304)以及栅电极(401)；
所述第二高压nLIGBT器件(2)与第一高压nLIGBT器件(1)的差别在于：第二高压nLIGBT器件(2)的多沟道发射极包括多个按照第一右元胞1(1)、第一左元胞2(1)、第二右元胞1(2)、第二左元胞2(2)、……第n右元胞1(n)、第n左元胞2(n)…的顺序交替排列的多个元胞；
所述第一高压nLDMOS器件(3)，位于包括介质(301)、第二导电类型埋层(205)、介质槽(302)、填充物(402)以及第一导电类型注入区(105)的隔离区域内，其中，介质(301)位于衬底(101)中，介质槽(302)位于第二导电类型外延层(201)中并延伸至衬底(101)且与介质(301)相接形成完全隔离，第一导电类型注入区(105)位于介质槽(302)左右两侧，填充物(402)位于介质槽(302)中间，第二导电类型埋层(205)位于介质(301)上方，第一高压nLDMOS器件(3)还包括：位于器件两侧的多沟道源极，多沟道源极包括按照左元胞2(0)、第一右元胞1(1)、第一左元胞2(1)、第二右元胞1(2)、第二左元胞2(2)、……第n右元胞1(n)、第n左元胞2(n)…的顺序交替排列的多个元胞，所述第一高压nLDMOS器件(3)还包括：第二导电类型外延层(201)构成的漂移区、由第二导电类型缓冲区(203)和与金属层(501)直接相连的第二导电类型接触区(202)组成的漏电极、位于第二导电类型外延层(201)表面的场氧化层(303)、金属层(501)以及金属前介质层(305)，其中，源极的每一个元胞包括第二导电类型阱区(206)、位于第二导电类型阱区(206)中的第一导电类型区域(102)、与金属层(501)直接相连且位于第一导电类型区域(102)中的第一导电类型接触区(103)、第二导电类型接触区(202)、位于第一导电类型区域(102)上表面的薄介质层(304)以及栅电极(401)；
所述第二高压nLDMOS器件(4)和第一高压nLDMOS器件(3)的差别在于：薄层介质层(304)与第二导电类型阱区(206)上表面之间设有第二导电类型注入区(207)；
所述第三高压nLDMOS器件(5)和第一高压nLDMOS器件(3)的差别在于：第二导电类型外延层(201)表面无场氧化层(303)；
所述第一高压pLDMOS器件(6)，位于包括介质(301)、第二导电类型埋层(205)、介质槽(302)、填充物(402)以及第一导电类型注入区(105)组成的隔离区域内，其中，介质(301)位于衬底(101)中，介质槽(302)位于第二导电类型外延层(201)中并延伸至衬底(101)且与介质(301)相接形成完全隔离，第一导电类型注入区(105)位于介质槽(302)左右两侧，填充物(402)位于介质槽(302)中间，第二导电类型埋层(205)位于介质(301)上方，所述高压pLDMOS器件(6)还包括：由位于器件两侧的左元胞2(0)构成的源极、由位于第二导电类型外延层(201)中的第一导电类型区域(102)构成的漂移区、由位于第一导电类型区域(102)中的一个第一导电类型接触区(103)构成的漏极、位于第二导电类型外延层(201)上方场氧化层(303)、金属层(501)以及金属前介质层(305)，构成源极的左元胞2(0)包括第二导电类型阱区(206)、位于第二导电类型阱区(206)中且与金属层(501)直接相连的另一第一导电类型接触区(103)以及第二导电类型接触区(202)、位于第二导电类型阱区(206)区域上表面的薄介质层(304)以及栅电极(401)；
所述低压NMOS器件(7)设置在第一导电类型区域(102)中，第一导电类型区域(102)位于第二导电类型外延层(201)中，第二导电类型接触区(202)和一个第一导电类型接触区(103)作为源极，位于第一导电类型区域(102)的一侧且分别与金属层(501)相连；另一第一导电类型接触区(103)作为漏极，位于第一导电类型区域(102)的另一侧且与金属层(501)相连，栅电极(401)处于薄介质层(304)上、金属前介质层(305)下；栅电极(401)和金属层(501)通过金属前介质层(305)相互隔离；
所述低压PMOS器件(8)设置在第二导电类型阱区(206)中，第二导电类型阱区(206)位于第二导电类型外延层(201)中，第二导电类型接触区(202)和一个第一导电类型接触区(103)作为源极位于第一导电类型区域(102)的一侧且与金属层(501)相连；另一第一导电类型接触区(103)作为漏极，位于第一导电类型区域(102)的另一侧且与金属层(501)相连，栅电极(401)处于薄介质层(304)上、金属前介质层(305)下；金属层(501)和栅电极(401)通过金属前介质层(305)相互隔离；
所述PNP器件(9)设置在第一导电类型区域(102)中金属前介质层(305)之下，第一导电类型接触区(103)集电极置于第一导电类型区域(102)中，第一导电类型接触区(103)发射极与第二导电类型接触区(202)基极位于第二导电类型缓冲区(203)基区中，第二导电类型缓冲区(203)位于第一导电类型区域(102)中，其中第一导电类型接触区(103)集电极、第一导电类型接触区(103)发射极、第二导电类型接触区(202)基极均与金属层(501)相接；
所述diode器件(10)设置在第一导电类型区域(102)中金属前介质层(305)之下，第一导电类型接触区(103)阳极置于第一导电类型区域(102)中，第二导电类型接触区(202)阴极位于第一导电类型区域(102)中，其中第一导电类型接触区(103)阳极、第二导电类型接触区(202)阴极与金属层(501)相接。
2.如权利要求1所述的一种BCD半导体器件，其特征在于：所述第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)、第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)，第一高压pLDMOS器件(6)，其介质(301)上方第二导电类型埋层(205)换成第一导电类型耐压结构(106)，第一导电类型耐压结构(106)与介质槽(302)侧壁的第一导电类型注入区(105)相连。
3.如权利要求1所述的一种BCD半导体器件，其特征在于：所述第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)、第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)，第一高压pLDMOS器件(6)，其介质槽(302)侧壁左右第一导电类型注入区(105)换成第二导电类型介质电场增强结构(208)。
4.如权利要求1所述的一种BCD半导体器件，其特征在于：所述第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)、第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)，第一高压pLDMOS器件(6)，其介质槽(302)侧壁左右第一导电类型注入区(105)替换成第二导电类型介质电场增强结构(208)，同时其介质(301)上方第二导电类型埋层(205)替换成第一导电类型耐压结构(106)。
5.如权利要求1所述的一种BCD半导体器件，其特征在于：所述第一高压nLIGBT器件(1)的发射极结构与第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)、第一高压pLDMOS器件(6)的源极结构，当器件的边缘以第n左元胞2(n)结束时，其沟道数量为2n+1；当n＝0时，器件为单沟道器件；当器件的边缘以第n右元胞1(n)结束，其沟道数量为2n，且n≥1；所述第二高压nLIGBT器件(2)的发射极结构：当器件的边缘以第n左元胞2(n)结束时，其沟道数量为2n，且n≥1；当器件的边缘以第n右元胞1(n)结束，其沟道数量为2n+1，当n＝0时，器件为单沟道器件。
6.如权利要求1所述的一种BCD半导体器件，其特征在于：所述第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)的发射极结构，与第三高压nLDMOS器件(5)、第一高压pLDMOS器件(6)的源极结构还包含位于薄层介质层(304)与第二导电类型阱区(206)上表面之间的第二导电类型注入区(207)。
7.如权利要求1所述的一种BCD半导体器件，其特征在于：所述第一高压nLIGBT器件(1)的发射极结构与第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)、第一高压pLDMOS器件(6)的源极结构中没有左元胞2(0)。
8.如权利要求1所述的一种BCD半导体器件，其特征在于：所述第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)、第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)中，第二导电类型阱区(206)不存在。
9.如权利要求1所述的一种BCD半导体器件，其特征在于：所述第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)、第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)、第一高压pLDMOS器件(6)中，介质槽(302)左右两侧的第一导电类型注入区(105)不存在，介质(301)上方第二导电类型埋层(205)也不存在。
10.如权利要求1所述的一种BCD半导体器件，其特征在于：所述第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)、第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)、第一高压pLDMOS器件(6)中，介质槽(302)中填充物(402)为多晶硅、或二氧化硅、或空气。
11.如权利要求1所述的一种BCD半导体器件，其特征在于：所述第一高压nLIGBT器件(1)、第二高压nLIGBT器件(2)、第一高压nLDMOS器件(3)、第二高压nLDMOS器件(4)、第三高压nLDMOS器件(5)、第一高压pLDMOS器件(6)中的第一导电类型区域(102)以及第二导电类型阱区(206)触及衬底(101)或者介质(301)，此时，所述的这些器件为单沟道器件。
12.如权利要求1所述的一种BCD半导体器件，其特征在于：采用介质隔离，把高压器件做于介质岛内，或者把低压器件做在隔离岛之内。
13.如权利要求1所述的一种BCD半导体器件，其特征在于：栅电极(401)为槽栅结构。
14.权利要求1所述的一种BCD半导体器件的制造方法，其特征在于包括以下步骤：
第一步，采用光刻和离子注入工艺，在衬底(101)中注入一定数量的氧离子，退火形成介质(301)；
第二步，采用光刻和离子注入工艺，在衬底(101)中注入第二导电类型杂质；
第三步，外延形成第二导电类型外延层(201)，同时利用此高温过程形成介质(301)上方的第二导电类型埋层(205)；
第四步，采用光刻和刻蚀工艺，在第二导电类型外延层(201)上电极刻蚀屏蔽层后进行深槽刻蚀，采用斜角注入的方式在深槽的侧壁形成第一导电类型注入区(105)；
第五步，通过热生长的方式在槽侧壁以及第二导电类型外延层(201)上表面生长氧化层，形成介质槽(302)，淀积多晶硅以填充深槽剩余空隙，第二导电类型外延层(201)上表面的多晶以及氧化物；
第六步，采用光刻和离子注入工艺，在第二导电类型外延层(201)上以不同的能量分别注入第一导电类型杂质以及第二导电类型杂质，退火形成第一导电类型区域(102)以及第二导电类型阱区(206)；
第七步，光刻出有源区，然后通过热生长的方式第二导电类型外延层(201)上表面生长场氧化层(303)；
第八步，采用光刻和离子注入工艺，在第二导电类型外延层(201)上注入第二导电类型杂质，退火形成第二导电类型缓冲区(203)；
第九步，热氧生长形成薄介质层(304)，淀积多晶硅，光刻以及离子注入，形成第一导电类型接触区(103)以及第二导电类型接触区(202)；
第十步，淀积金属前介质层(305)，打孔后淀积金属层(501)。
15.如权利要求14所述的一种BCD半导体器件制造方法，其特征在于：第三步与第四步之间添加退火过程以确保形成第二导电类型埋层(205)；第六步采用淀积的方法先填充槽，然后再在进行场氧化层的生长。
16.一种BCD半导体器件，其特征在于：包括集成于同一芯片上的第三高压nLIGBT器件(11)；第四高压nLDMOS器件(12)、第五高压nLDMOS器件(13)、第六高压nLDMOS器件(14)、第二高压pLDMOS器件(15)、第二低压PMOS器件(16)、第二低压NMOS器件(17)、NPN器件(18)、第二PNP器件(19)和第二diode器件(20)，所述第三高压nLIGBT器件(11)和第四高压nLDMOS器件(12)、第五高压nLDMOS器件(13)、第六高压nLDMOS器件(14)、第二高压pLDMOS器件(15)均采用介质隔离，实现高低压器件完全隔离；
所述第三高压nLIGBT器件(11)，位于包括介质(301)、第一导电类型耐压结构(106)、介质槽(302)、填充物(402)以及第一导电类型注入区(105)的隔离区域内，其中，介质(301)位于衬底(101)中，介质槽(302)位于第一导电类型外延层(104)中并延伸至衬底(101)且与介质(301)相接形成完全隔离，第一导电类型注入区(105)位于介质槽(302)左右两侧，填充物(402)位于介质槽(302)中间，第一导电类型耐压结构(106)位于介质(301)上方，所述第三高压nLIGBT器件(11)还包括：位于第一导电类型外延层(104)中的作为漂移区的第二导电类型阱区(206)，第二导电类型缓冲区(203)作为场阻区位于第二导电类型阱区(206)之中；一个第一导电类型接触区(103)作为集电极位于第二导电类型缓冲区(203)之中并且与金属层(501)相连；场氧化层(303)位于第二导电类型阱区(206)的上方，栅电极(401)以及薄介质层(304)位于场氧化层(303)靠近发射极的一侧，并且位于第一导电类型区域(102)的上表面；另一第一导电类型接触区(103)以及第二导电类型接触区(202)位于栅电极(401)远离场氧化层(303)的一侧且与金属层(501)相连；金属层(501)与栅电极(401)通过金属前介质层(305)隔离；
所述第四高压nLDMOS器件(12)，位于包括介质(301)、第一导电类型耐压结构(106)、介质槽(302)、填充物(402)以及第一导电类型注入区(105)的隔离区域内，其中，介质(301)位于衬底(101)中，介质槽(302)位于第一导电类型外延层(104)中并延伸至衬底(101)且与介质(301)相接形成完全隔离，第一导电类型注入区(105)位于介质槽(302)左右两侧，填充物(402)位于介质槽(302)中间，第一导电类型耐压结构(106)位于介质(301)上方，所述第四高压nLDMOS器件(12)还包括：位于第一导电类型外延层(104)中的作为漂移区的第二导电类型阱区(206)；第二导电类型缓冲区(203)作为场阻区位于第二导电类型阱区(206)之中；一个第二导电类型接触区(202)作为漏极位于第二导电类型缓冲区(203)之中并且与金属层(501)相连；场氧化层(303)位于第二导电类型阱区(206)的上方，栅电极(401)以及薄介质层(304)位于场氧化层(303)靠近源极的一侧，并且位于第一导电类型区域(102)的上表面；第一导电类型接触区(103)以及另一第二导电类型接触区(202)位于栅电极(401)远离场氧化层(303)的一侧且与金属层(501)相连；金属层(501)与栅电极(401)通过金属前介质层(305)隔离；
所述第五高压nLDMOS器件(13)，和第四高压nLDMOS器件(12)的差别在于：第二导电类型注入区(207)位于第一导电类型区域(102)的上表面；栅电极(401)以及薄介质层(304)位于第二导电类型注入区(207)上表面；
所述第六高压nLDMOS器件(14)，和第四高压nLDMOS器件(12)的差别在于：第二导电类型阱区(206)的上方没有场氧化层(303)；
所述第二高压pLDMOS器件(15)，位于包括介质(301)、第二导电类型埋层(205)、介质槽(302)、填充物(402)以及第一导电类型注入区(105)的隔离区域内，其中，介质(301)位于衬底(101)中，介质槽(302)位于第一导电类型外延层(104)中并延伸至衬底(101)且与介质(301)相接形成完全隔离，第一导电类型注入区(105)位于介质槽(302)左右两侧，填充物(402)位于介质槽(302)中间，第二导电类型埋层(205)位于介质(301)上方，所述第二高压pLDMOS器件(15)还包括：位于第一导电类型外延层(104)中的作为漏极的一个第一导电类型接触区(103)，并且与金属层(501)相连；栅电极(401)以及薄介质层(304)位于第二导电类型阱区(206)的上表面；场氧化层(303)位于第一导电类型外延层(104)上表面且在第二导电类型阱区(206)与上述第一导电类型接触区(103)之间，另一第一导电类型接触区(103)以及第二导电类型接触区(202)位于栅电极(401)远离场氧化层(303)的一侧且分别与金属层(501)相连；金属层(501)与栅电极(401)通过金属前介质层(305)隔离；
所述第二低压PMOS器件(16)设置在第二导电类型阱区(206)中，第二导电类型阱区(206)位于第一导电类型外延层(104)中，其中第二导电类型接触区(202)和一个第一导电类型接触区(103)分别与金属层(501)相连作为源极，位于第二导电类型阱区(206)内部的一侧，另一第一导电类型接触区(103)与金属层(501)相连作为漏极，位于第二导电类型阱区(206)内部的另一侧栅电极(401)处于薄介质层(304)上、金属前介质层(305)下；栅电极(401)、金属层(501)与栅电极(401)通过金属前介质(305)相互隔离；
所述第二低压NMOS器件(17)设置在第一导电类型区域(102)中，第一导电类型区域(102)位于第一导电类型外延层(104)中，其一个第二导电类型接触区(202)和第一导电类型接触区(103)分别与金属层(501)相连作为源极，位于第一导电类型区域(102)内部的一侧，另一第二导电类型接触区(202)与金属层(501)相连作为漏极，位于第一导电类型区域(102)内部的另一侧；栅电极(401)处于薄介质层(304)上、金属前介质层(305)下；栅电极(401)和金属层(501)通过金属前介质层(305)相互隔离；
所述NPN器件(18)设置在第二导电类型阱区(206)中金属前介质层(305)之下，第二导电类型接触区(202)集电极置于第二导电类型阱区(206)中，第二导电类型接触区(202)发射极与第一导电类型接触区(103)基极位于第一导电类型区域(102)基区中，其中第二导电类型接触区(202)发射极、第二导电类型接触区(202)集电极、第一导电类型接触区(103)基极均与金属层(501)相接；
所述第二PNP器件(19)设置于第一导电类型外延层(104)中、金属前介质层(305)之下，第一导电类型接触区(103)集电极以及发射极分别位于第一导电类型区域(102)中，第二导电类型接触区(202)基极位于第二导电类型阱区(206)基区中，第一导电类型区域(102)也位于第二导电类型阱区(206)中，其中第一导电类型接触区(103)集电极、第一导电类型接触区(103)发射极、第二导电类型区域(202)基极均与金属层(501)相接；
所述第二diode器件(20)设置在第二导电类型阱区(206)中、金属前介质层(305)之下，第一导电类型接触区(103)阳极置于第二导电类型阱区(206)中，第二导电类型接触区(202)阴极位于第二导电类型阱区(206)中，其中第一导电类型接触区(103)阳极、第二导电类型接触区(202)阴极与金属层(501)相接。
17.权利要求16所述的一种BCD半导体器件的制造方法，其特征在于包括以下步骤：
第一步，采用光刻和离子注入工艺，在衬底(101)中注入一定数量的氧离子，退火形成介质(301)；
第二步，采用光刻和离子注入工艺，在衬底(101)中注入第一导电类型杂质；
第三步，外延形成第一导电类型外延层(104)，同时利用此高温退火过程形成介质(301)上方的第一导电类型耐压结构(106)；
第四步，采用光刻和刻蚀工艺，在第一导电类型外延层(104)上电极刻蚀屏蔽层后进行深槽刻蚀，采用斜角注入的方式在深槽的侧壁形成第一导电类型注入区(105)；
第五步，通过热生长的方式在槽侧壁以及第一导电类型外延层(104)上表面生长氧化层，形成介质槽(302)，淀积多晶硅以填充深槽剩余空隙，CMP去掉第二导电类型外延层(201)上表面的多晶硅以及氧化层；
第六步，采用光刻和离子注入工艺，在第一导电类型外延层(104)上以不同的能量分别注入第一导电类型杂质以及第二导电类型杂质，退火形成第一导电类型区域(102)以及第二导电类型阱区(206)；
第七步，光刻出有源区，通过热生长的方式在第一导电类型外延层(104)上表面生长氧化层，形成场氧化层(303)，去掉光刻胶；
第八步，采用光刻和离子注入工艺，在第一导电类型外延层(104)上注入第二导电类型杂质，退火形成第二导电类型缓冲区(203)；热氧生长形成薄介质层(304)，淀积栅电极(401)，光刻；
第九步，光刻以及离子注入，形成第一导电类型接触区(103)以及第二导电类型接触区(202)；
第十步，淀积金属前介质层(305)，打孔后淀积金属层(501)。
18.如权利要求17所述的一种BCD半导体器件的制造方法，其特征在于：第三步与第四步之间添加退火过程以确保形成第一导电类型耐压结构(106)；第六步采用淀积的方法先填充槽，然后再在进行场氧化层的生长。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024825A (zh) * 2010-09-21 2011-04-20 电子科技大学 一种用于负电源电压的薄层soi集成功率器件
CN103337498A (zh) * 2013-05-31 2013-10-02 深圳市联德合微电子有限公司 一种bcd半导体器件及其制造方法
CN107978632A (zh) * 2017-11-30 2018-05-01 电子科技大学 多沟道的横向高压器件

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5156989A (en) * 1988-11-08 1992-10-20 Siliconix, Incorporated Complementary, isolated DMOS IC technology
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CN100578790C (zh) 2008-12-30 2010-01-06 电子科技大学 Bcd半导体器件及其制造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024825A (zh) * 2010-09-21 2011-04-20 电子科技大学 一种用于负电源电压的薄层soi集成功率器件
CN103337498A (zh) * 2013-05-31 2013-10-02 深圳市联德合微电子有限公司 一种bcd半导体器件及其制造方法
CN107978632A (zh) * 2017-11-30 2018-05-01 电子科技大学 多沟道的横向高压器件

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