CN109037030B - Method for preparing epitaxial wafer with improved back silicon single crystal, epitaxial wafer and semiconductor device - Google Patents

Method for preparing epitaxial wafer with improved back silicon single crystal, epitaxial wafer and semiconductor device Download PDF

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CN109037030B
CN109037030B CN201810722379.5A CN201810722379A CN109037030B CN 109037030 B CN109037030 B CN 109037030B CN 201810722379 A CN201810722379 A CN 201810722379A CN 109037030 B CN109037030 B CN 109037030B
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epitaxial wafer
single crystal
epitaxial
silicon single
wafer
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CN109037030A (en
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高璇
陈建纲
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WAFER WORKS EPITAXIAL CORP
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium

Abstract

The invention discloses a preparation method of an epitaxial wafer for improving back silicon single crystal, the epitaxial wafer and a semiconductor device. The epitaxial wafer produced according to the technical scheme of the invention can completely inhibit the growth of monocrystalline silicon points on the back surface of the epitaxial wafer.

Description

Method for preparing epitaxial wafer with improved back silicon single crystal, epitaxial wafer and semiconductor device
Technical Field
The invention relates to a preparation method of an epitaxial wafer for improving back silicon single crystal, the epitaxial wafer and a semiconductor device.
Background
For a semiconductor device, an epitaxial layer is required to have a perfect crystal structure, and certain requirements are required on the thickness, conductivity type, resistivity, resistance uniformity and the like of the epitaxial layer. In addition, the requirement of more and more products on the back surface of the epitaxial wafer is higher and higher, because the requirement directly affects the photoetching processing of the subsequent products, and the defect on the back surface of the epitaxial wafer easily causes the problem of defocusing. Defects on the back surface of the epitaxial wafer include: silicon crystal points on the back surface of the epitaxial wafer, scratches, color differences, etc., which directly affect the subsequent IC process.
Since most epitaxial wafer products are determined by the application of the subsequent products, more and more circuits and electronic elements, such as Power MOS, NMOS, CMOS, Super junction, etc., need to be fabricated on the epitaxial wafer. With the trend of the integrated circuit design towards the narrowing of line width and the higher and higher requirements of the photolithography technology, the requirements for epitaxial products are also demanding. The back sealing structure of the epitaxial wafer is improved, so that the epitaxial wafer is more suitable for more subsequent photoetching processing and becomes a main problem.
As shown in FIG. 1, in the epitaxial wafer, because the substrate is heated at high temperature in the epitaxial process, the silicon dioxide sealed on the back of the edge of the substrate is very easy to react with hydrogen to be reduced into silicon single crystal, and penetrates out of the silicon dioxide layer.
In addition, since the edge of the back side of the wafer needs to be subjected to acid etching to clean the edge and chamfer, the thickness of the silicon dioxide on the edge of the back side of the wafer is correspondingly reduced. Meanwhile, the wafer is heated at high temperature in the epitaxial process, the edge of the wafer slightly tilts and cannot be tightly attached to the bearing disc, and thus, reaction gas hydrogen can permeate into the wafer to react with silicon dioxide to reduce the silicon dioxide into silicon single crystal. In the epitaxial wafer production process, particularly in the vapor phase epitaxy production method, how to avoid the problem that the reaction of hydrogen and silicon dioxide at the edge of the back side of the wafer into a silicon single crystal becomes the difficulty of epitaxial wafer production.
In theory, normal epitaxial wafer production should be very flat to complete. However, the wafer is warped around the wafer to form a U-shaped structure, and if the temperature control is not good, the edge of the wafer warps more, and the silicon single crystal point condition on the back surface of the epitaxial wafer is more serious.
The condition of the back of the epitaxial wafer is also one of the important indexes of the capability of an epitaxial production enterprise, and is a measurement index with high and low process capability. Therefore, improvement of the silicon single crystal phenomenon on the back surface of the epitaxial wafer is a problem to be solved urgently.
Disclosure of Invention
The present invention provides a method for manufacturing an epitaxial wafer with an improved back surface silicon single crystal, an epitaxial wafer, and a semiconductor device.
In order to achieve the above purpose, the invention is realized by the following technical scheme:
a method for preparing an epitaxial wafer for improving back silicon single crystal comprises the steps of firstly covering a layer of polycrystalline silicon on the surface of a bearing disc before an epitaxial layer grows.
According to one embodiment of the invention, the thickness of the polysilicon covered on the surface of the bearing plate is 0.5-1 micron.
According to one embodiment of the invention, the substrate of the epitaxial wafer is doped in an N type and is heavily doped.
According to one embodiment of the invention, the substrate N-type impurity atoms are arsenic atoms.
According to one embodiment of the invention, the doping concentration of the arsenic atoms is 1.2X 1019～2.2×1019 cm-3。
According to one embodiment of the present invention, the substrate is made by a Czochralski single crystal manufacturing process.
According to one embodiment of the invention, a silicon dioxide back seal is arranged on the back surface of the substrate, and the thickness of the silicon dioxide back seal is 4000-5000A.
According to one embodiment of the invention, the epitaxial layer of the epitaxial wafer is doped in an N type and heavily doped.
According to one embodiment of the invention, the N-type is doped with at least one element of phosphorus, arsenic or antimony.
According to one embodiment of the invention, the N-type doping atoms are phosphorus atoms, and the doping concentration of the phosphorus atoms is 5 x 1015～5.5×1015 cm-3。
According to one embodiment of the invention, the epitaxial layer is formed by chemical vapor deposition.
An epitaxial wafer is prepared by the method.
According to one embodiment of the invention, the thickness of the epitaxial layer of the epitaxial wafer is 4-20 microns.
According to one embodiment of the invention, the epitaxial layer has a thickness of 7.5 microns.
A semiconductor device comprises the epitaxial wafer.
Before epitaxial growth, the surface of the bearing disc is covered with a layer of polycrystalline silicon, and a gap between the back edge of the wafer and the bearing disc is sealed, so that hydrogen can not enter the back edge of the wafer, thereby reducing silicon single crystal points and improving the condition. The epitaxial wafer with a better back surface can greatly increase the yield of devices, reduce the process cost and improve the quality of integrated circuit products in the subsequent process. The thickness of the epitaxial layer of the epitaxial wafer is 4-20 microns, and when the thickness of the epitaxial layer exceeds the thickness interval, polycrystalline silicon growing on the bearing disc cannot avoid polycrystalline points growing on the back surface of the wafer. The epitaxial wafer produced according to the technical scheme of the invention can completely inhibit the growth of monocrystalline silicon points on the back surface of the epitaxial wafer.
Drawings
FIG. 1 is a schematic view of a substrate back side edge silicon single crystal of the prior art;
FIG. 2 is a schematic structural diagram of an epitaxial wafer; wherein, 1 is a substrate, 2 is a silicon dioxide back seal, and 3 is an epitaxial layer;
fig. 3 is a schematic structural diagram of the present invention.
Detailed Description
The invention is described in detail below with reference to the attached drawing figures:
example 1
As shown in fig. 3, in the method for manufacturing an improved epitaxial wafer of back silicon single crystal according to this embodiment, before the epitaxial layer grows, a layer of polysilicon 5 is first covered on the surface of the carrier plate 6, and the layer of polysilicon 5 seals the gap between the edge of the back of the epitaxial wafer 4 and the carrier plate 6, so that hydrogen cannot enter the edge of the back of the epitaxial wafer 4 during the epitaxial layer growth, thereby reducing the silicon single crystal points on the back of the epitaxial wafer 4. The thickness of the polysilicon 5 is 0.5 micron.
The substrate of the epitaxial wafer 4 is doped in an N type and is super-doped. The substrate N-type impurity atoms are arsenic atoms. The doping concentration of the arsenic atoms is 1.2 multiplied by 1019 cm-3. The substrate is prepared by a Czochralski single crystal manufacturing method.
As shown in fig. 2, a silicon dioxide back seal is disposed on the back surface of the substrate, and the thickness of the silicon dioxide back seal is 4000 a.
The epitaxial layer of the epitaxial wafer 4 is doped in an N type and heavily doped. The N type is doped with at least one element of phosphorus, arsenic or antimony. The N-type doping atoms are phosphorus atoms, and the doping concentration of the phosphorus atoms is 5 multiplied by 1015 cm-3. The epitaxial layer is prepared by chemical vapor deposition.
The thickness of the epitaxial layer of the epitaxial wafer 4 is 4 microns.
Example 2
As shown in fig. 3, in the method for manufacturing an improved epitaxial wafer of back silicon single crystal according to this embodiment, before the epitaxial layer grows, a layer of polysilicon 5 is first covered on the surface of the carrier plate 6, and the layer of polysilicon 5 seals the gap between the edge of the back of the epitaxial wafer 4 and the carrier plate 6, so that hydrogen cannot enter the edge of the back of the epitaxial wafer 4 during the epitaxial layer growth, thereby reducing the silicon single crystal points on the back of the epitaxial wafer 4. The thickness of the polysilicon 5 is 1 micron.
The above-mentionedThe substrate of the epitaxial wafer 4 is doped in an N type and is super-doped. The substrate N-type impurity atoms are arsenic atoms. The doping concentration of the arsenic atoms is 2.2 multiplied by 1019 cm-3. The substrate is prepared by a Czochralski single crystal manufacturing method.
As shown in fig. 2, a silicon dioxide back seal is disposed on the back surface of the substrate, and the thickness of the silicon dioxide back seal is 5000 a.
The epitaxial layer of the epitaxial wafer 4 is doped in an N type and heavily doped. The N type is doped with at least one element of phosphorus, arsenic or antimony. The N-type doping atoms are phosphorus atoms, and the doping concentration of the phosphorus atoms is 5.5 multiplied by 1015 cm-3. The epitaxial layer is prepared by chemical vapor deposition.
The thickness of the epitaxial layer of the epitaxial wafer 4 is 20 microns.
Example 3
As shown in fig. 3, in the method for manufacturing an improved epitaxial wafer of back silicon single crystal according to this embodiment, before the epitaxial layer grows, a layer of polysilicon 5 is first covered on the surface of the carrier plate 6, and the layer of polysilicon 5 seals the gap between the edge of the back of the epitaxial wafer 4 and the carrier plate 6, so that hydrogen cannot enter the edge of the back of the epitaxial wafer 4 during the epitaxial layer growth, thereby reducing the silicon single crystal points on the back of the epitaxial wafer 4. The thickness of the polysilicon 5 is 0.7 micron.
The substrate of the epitaxial wafer 4 is doped in an N type and is super-doped. The substrate N-type impurity atoms are arsenic atoms. The doping concentration of the arsenic atoms is 2.0 multiplied by 1019 cm-3. The substrate is prepared by a Czochralski single crystal manufacturing method.
As shown in fig. 2, a silicon dioxide back seal is disposed on the back surface of the substrate, and the thickness of the silicon dioxide back seal is 4500 a.
The epitaxial layer of the epitaxial wafer 4 is doped in an N type and heavily doped. The N type is doped with at least one element of phosphorus, arsenic or antimony. The N-type doping atoms are phosphorus atoms, and the doping concentration of the phosphorus atoms is 5.25 multiplied by 1015 cm-3. The epitaxial layer is prepared by chemical vapor deposition.
The thickness of the epitaxial layer of the epitaxial wafer 4 is 7.5 microns.
Table 1 shows the thickness values of the epitaxial layer of the epitaxial wafer, taking five samples, each sample taking nine times and taking an average value, the uniformity being calculated by taking five times on the epitaxial layer of the wafer, and the formula: (max-min)/(max + min):
Figure 96996DEST_PATH_IMAGE001
table 2 shows the resistivity (converted from the doping concentration) of the epitaxial layer of the epitaxial wafer, taking five samples, each taking nine times and taking the average:
Figure 420662DEST_PATH_IMAGE002
the above two tables show that the epitaxial layer prepared according to this example has good thickness and resistance uniformity.
Table 3 shows that the polycrystalline silicon 5 grows on the carrier plate 6, and the thicker the polycrystalline silicon 5 is, the less the silicon single crystal dots are on the back surface of the epitaxial wafer 4. No polycrystalline silicon 5 exists, the back silicon single crystal points are gathered at a distance of 5-10 mm from the edge of the wafer, and the whole circle is very compact; the polycrystalline silicon 5 with the length of 0.5 micron is gathered at the back silicon single crystal point 1-3 m away from the edge of the wafer, and is hardly visible; polysilicon 5 of 1 micron length, the back side silicon single crystal dots are substantially invisible.
TABLE 3
Figure 403661DEST_PATH_IMAGE003
Example 4
The semiconductor device of the present example includes the epitaxial wafer 4 prepared in example 1, 2 or 3.
The embodiments of the present invention are merely illustrative, and not restrictive, of the scope of the claims, and other substantially equivalent alternatives may occur to those skilled in the art and are within the scope of the present invention.

Claims (13)

1. A preparation method of an epitaxial wafer for improving back silicon single crystal is characterized in that before an epitaxial layer grows, a layer of polycrystalline silicon is covered on the surface of a bearing disc; the thickness of the polycrystalline silicon covered on the surface of the bearing disc is 0.5-1 micron; the thickness of the epitaxial layer of the epitaxial wafer is 4-20 microns.
2. The method for preparing an epitaxial wafer with improved back surface silicon single crystal as claimed in claim 1, wherein the substrate of the epitaxial wafer is doped N-type and heavily doped.
3. The method of manufacturing an epitaxial wafer with an improved back side silicon single crystal as claimed in claim 2, wherein the substrate N-type impurity atoms are arsenic atoms.
4. The method of claim 3, wherein the arsenic atoms are doped at a concentration of 1.2X 1019～2.2×1019cm-3。
5. The method of producing an epitaxial wafer with an improved back surface silicon single crystal as claimed in claim 2, 3 or 4, wherein the substrate is produced by Czochralski single crystal manufacturing method.
6. The method for preparing the epitaxial wafer for improving the back surface silicon single crystal according to claim 5, wherein a silicon dioxide back seal is arranged on the back surface of the substrate, and the thickness of the silicon dioxide back seal is 4000-5000A.
7. The method for preparing an epitaxial wafer with an improved back surface silicon single crystal as claimed in claim 1, wherein the epitaxial layer of the epitaxial wafer is doped N-type and heavily doped.
8. The method for producing an epitaxial wafer with improved back surface silicon single crystal as claimed in claim 7, wherein said N type is doped with at least one element selected from phosphorus, arsenic and antimony.
9. The method of claim 8, wherein said N-type dopant atoms are phosphorus atoms having a dopant concentration of 5 x 1015～5.5×1015cm-3。
10. The method for producing an epitaxial wafer with an improved back surface silicon single crystal as claimed in claim 7, 8 or 9, wherein the epitaxial layer is produced by chemical vapor deposition.
11. An epitaxial wafer produced by the method of any one of claims 1 to 10.
12. The epitaxial wafer of claim 11 wherein the epitaxial layer has a thickness of 7.5 microns.
13. A semiconductor device comprising the epitaxial wafer of any one of claims 11 to 12.
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CN202332817U (en) * 2011-09-30 2012-07-11 上海晶盟硅材料有限公司 Epitaxial wafer substrate capable of reducing self-doping in epitaxy process, epitaxial wafer and semiconductor device
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