JPS59165455A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59165455A JPS59165455A JP3954283A JP3954283A JPS59165455A JP S59165455 A JPS59165455 A JP S59165455A JP 3954283 A JP3954283 A JP 3954283A JP 3954283 A JP3954283 A JP 3954283A JP S59165455 A JPS59165455 A JP S59165455A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- high density
- polycrystalline silicon
- high concentration
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 19
- 239000012535 impurity Substances 0.000 abstract description 11
- 239000013078 crystal Substances 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-IGMARMGPSA-N silicon-28 atom Chemical compound [28Si] XUIMIQQOPSSXEZ-IGMARMGPSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置に係シ、特にバイポーラトランジ
スタにおけるコレクタ・シリーズ抵抗の低減化を図るた
めの高濃度層に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to semiconductor devices, and particularly to a highly doped layer for reducing collector series resistance in a bipolar transistor.
通常、ＮＰＮトランノスタにおいては、コレクタ・シリ
ーズ抵抗の低減化を図るために、基板表面から高濃度埋
込み層に達する程深くＮ型の高濃度層（表面濃度；１０
１９〜１０２０ｃｒｎ−３）が形成される。Normally, in an NPN trannostar, in order to reduce the collector series resistance, an N-type heavily doped layer (surface concentration: 10
19-1020crn-3) is formed.
従来、この高濃度層は熱拡散によシ形成されている。す
なわち、例えばｐｏｃｔ３（オキシ塩化リン）等の高濃
度Ｎ＋材料を約９００〜１１００℃の温度でシリコン基
板上に堆積し、その後９００〜１２００℃の温度の窒素
雰囲気中でスランビング処理を行うものである。Conventionally, this high concentration layer is formed by thermal diffusion. That is, for example, a high concentration N+ material such as POC 3 (phosphorus oxychloride) is deposited on a silicon substrate at a temperature of about 900 to 1100°C, and then a slumping process is performed in a nitrogen atmosphere at a temperature of 900 to 1200°C. .
〔背景技術の問題点〕 ／しかしながら
、この従来方法では、高濃度不純物を高温で拡散処理す
るために高濃度層の近傍に結晶欠陥を誘発してしまう。[Problems with Background Art] /However, in this conventional method, crystal defects are induced in the vicinity of the high concentration layer because the high concentration impurity is diffused at high temperature.
この結晶欠陥が発生すると、高濃度層とペース層との間
でリーク電流が増大し、素子の耐圧が劣化することにな
る。この結晶欠陥は特に素子の微細化に対して重大な悪
影響を及ぼすもので、このため製品の歩留りが低下する
。このような結晶欠陥の発生を防止するには、拡散不純
物の濃度を低下させればよいが、これではコレクタ・シ
リーズ抵抗の低減化を図ることができなくなる。When these crystal defects occur, leakage current increases between the high concentration layer and the paste layer, and the withstand voltage of the device deteriorates. These crystal defects particularly have a serious adverse effect on the miniaturization of elements, and therefore reduce the yield of products. Although the occurrence of such crystal defects can be prevented by lowering the concentration of the diffused impurity, it is no longer possible to reduce the collector series resistance.
この発明は上記実情に鑑みてなされたもので、その目的
は、結晶欠陥の発生を防止し、かつコレクタ・シリ−・
ズ抵抗の低減化を図ることのできる半導体装置を提供す
ることにある。This invention was made in view of the above circumstances, and its purpose is to prevent the occurrence of crystal defects, and to prevent the collector series from occurring.
An object of the present invention is to provide a semiconductor device that can reduce the current resistance.
この発明は、半導体基板上のバイポーラトランジスタが
形成された島領域において、その表面から高濃度埋込み
層に達する溝を形成し、この溝に例えば高濃度不純物を
含む多結晶シリコンを堆積して、この高濃度多結晶シリ
コン層により、コレクタ・シリーズ抵抗の低減化を図る
もので、高温の熱処理や高濃度不純物の拡散処理が不要
である。In the present invention, a groove is formed in an island region on a semiconductor substrate in which a bipolar transistor is formed, and a trench is formed from the surface of the island region to a high concentration buried layer, and polycrystalline silicon containing a high concentration of impurities is deposited in the trench. The high-concentration polycrystalline silicon layer reduces collector series resistance, eliminating the need for high-temperature heat treatment or high-concentration impurity diffusion treatment.
以下、図面を参照してこの発明の一実施例を説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図（、）は、例えばＰ型のシリコン基板１１上にＮ
＋高濃度埋込み層１２及び戸高濃度埋込み層１３．１４
を拡散形成し、その上にエピタキシャル層１５を成長さ
せ、さらにこのエピタキシャル層１５上に酸化膜（Ｓｉ
Ｏ□）１６を形成した状態を示したものである。ここで
、エピタキシャル層１５′の厚さは５μｎＢＱ抵抗は１
．５〜２．００・ｃｍ−’とする。この状態から素子分
離領域を形成するために、第２図（ｂ）に示すように写
真蝕刻法を用いて所定の領域の酸化膜１６をエツチング
し、開口１７．１８を形成する。In FIG. 1(,), for example, N is placed on a P-type silicon substrate 11.
+High concentration buried layer 12 and high concentration buried layer 13.14
is diffused, an epitaxial layer 15 is grown thereon, and an oxide film (Si
This figure shows the state in which O□) 16 is formed. Here, the thickness of the epitaxial layer 15' is 5 μn, and the BQ resistance is 1
．． 5 to 2.00 cm-'. In order to form an element isolation region from this state, as shown in FIG. 2(b), the oxide film 16 in a predetermined region is etched using photolithography to form openings 17 and 18.
その後、第１図（Ｃ）に示すように、開口１７゜１８を
通してＰ型不純物例えばボロンを選択的に拡散し素子分
離領域１９．２０を形成する。Thereafter, as shown in FIG. 1C, P-type impurities such as boron are selectively diffused through the openings 17 and 18 to form element isolation regions 19 and 20.
なお、この分離方法は酸化膜分離のような他の方法でも
可能である。次に、第１図（ｄ）に示すようにコレクタ
・シリーズ抵抗低減化のだめの高濃度層形成予定領域の
酸化膜１６を写真蝕刻法によシ選択的にエツチングして
開口を形成する。Note that this separation method can also be performed using other methods such as oxide film separation. Next, as shown in FIG. 1(d), an opening is formed by selectively etching the oxide film 16 in a region where a high concentration layer for reducing collector series resistance is to be formed by photolithography.
引き続き、反応性イオンエツチング技術を用いて、水素
（Ｈ２）と塩素（Ｃｔ３）との混合ガス中でプラズマを
発生させ、シリコン基板１１を選択的にエツチングして
溝２１を形成する。この選択エツチングにはレジスト材
料をマスクとして使用する。溝２ノの深さはエピタキシ
ャル層１５の厚、さと略同じとし、Ｎ＋高濃度埋込み層
１２に達するように深く形成するものとする。Subsequently, using reactive ion etching technology, plasma is generated in a mixed gas of hydrogen (H2) and chlorine (Ct3), and the silicon substrate 11 is selectively etched to form the grooves 21. A resist material is used as a mask for this selective etching. The depth of the trench 2 is approximately the same as the thickness of the epitaxial layer 15, and is formed deep enough to reach the N+ heavily doped buried layer 12.
次に、第１図（、）に示すように、例えばＣＶＤ（（Ｊ
６ｍｉｃａｌ″Ｖａｐｏｕｒ Ｄｅｐｏｓｉｔｉｏｎ
）法によシリコン基板１１上に高濃度のＮ型不純物を添
加した多結晶シリコンを堆積させ、所望の厚さの高濃度
多結晶シリコン層２２を形成する。すなわちへ００〜７
００℃の温度で、５ＩＨ４（シラン）ガスとドーピング
ガ゛ス（例えば、ＰＨ３１ＡＳＨ３）を同時に流して熱
分解させることにより、高濃度多結晶シリコン層２２を
形成するものである。Next, as shown in FIG. 1(,), for example, CVD ((J
6mical"Vapour Deposition
) polycrystalline silicon doped with a high concentration of N-type impurity is deposited on the silicon substrate 11 by the method to form a high concentration polycrystalline silicon layer 22 with a desired thickness. i.e. to 00-7
The highly concentrated polycrystalline silicon layer 22 is formed by simultaneously flowing 5IH4 (silane) gas and doping gas (for example, PH31ASH3) at a temperature of 0.000C to cause thermal decomposition.
その後、この溝２１内に埋込壕れだ高濃度多結晶シリコ
ン層２２を電気的に活性化させるために熱処理を施す。Thereafter, a heat treatment is performed to electrically activate the heavily doped polycrystalline silicon layer 22 buried in the trench 21.
第２図は上記高濃度多結晶シリコン層２２を加工した後
、ＮＰＮ）ランジスタのＰ層（ペース）２３及び１層（
エミッタ）２４を形成し、さらにペース電極２５、エミ
ッタ電極２６及びコレクタ電極２７をそれぞれ形成した
ものである。FIG. 2 shows the P layer (paste) 23 and the first layer (
In addition, a pace electrode 25, an emitter electrode 26, and a collector electrode 27 are formed.
第１図（、）の工程において、高濃度多結晶シリコン層
２２の形成は、第３図に示すようにＰ層（ペース）２３
を形成した後、エミッタ拡散の拡散材料として利用する
高濃度多結晶シリコン２８の形成と同様に行うようにし
てもよい。In the process shown in FIG. 1(,), the formation of the high concentration polycrystalline silicon layer 22 is performed using a P layer (paste) 23 as shown in FIG.
After forming, the process may be performed in the same manner as the formation of high concentration polycrystalline silicon 28 used as a diffusion material for emitter diffusion.
このようにして形成されたバイポーラトランジスタにお
いては、溝２１の内部に高濃度多結晶シリコン層２２が
埋め込まれているために、コレクタ・シリーズ抵抗の低
減化を図ることができる。また、この高濃度多結晶シリ
コン層２２の形成には高濃度不純物の拡散や高温の熱処
理が不要であるため、結晶欠陥の発生を防止することが
できる。従って、リーク電流の増大、素子の耐圧劣化を
防止することができ、このため高濃度多結晶シリコン層
２２をＰ層（ペース）２３に近接して形成することがで
き、集積度が向上すると共に製品の製造歩留りが向上す
る。In the bipolar transistor thus formed, since the highly concentrated polycrystalline silicon layer 22 is embedded inside the groove 21, the collector series resistance can be reduced. Further, since the formation of this highly concentrated polycrystalline silicon layer 22 does not require diffusion of highly concentrated impurities or high temperature heat treatment, it is possible to prevent crystal defects from occurring. Therefore, it is possible to prevent an increase in leakage current and a deterioration in the withstand voltage of the element. Therefore, the high concentration polycrystalline silicon layer 22 can be formed close to the P layer (paste) 23, and the degree of integration is improved. Product manufacturing yield is improved.
具体的には、従来、６０〜７０チであった製造品（ａで
示す）と本発明による製品（ｂで示す）とを比較して示
すものである。ここで、測定条件はＲｇ＝ １０ ｋΩ
、■。＝５００μＡとしている。同図によれば、従来製
品と比較して本発明による製品が良好な特性を示すこと
がわかる。Specifically, the figure shows a comparison between a conventional manufactured product (indicated by a) having a size of 60 to 70 inches and a product according to the present invention (indicated by b). Here, the measurement conditions are Rg = 10 kΩ
,■. =500μA. According to the figure, it can be seen that the product according to the present invention exhibits better characteristics than the conventional product.
尚、上記実施例においては、高濃度多結晶シリコン層２
２をＣＶＤ法により形成するようにしだが、その他プラ
ズマ励起による方法、スパッタリング方法を用いてもよ
く、さらにはＣＶＤ法により多結晶シリコンを堆積した
後に不純物のイオン注入を行う方法によっても形成する
ことができる。また、上記実施例においては、溝２１内
に高濃度多結晶シリコン層２２を形成するようにしたが
、これに限定するものではなく、高濃度多結晶シリコン
層２２の代シに金属（Ａｔ、 ＡＡ合金、 Ｍｏ 、
Ｍｏ５ｔ 、 Ｐｔ 、 Ｔｉ 、 ＴｉＮ。In the above embodiment, the highly concentrated polycrystalline silicon layer 2
2 is formed by the CVD method, but other methods such as plasma excitation, sputtering, or even impurity ion implantation after depositing polycrystalline silicon by the CVD method may also be used. can. Further, in the above embodiment, the high concentration polycrystalline silicon layer 22 is formed in the groove 21, but the invention is not limited to this, and instead of the high concentration polycrystalline silicon layer 22, metal (At, AA alloy, Mo,
Mo5t, Pt, Ti, TiN.
ＴＩＷ等）をＣＶＤ法、スクリーンプリンタ法等により
堆積するようにしてもよい。TIW, etc.) may be deposited by a CVD method, a screen printer method, or the like.
以上のようにこの発明によれば、結晶欠陥の発生を防止
することができるため、リーク電流の増大及び素子の耐
圧劣化を防止して集積度を向上させることができると共
にコレクタ・シリーズ抵抗の低減化を図ることが容易と
なる。As described above, according to the present invention, since it is possible to prevent the occurrence of crystal defects, it is possible to prevent an increase in leakage current and a deterioration of the breakdown voltage of elements, thereby improving the degree of integration, and reducing collector series resistance. This makes it easier to promote
第１図（、）〜（、）はこの発明の一実施例に係る半導
体装置の製造工程を示す断面図、第２図及び指数を従来
製品と本発明による製品とを比較して示す特性図である
。
１１・・・シリコン基板、１２・・・Ｎ＋高濃度埋込み
層、１５・・・エピタキシャル層、１９．２０・・・素
子分離領域、２１・・・溝、−２２・・・高濃度多結晶
シリコン層、２３・・・Ｐ！（ペース）、２４・・・Ｎ
＋層（エミッタ）。
出願人代理人 弁理士 鈴 江 武 彦第１図
１６
第１図
１
第２図FIG. 1 (,) to (,) are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a characteristic diagram showing a comparison of indexes between a conventional product and a product according to the present invention. It is. DESCRIPTION OF SYMBOLS 11... Silicon substrate, 12... N+ high concentration buried layer, 15... Epitaxial layer, 19.20... Element isolation region, 21... Groove, -22... High concentration polycrystalline silicon Layer, 23...P! (pace), 24...N
+ layer (emitter). Applicant's agent Patent attorney Takehiko Suzue Figure 1 16 Figure 1 1 Figure 2
Claims (1)
れた第二導電型の半導体層と、この半導体層に形成され
た島領域と、この島領域に形成された能動層と、この能
動層の下部に形成された第二導電型の高濃度埋込み層と
、前記半導体基板の表面から前記高濃度埋込み層に達す
るように形成された溝と、この溝の内部に堆積された導
電層とを具備したことを特徴とする半導体装置。A semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on this semiconductor substrate, an island region formed in this semiconductor layer, an active layer formed in this island region, and a semiconductor layer of a second conductivity type formed on this semiconductor substrate. a second conductivity type high concentration buried layer formed at the bottom of the layer; a groove formed to reach the high concentration buried layer from the surface of the semiconductor substrate; and a conductive layer deposited inside the groove. A semiconductor device characterized by comprising:
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3954283A JPS59165455A (en) | 1983-03-10 | 1983-03-10 | Semiconductor device |
| GB08405871A GB2137019A (en) | 1983-03-10 | 1984-03-06 | Semiconductor Device and Method for Manufacturing |
| DE19843408552 DE3408552A1 (en) | 1983-03-10 | 1984-03-08 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3954283A JPS59165455A (en) | 1983-03-10 | 1983-03-10 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59165455A true JPS59165455A (en) | 1984-09-18 |
Family
ID=12555937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3954283A Pending JPS59165455A (en) | 1983-03-10 | 1983-03-10 | Semiconductor device |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPS59165455A (en) |
| DE (1) | DE3408552A1 (en) |
| GB (1) | GB2137019A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166071A (en) * | 1985-01-17 | 1986-07-26 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS63215068A (en) * | 1987-03-04 | 1988-09-07 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
| JPH04123076U (en) * | 1991-04-24 | 1992-11-06 | 船井電機株式会社 | parallel jumper wire |
| KR20190019191A (en) * | 2016-06-23 | 2019-02-26 | 리텔퓨즈 인코퍼레이티드 | Semiconductor device having side-diffusion trench plug |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2181889A (en) * | 1985-10-19 | 1987-04-29 | Plessey Co Plc | Improvements relating to bipolar transistors |
| DE69132730T2 (en) * | 1990-05-31 | 2002-07-04 | Canon Kk | Semiconductor arrangement with improved wiring |
| GB9013926D0 (en) * | 1990-06-22 | 1990-08-15 | Gen Electric Co Plc | A vertical pnp transistor |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA928863A (en) * | 1970-01-19 | 1973-06-19 | Rca Corporation | Semiconductor integrated circuit device |
| DE2106540A1 (en) * | 1970-02-13 | 1971-08-19 | Texas Instruments Inc | Semiconductor circuits and processes for their manufacture |
| US3847687A (en) * | 1972-11-15 | 1974-11-12 | Motorola Inc | Methods of forming self aligned transistor structure having polycrystalline contacts |
| US3913124A (en) * | 1974-01-03 | 1975-10-14 | Motorola Inc | Integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector including fabrication method therefor |
| GB1534896A (en) * | 1975-05-19 | 1978-12-06 | Itt | Direct metal contact to buried layer |
-
1983
- 1983-03-10 JP JP3954283A patent/JPS59165455A/en active Pending
-
1984
- 1984-03-06 GB GB08405871A patent/GB2137019A/en not_active Withdrawn
- 1984-03-08 DE DE19843408552 patent/DE3408552A1/en not_active Ceased
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61166071A (en) * | 1985-01-17 | 1986-07-26 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS63215068A (en) * | 1987-03-04 | 1988-09-07 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
| JPH04123076U (en) * | 1991-04-24 | 1992-11-06 | 船井電機株式会社 | parallel jumper wire |
| KR20190019191A (en) * | 2016-06-23 | 2019-02-26 | 리텔퓨즈 인코퍼레이티드 | Semiconductor device having side-diffusion trench plug |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2137019A (en) | 1984-09-26 |
| GB8405871D0 (en) | 1984-04-11 |
| DE3408552A1 (en) | 1984-09-20 |
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