CN108964444A - 电荷泵电路及电荷泵单元 - Google Patents
电荷泵电路及电荷泵单元 Download PDFInfo
- Publication number
- CN108964444A CN108964444A CN201710687034.6A CN201710687034A CN108964444A CN 108964444 A CN108964444 A CN 108964444A CN 201710687034 A CN201710687034 A CN 201710687034A CN 108964444 A CN108964444 A CN 108964444A
- Authority
- CN
- China
- Prior art keywords
- type transistor
- charge pump
- coupled
- clock signal
- pump unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 90
- 230000005611 electricity Effects 0.000 claims description 10
- 240000002853 Nelumbo nucifera Species 0.000 claims description 4
- 235000006508 Nelumbo nucifera Nutrition 0.000 claims description 4
- 235000006510 Nelumbo pentapetala Nutrition 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 230000035755 proliferation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 101150070189 CIN3 gene Proteins 0.000 description 7
- 101150110971 CIN7 gene Proteins 0.000 description 7
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 7
- 101150110298 INV1 gene Proteins 0.000 description 7
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 7
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 7
- 101100508840 Daucus carota INV3 gene Proteins 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000003860 storage Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
- G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/18—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
- H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0042—Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/4013—Memory devices with multiple cells per bit, e.g. twin-cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0041—Control circuits in which a clock signal is selectively enabled or disabled
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/159—Applications of delay lines not covered by the preceding subgroups
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Nonlinear Science (AREA)
- Read Only Memory (AREA)
- Dc-Dc Converters (AREA)
- Semiconductor Memories (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
本发明公开了一种电荷泵电路,电荷泵电路包括第一电荷泵单元及第二电荷泵单元。第一电荷泵单元根据第一时钟信号、第二时钟信号及第三时钟信号抬升输入电压以输出第一抬升电压。第二电荷泵单元根据第一时钟信号、第四时钟信号及第三时钟信号抬升第一抬升电压以输出第二抬升电压。第一时钟信号及第三时钟信号为非重迭的两个时钟信号。第二时钟信号的负缘领先第一时钟信号的正缘。第四时钟信号的负缘领先第三时钟信号的正缘。
Description
技术领域
本发明是有关于一种电荷泵电路,特别是指一种低逆向电流的电荷泵电路。
背景技术
基于电子产品对低耗电的需求,集成电路的电力规格也被重新设计成能够在低电压的环境下操作以节省电能消耗。举例来说,先前集成电路的电力规格常为5V,现今则大多改为3.3V或甚至低于2V。虽然低电压可用来减少电能消耗,然而在某些情况下仍会需要较大的电压。举例来说,闪存的写入或清除操作就需要较大的电压来完成。较大的电压通常可利用电荷泵电路来提供。
现有技术的电荷泵电路常由不同的时钟信号控制。然而,由于时钟信号并非完美的方波,因此在时钟信号的电压变换期间,电荷泵中的开关可能会被不预期地导通或截止。在这种情况下,多余的逆向电流就可能产生,进而增加电能的耗损。
发明内容
本发明的一实施例提供一种电荷泵电路。电荷泵电路包括第一电荷泵单元及第二电荷泵单元。第一电荷泵单元接收输入电压、第一时钟信号、第二时钟信号及第三时钟信号,并根据第一时钟信号、第二时钟信号及第三时钟信号抬升输入电压以输出第一抬升电压。第二电荷泵单元耦接于第一电荷泵单元。第二电荷泵单元接收第一抬升电压、第一时钟信号、第四时钟信号及第三时钟信号,并根据第一时钟信号、第四时钟信号及第三时钟信号抬升第一抬升电压以输出第二抬升电压。
第一时钟信号及第三时钟信号为非重迭的两个时钟信号。第二时钟信号的负缘领先第一时钟信号的正缘,接续在第二时钟信号的负缘之后的第二时钟信号的正缘领先接续在第一时钟信号的正缘之后的第一时钟信号的负缘。第四时钟信号的负缘领先第三时钟信号的正缘,接续在第四时钟信号的负缘之后的第四时钟信号的正缘领先接续在第三时钟信号的正缘之后的第三时钟信号的负缘。
本发明的另一实施例提供一种电荷泵电路。电荷泵电路包括电压输入端口、电压输出端口及M个电荷泵单元。
M个电荷泵单元中的第i电荷泵包括输入端、输出端、第一N型晶体管、第二N型晶体管、第三N型晶体管、第一电容、第一P型晶体管、第二P型晶体管、第二电容及第三电容。
第一N型晶体管具有耦接于第i电荷泵单元的输入端的第一端,第二端,及控制端。第二N型晶体管具有耦接于第i电荷泵单元的输入端的第一端,耦接于第i电荷泵单元的第一N型晶体管的控制端的第二端,及耦接于第i电荷泵单元的第一N型晶体管的第二端的控制端。第三N型晶体管具有耦接于第i电荷泵单元的输入端的第一端,耦接于第i电荷泵单元的第一N型晶体管的第二端的第二端,及耦接于第i电荷泵单元的第三N型晶体管的第一端的控制端。第一电容具有接收第一时钟信号的第一端,及耦接于第i电荷泵单元的第一N型晶体管的第二端的第二端。第一P型晶体管具有耦接于第i电荷泵单元的第一N型晶体管的第二端的第一端,耦接于第i电荷泵单元的输出端的第二端,控制端,及耦接于第i电荷泵单元的第一P型晶体管的第二端的基极端。第二P型晶体管具有耦接于第i电荷泵单元的第一P型晶体管的控制端的第一端,耦接于第i电荷泵单元的输出端的第二端,耦接于第i电荷泵单元的第一P型晶体管的第一端的控制端,及耦接于第i电荷泵单元的第二P型晶体管的第二端的基极端。第二电容具有接收第二时钟信号的第一端,及耦接于第i电荷泵单元的第一P型晶体管的控制端的第二端。第三电容具有接收第三时钟信号的第一端,及耦接于第i电荷泵单元的第一N型晶体管的控制端的第二端。
M个电荷泵单元中的第(i+1)电荷泵包括输入端、输出端、第一N型晶体管、第二N型晶体管、第三N型晶体管、第一电容、第一P型晶体管、第二P型晶体管、第二电容及第三电容。
第(i+1)电荷泵的输入端耦接于第i电荷泵单元的输出端。第一N型晶体管具有耦接于第(i+1)电荷泵单元的输入端的第一端,第二端,及控制端。第二N型晶体管具有耦接于第(i+1)电荷泵单元的输入端的第一端,耦接于第(i+1)电荷泵单元的第一N型晶体管的控制端的第二端,及耦接于第(i+1)电荷泵单元的第一N型晶体管的第二端的控制端。第三N型晶体管具有耦接于第(i+1)电荷泵单元的输入端的第一端,耦接于第(i+1)电荷泵单元的第一N型晶体管的第二端的第二端,及耦接于第(i+1)电荷泵单元的第三N型晶体管的第一端的控制端。第一电容具有接收第三时钟信号的第一端,及耦接于第(i+1)电荷泵单元的第一N型晶体管的第二端的第二端。第一P型晶体管具有耦接于第(i+1)电荷泵单元的第一N型晶体管的第二端的第一端,耦接于第(i+1)电荷泵单元的输出端的第二端,控制端,及耦接于第(i+1)电荷泵单元的第一P型晶体管的第二端的基极端。第二P型晶体管具有耦接于第(i+1)电荷泵单元的第一P型晶体管的控制端的第一端,耦接于第(i+1)电荷泵单元的输出端的第二端,耦接于第(i+1)电荷泵单元的第一P型晶体管的第一端的控制端,及耦接于第(i+1)电荷泵单元的第二P型晶体管的第二端的基极端。第二电容具有接收第四时钟信号的第一端,及耦接于第(i+1)电荷泵单元的第一P型晶体管的控制端的第二端。第三电容具有接收第一时钟信号的第一端,及耦接于第(i+1)电荷泵单元的第一N型晶体管的控制端的第二端。
M是为大于1的正整数,i是为小于M的正整数。第一时钟信号及第三时钟信号为非重迭的两个时钟信号。
附图说明
图1为本发明一实施例的电荷泵电路的示意图。
图2为图1的时钟信号及第一电容之端电压的波型图。
图3为本发明一实施例的时钟信号产生电路的示意图。
图4为本发明另一实施例的时钟信号产生电路的示意图。
图5为本发明另一实施例的电荷泵电路的示意图。
其中,附图标记说明如下:
10、20 电荷泵电路
1001、1002、100i、100(i+1)、100M 电荷泵单元
VIN 电压输入端口
VOUT 电压输出端口
110A、110B 基极开关
N1A、N1B 第一N型晶体管
N2A、N2B 第二N型晶体管
N3A、N3B 第三N型晶体管
N4A、N4B 第四N型晶体管
N5A、N5B 第五N型晶体管
N6A、N6B 第六N型晶体管
N7A、N7B 第七N型晶体管
P1A、P1B 第一P型晶体管
P2A、P2B 第二P型晶体管
C1A、C1B 第一电容
C2A、C2B 第二电容
C3A、C3B 第三电容
INA、INB 输入端
OUTA、OUTB 输出端
SIGCLK1 第一时钟信号
SIGCLK2 第二时钟信号
SIGCLK3 第三时钟信号
SIGCLK4 第四时钟信号
SIGctrl 控制信号
Vbias 偏压电压
VDD 第一电压
VSS 第二电压
VBSTA、VBSTB 端电压
120A、120B 放电电路
130 ***电压端
2VDD 第三电压
3VDD 第四电压
TA、TB、TC、T1至T8 时段
RECLK1、RECLK2、RECLK3、RECLK4 正缘
FECLK1、FECLK2、FECLK3、FECLK4 负缘
12、22 时钟产生电路
CG 非重迭时钟产生器
CLK 时钟输入端
SIGCLK0 主要时钟信号
SIGCLKA 第一中介时钟信号
SIGCLKB 第二中介时钟信号
INV1 第一逆变器
INV2 第二逆变器
INV3 第三逆变器
INV4 第四逆变器
DE1 第一延迟组件
DE2 第二延迟组件
具体实施方式
图1为本发明一实施例之电荷泵电路10的示意图。电荷泵电路10包括电压输入端口VIN、电压输出端口VOUT、第一电荷泵单元1001及第二电荷泵单元1002。第一电荷泵单元1001及第二电荷泵单元1002可具有相同的结构但可接收相异的信号。
第一电荷泵单元1001包括输入端INA、输出端OUTA、第一N型晶体管N1A、第二N型晶体管N2A、第三N型晶体管N3A、第一P型晶体管P1A、第二P型晶体管P2A、第一电容C1A、第二电容C2A及第三电容C3A。
输入端INA耦接于电压输入端口VIN以接收第一电压VDD作为其输入电压。第一N型晶体管N1A具有第一端、第二端及控制端,第一N型晶体管N1A的第一端耦接于输入端INA。第二N型晶体管N2A具有第一端、第二端及控制端,第二N型晶体管N2A的第一端耦接于输入端INA,第二N型晶体管N2A的第二端耦接于第一N型晶体管N1A的控制端,而第二N型晶体管N2A的控制端耦接于第一N型晶体管N1A的第二端。
第三N型晶体管N3A具有第一端、第二端及控制端,第三N型晶体管N3A的第一端耦接于输入端INA,第三N型晶体管N3A的第二端耦接于第一N型晶体管N1A的第二端,而第三N型晶体管N3A的控制端耦接于第三N型晶体管N3A的第一端。此外,第三N型晶体管N3A的基极端可耦接于,但不限于,第一N型晶体管N1A的基极端。
第一P型晶体管P1A具有第一端、第二端、控制端及基极端,第一P型晶体管P1A的第一端耦接于第一N型晶体管N1A的第二端,第一P型晶体管P1A的第二端耦接于输出端OUTA,而第一P型晶体管P1A的基极端耦接于第一P型晶体管P1A的第二端。
第二P型晶体管P2A具有第一端、第二端、控制端及基极端,第二P型晶体管P2A的第一端耦接于第一P型晶体管P1A的控制端,第二P型晶体管P2A的第二端耦接于输出端OUTA,第二P型晶体管P2A的控制端耦接于第一P型晶体管P1A的第一端,而第二P型晶体管P2A的基极端耦接于第二P型晶体管P2A的第二端。
第一电容C1A具有第一端及第二端,第一电容C1A的第一端可接收第一时钟信号SIGCLK1,而第一电容C1A的第二端耦接于第一N型晶体管N1A的第二端。第二电容C2A,具有第一端及第二端,第二电容C2A的第一端可接收第二时钟信号SIGCLK2,而第二电容C2A的第二端耦接于第一P型晶体管P1A的控制端。第三电容C3A具有第一端及第二端,第三电容C3A的第一端可接收第三时钟信号SIGCLK3,而第三电容C3A的第二端耦接于第一N型晶体管N1A的控制端。
第二电荷泵单元1002可与第一电荷泵单元1001具有相同的结构。也就是说,第二电荷泵单元1002可包括输入端INB、输出端OUTB、第一N型晶体管N1B、第二N型晶体管N2B、第三N型晶体管N3B、第一P型晶体管P1B、第二P型晶体管P2B、第一电容C1B、第二电容C2B及第三电容C3B。第二电荷泵单元1002的输入端INB可耦接于第一电荷泵单元1001的输出端OUTA。再者,第一电容C1B的第一端可接收第三时钟信号SIGCLK3,第二电容C2B的第一端可接收第四时钟信号SIGCLK4,而第三电容C3B的第一端可接收第一时钟信号SIGCLK1。此外,第三N型晶体管N3B的基极端可耦接于,但不限于,第一N型晶体管N1B的基极端。
图2为本发明一实施例的第一时钟信号SIGCLK1、第二时钟信号SIGCLK2、第三时钟信号SIGCLK3、第四时钟信号SIGCLK4、第一电容C1A的第二端的端电压VBSTA及第一电容C1B的第二端的端电压VBSTB的波型图。
在图2中,第一时钟信号SIGCLK1及第三时钟信号SIGCLK3为非重迭的两个时钟信号,也就是说,第一时钟信号SIGCLK1及第三时钟信号SIGCLK3会在不同的时点切换电位。更进一步说,当第一时钟信号SIGCLK1为第一电压VDD时,第三时钟信号SIGCLK3为较第一电压VDD低的第二电压VSS,且当第三时钟信号SIGCLK3为第一电压VDD时,第一时钟信号SIGCLK1为较第一电压VDD低的第二电压VSS。
再者,第二时钟信号SIGCLK2的负缘FECLK2会领先第一时钟信号SIGCLK1的正缘RECLK1,而接续在第二时钟信号SIGCLK2的负缘FECLK2之后的第二时钟信号SIGCLK2的正缘RECLK2领先接续在第一时钟信号SIGCLK1的正缘RECLK1之后的第一时钟信号SIGCLK1的负缘FECLK1。
并且,第四时钟信号SIGCLK4的负缘FECLK4会领先第三时钟信号SIGCLK3的正缘RECLK3,而接续在第四时钟信号SIGCLK4的负缘FECLK4之后的第四时钟信号SIGCLK4的正缘RECLK4会领先接续在第三时钟信号SIGCLK3的正缘
RECLK3之后的第三时钟信号SIGCLK3的负缘FECLK3。
图2所示的波型图是在电荷泵电路10已进入稳定输出抬升电压的情况下所撷取的。然而,在第一电荷泵单元1001的初始操作中,当第一时钟信号SIGCLK1为第二电压VSS时,第三N型晶体管N3A可将第一电容C1A的第二端充电至相当于VDD-Vthn的电压,其中Vthn为第三N型晶体管N3A的临界电压,使得第一电荷泵单元1001能够快速进入稳定阶段并进行后续操作。
为方便理解电荷泵单元1001及1002在时段T1至T8的操作,可先观察第一电荷泵单元1001自时段TA至TC的操作。
在时段TA,第一时钟信号SIGCLK1为第一电压VDD,第二时钟信号
SIGCLK2为第二电压VSS,而第三时钟信号SIGCLK3为第二电压VSS。由于第一电容C1A的第二端在第一时钟信号SIGCLK1为第二电压VSS时,就已经被充电至第一电压VDD,因此当第一时钟信号SIGCLK1变为第一电压VDD时,第一电容C1A的第二端电压将被提升至第三电压2VDD。因此,第二N型晶体管N2A将被导通,而第三电容C3A的第二端会在时段TA中,经由第二N型晶体管N2A被充电至第一电压VDD。
第二时钟信号SIGCLK2在时段TB变为第一电压VDD,而第一时钟信号SIGCLK1在时段TC变为第二电压VSS。因此在时段TB及TC中,第一P型晶体管P1A将被截止,接着第二P型晶体管P2A将被导通,而第一电荷泵单元1001可停止将内部储存的电荷分享给第二电荷泵单元1002。
在时段T1,第三时钟信号SIGCLK3变为第一电压VDD,第一时钟信号SIGCLK1为第二电压VSS,而第二时钟信号SIGCLK2为第一电压VDD。由于在先前第三时钟信号SIGCLK3仍为第二电压VSS时,第三电容C3A的第二端已被充电至第一电压VDD,因此当第三时钟信号SIGCLK3自第二电压VSS变为第一电压VDD时,第三电容C3A的第二端将被抬升至第三电压2VDD,亦即两倍的第一电压VDD。
如此一来,第一N型晶体管N1A将被导通,而第一电容C1A的第二端也将随着第一时钟信号SIGCLK1变为第二电压VSS而被充电至第一电压
VDD。在此情况下,第二P型晶体管P2A可被导通,而第二电容C2A的第二端可处于第三电压2VDD,使得第一P型晶体管P1A被截止。也就是说,在时段T1中,第一电荷泵单元1001会对第一电容C1A充电,且不会将储存的电荷分享给第二电荷泵单元1001。
在时段T2中,第三时钟信号SIGCLK3变为第二电压VSS,而第一时钟信号SIGCLK1、第二时钟信号SIGCLK2及第四时钟信号SIGCLK4则维持前一时段T1的电位。因此,第一N型晶体管N1A会被截止。由于没有周围没有可放电的路径,因此第一电容C1A的第二端的端电压VBSTA保持在第一电压VDD。
在时段T3中,第二时钟信号SIGCLK2变为第二电压VSS,而第一时钟信号SIGCLK1、第三时钟信号SIGCLK3及第四时钟信号SIGCLK4则维持前一时段T2的电位。在时段T4中,第一时钟信号SIGCLK1变为第一电压VDD,而第二时钟信号SIGCLK2、第三时钟信号SIGCLK3及第四时钟信号SIGCLK4则维持前一时段T3的电位。也就是说,在端电压VBSTA随着第一时钟信号SIGCLK1在时段T4的抬升而被抬升到第三电压2VDD之前,第一P型晶体管P1A可先在时段T3被导通。因此,第一电荷泵单元1001的输出端OUTA可在时段T4中,经由第一P型晶体管P1A输出第三电压2VDD。
同时,在时段T4中,第二电荷泵单元1002的第一N型晶体管N1B会随着被导通第一时钟信号SIGCLK1的电压抬升而被导通,因此第一电容C1B的第二端的端电压VBSTB会被第一电荷泵单元1001充电至第三电压2VDD。然而,第一P型晶体管P1A的栅极所需的导通延迟时间可能会减少第一电荷泵单元1001与第二电荷泵单元1002之间的电荷传递,进而降低效率。因此第一电荷泵单元1001的第一P型晶体管P1A可在时段T4之前的时段T3先开始导通,以确保在第一时钟信号SIGCLK1变为第一电压VDD时,可立即对第二电荷泵单元1002的第一电容C1B进行充电。
然而,在部分实施例中,若栅极延迟的时间甚短,则第二时钟信号SIGCLK2也可在第一时钟信号SIGCLK1自第二电压VSS变为第一电压VDD时,同步自第一电压VDD变为第二电压VSS。
再者,当第一电容C1A的第二端的端电压VBSTA为第三电压2VDD时,第二N型晶体管N2A可被导通,使得第三电容C3A的第二端的电压维持在第一电压VDD。因此,第一N型晶体管N1A可被截止,以避免逆向电流自第一电容C1A的第二端流向输入端INA。
在时段T5中,第二时钟信号SIGCLK2变为第一电压VDD,而第一时钟信号SIGCLK1、第三时钟信号SIGCLK3及第四时钟信号SIGCLK4则维持前一时段T4的电位。在时段T6中,第一时钟信号SIGCLK1变为第二电压VSS,而第二时钟信号SIGCLK2、第三时钟信号SIGCLK3及第四时钟信号SIGCLK4则维持前一时段T5的电位。
也就是说,在第一时钟信号SIGCLK1于时段T6中降低电位,使得第一电荷泵单元1001的第一电容C1A的第二端端电压VBSTA的电位也随着降低之前,第一P型晶体管P1A可在时段T5先被截止。因此,第二电荷泵单元1002的第一电容C1B的第二端不会因为第一P型晶体管P1A及第N型晶体管N1B的截止延迟,而从第一电荷泵单元1001接收到第一电压VDD,进而避免逆向电流。此外,第二P型晶体管P2A可在时段T6中被导通,使得第一P型晶体管P1A的第二端及控制端之间被电性短路,而此时第一P型晶体管P1A的操作状态将形同以二极管方式电性连接的晶体管,以避免逆向电流流经第一P型晶体管P1A。
在时段T7,第四时钟信号SIGCLK4变为第二电压VSS,而第一时钟信号SIGCLK1、第二时钟信号SIGCLK2及第三时钟信号SIGCLK3则维持前一时段T6的电位。在时段T8,第三时钟信号SIGCLK3变为第一电压VDD,而第一时钟信号SIGCLK1、第二时钟信号SIGCLK2及第四时钟信号SIGCLK4则维持前一时段T7的电位。
也就是说,在端电压VBSTB随着第三时钟信号SIGCLK3于时段T8的电压抬升而自第三电压2VDD抬升至第四电压3VDD之前,第一P型晶体管P1B可在时段T7中先导通。因此第二电荷泵单元1002的输出端OUTB即可在时段T8中经由第一P型晶体管P1B输出第四电压3VDD,而不会受到第一P型晶体管P1B的栅极延迟所影响。
总而言之,电荷泵电路的主要功能是在将电压输入端口所接收到的输入电压提高并经由电压输出端口输出高电压。本发明的电荷泵电路可以在较长的时段中(例如时段TA、T1、T4及T8)中进行电位提升及分享电荷的操作,同时也可在较短的时段中(例如时段TB、TC、T2、T3、T5、T6及T7)导通或截止电荷分享的路径以避免逆电流产生。
如此一来,两段式的电荷泵电路10便可以根据第一电压VDD产生第四电压3VDD。此外,透过四个时钟信号SIGCLK1、SIGCLK2、SIGCLK3及SIGCLK4,还可避免逆向电流。
根据先前所述的操作,由于第二电容C2A及第三电容C3A主要可用来控制晶体管的栅极,因此第二电容C2A及第三电容C3A虽然需要耐高压,但无须具有大的电容值。因此,在部分实施例中,第二电容C2A及第三电容C3A可为金属-氧化物-金属(metal-oxide-metal,MOM)电容,以确保能够电容能够承受高压,同时也无须过大的面积。
然而,由于第一电容C1A中所储存的电荷将被分享至下一级的电荷泵单元,因此第一电容C1A的电容值应该要足够大到能够维持输出电压。在此情况下,第一电容C1A可为晶体管电容以减少所需的面积。
再者,在图1中,第一电荷泵单元1001可另包括基极开关110A及放电电路120A。基极开关110A可以确保第一N型晶体管N1A的基极端处于较低的电压,以减少基体效应(bodyeffect)及漏电流。在第一电荷泵单元1001停止输出电压时,放电电路120A可对第三电容C3A的第二端进行放电,以提升第一电荷泵单元1001的可信赖度。
相似地,第二电荷泵单元1002也可包括基极开关110B及放电电路120B。
在图1中,基极开关110A可包括第四N型晶体管N4A及第五N型晶体管N5A。第四N型晶体管N4A具有第一端、第二端、控制端及基极端,第四N型晶体管N4A的第一端耦接于第一N型晶体管N1A的第一端,第四N型晶体管N4A的第二端耦接于第一N型晶体管N1A的基极端,第四N型晶体管N4A的控制端耦接于第一N型晶体管N1A的第二端,而第四N型晶体管N4A的基极端耦接于第一N型晶体管N1A的基极端。
第五N型晶体管N5A具有第一端、第二端、控制端及基极端,第五N型晶体管N5A的第一端耦接于第一N型晶体管N1A的基极端,第五N型晶体管N5A的第二端耦接于第一N型晶体管N1A的第二端,第五N型晶体管N5A的控制端耦接于第一N型晶体管N1A的第一端,而第五N型晶体管N5A的基极端耦接于第一N型晶体管N1A的基极端。
透过基极开关110A,第一N型晶体管N1A的基极端的电压就能够被控制在不大于第一N型晶体管N1A的第一端及第二端的电压。如此一来,就能够减少第一N型晶体管N1A的基极端所产生的基体效应及漏电流。
放电电路120耦接于第一N型晶体管N1A的控制端及***电压端130之间,以接收***电压VSS。
在图1中,放电电路120A可包括第六N型晶体管N6A及第七N型晶体管N7A。
第六N型晶体管N6A具有第一端、第二端、控制端及基极端,第六N型晶体管N6A的第一端耦接于第一N型晶体管N1A的控制端,而第六N型晶体管N6A的控制端可接收偏压电压Vbias,而第六N型晶体管N6A的基极端耦接于第六N型晶体管N6A的第二端。
第七N型晶体管N7A具有第一端、第二端、控制端及基极端,第七N型晶体管N7A的第一端耦接于第六N型晶体管N6A的第二端,第七N型晶体管N7A的第二端耦接于***电压端130,第七N型晶体管N7A的控制端可接收控制信号SIGctrl,而第七N型晶体管N7A的基极端耦接于第七N型晶体管N7A的第二端。
当电荷泵单元停止产生输出电压时,偏压电压Vbias及控制信号SIGctrl可导通第六N型晶体管N6A及第七N型晶体管N7A。然而,第三电容C3A的第二端电压可能相对较高,例如为第三电压2VDD。此外,第二电荷泵单元1002所需要放电的电压还可能更高。因此,在部分实施例中,第六N型晶体管N6A可为N型横向扩散金氧半晶体管(Laterally DiffusedMetal Oxide Semiconductor,LDMOS),以承受较高的耐压。在此情况下,第七N型晶体管N7A则可为一般低耐压的金氧半晶体管,以避免增加不必要的电路面积。然而,根据***的需求,放电电路也包括其他数量及/或其他种类的晶体管。
在部分实施例中,电荷泵电路10还可包括时钟产生电路12以产生所需的时钟信号。图3为本发明一实施例的时钟信号产生电路12的示意图。
时钟产生电路12包括时钟输入端CLK、非重迭时钟产生器CG、第一逆变器INV1、第二逆变器INV2、第三逆变器INV3及第四逆变器INV4。
时钟输入端可接收主要时钟信号SIGCLK0。在部分实施例中,主要时钟信号SIGCLK0可由所应用***中的时钟产生器产生。非重迭时钟产生器CG耦接于时钟输入端CLK,并可制造第一中介时钟信号SIGCLKA及第二中介时钟信号SIGCLKB。非重迭时钟产生器CG可由任何现今技术领域所习知或未知的非重迭时钟产生器来实作,并能使得第一中介时钟信号SIGCLKA及第二中介时钟信号SIGCLKB为非重迭的两个时钟信号。
第一逆变器INV1具有输入端及输出端,第一逆变器INV1的输入端可接收第一中介时钟信号SIGCLKA,而第一逆变器INV1的输出端可输出第二时钟信号SIGCLK2。
第二逆变器INV2具有输入端及输出端,第二逆变器INV2的输入端耦接于第一逆变器INV1的输出端,而第二逆变器INV2的输出端可输出第一时钟信号SIGCLK1。
第三逆变器INV3具有输入端及输出端,第三逆变器INV3的输入端可接收第二中介时钟信号SIGCLKB,而第三逆变器INV3的输出端可输出第四时钟信号SIGCLK4。
第四逆变器INV4具有输入端及输出端,第四逆变器INV4的输入端耦接于第三逆变器INV3的输出端,而第四逆变器INV4的输出端可输出第三时钟信号SIGCLK3。
利用时钟产生电路12,就能够产生电荷泵电路10所需的四个时钟信号SIGCLK1、SIGCLK2、SIGCLK3及SIGCLK4,以避免产生逆向电流,并可增加电荷泵电路10的效率。
图4为本发明另一实施例的时钟产生电路22的示意图。时钟产生电路22与时钟产生电路12具有相似的结构,然而时钟产生电路22还包括两个延迟组件DE1及DE2。
第一延迟组件DE1具有输入端及输出端,第一延迟组件DE1的输入端耦接于第一逆变器INV1的输出端。第二逆变器INV2具有输入端及输出端,第二逆变器INV2的输入端耦接于第一延迟组件DE1的输出端,而第二逆变器INV2的输出端可输出第一时钟信号SIGCLK1。
第二延迟组件DE2具有输入端及输出端,第二延迟组件DE2的输入端耦接于第三逆变器INV3的输出端。第四逆变器INV4具有输入端及输出端,第四逆变器INV4的输入端耦接于第二延迟组件DE2的输出端,而第四逆变器INV4的输出端可输出第三时钟信号SIGCLK3。
也就是说,第一延迟组件DE1可以设置在第一逆变器INV1及第二逆变器INV2之间,以根据***的需求使第一时钟信号SIGCLK1及第二时钟讯
SIGCLK2之间产生适当的延迟。相似地,第二延迟组件DE2可以设置在第三逆变器INV3及第四逆变器INV4之间,以使第三时钟信号SIGCLK3及第四时钟讯SIGCLK4之间产生适当的延迟。
虽然电荷泵电路10包括两级的电荷泵单元1001及1002,然而在其他的实施例中,电荷泵电路也可包括更多级的电荷泵单元以产生更高的电压。
图5为本发明另一实施例之电荷泵电路20的示意图。电荷泵电路20包括M个电荷泵单元1001至100M,其中M为大于1的正整数。电荷泵电路20可自电压输入端口VIN接收第一电压VDD,并产生第五电压(M+1)VDD,亦即第一电压VDD的(M+1)倍的电压。电荷泵单元1001至100M可具有相同的结构,然而,每两个相邻的电荷泵单元可接收相异组的时钟信号。
举例来说,在图5中,第i电荷泵单元100i的第一电容C1A的第一端会接收第一时钟信号SIGCLK1,第i电荷泵单元100i的第二电容C2A的第一端会接收第二时钟信号SIGCLK2,而第i电荷泵单元100i的第三电容C3A的第一端会接收第三时钟信号SIGCLK3,其中i为小于M的正整数。
在此情况下,第(i+1)电荷泵单元100(i+1)的第一电容C1B的第一端会接收第三时钟信号SIGCLK3,第(i+1)电荷泵单元100(i+1)的第二电容C2B的第一端会接收第四时钟信号SIGCLK4,而第(i+1)电荷泵单元100(i+1)的第三电容C3B的第一端会接收第一时钟信号SIGCLK1。
也就是说,连续两级电荷泵单元中的第一电容的第二端会在相异的时段充电,并在相异的时段被抬升,使得在前一级电荷泵单元中的储存的电荷能够稳定地与下一级的电荷泵单元分享。此外,电荷泵电路20可利用四个时钟信号SIGCLK1、SIGCLK2、SIGCLK3及SIGCLK4来产生高输出电压(M+1)VDD,同时也可减少逆向电流,并可增加电能效率。电荷泵单元20以可利用图3中的时钟产生电路12或图4中的时钟产生电路22来产生所需的时钟信号。
综上所述,本发明的实施例所提供的电荷泵电路可以利用四个时钟信号来产生高电压。透过精确设计过的四个时钟信号,相连两级的电荷泵单元就能够在相异的时段充电,并可在相异的时段被抬升,使得前一级电荷泵单元中的储存的电荷能够稳定地与下一级的电荷泵单元分享。透过在停止输出抬升电压之前,先将第一P型晶体管截止,就能够避免因为第一P型晶体管的栅极延迟所导致的逆向电流。此外,透过在输出抬升电压之前,先将第一P型晶体管导通,就能够避免因为第一P型晶体管的栅极延迟所导致的电能效率不彰。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (20)
1.一种电荷泵电路,其特征在于,包括:
第一电荷泵单元,用以接收输入电压、第一时钟信号、第二时钟信号及第三时钟信号,并用以根据所述第一时钟信号、所述第二时钟信号及所述第三时钟信号抬升所述输入电压以输出第一抬升电压;及
第二电荷泵单元,耦接于所述第一电荷泵单元,用以接收所述第一抬升电压、所述第一时钟信号、第四时钟信号及所述第三时钟信号,并用以根据所述第一时钟信号、所述第四时钟信号及所述第三时钟信号抬升所述第一抬升电压以输出第二抬升电压;
其中:
所述第一时钟信号及所述第三时钟信号为非重迭的两个时钟信号;
所述第二时钟信号的负缘领先所述第一时钟信号的正缘;
接续在所述第二时钟信号的所述负缘之后的所述第二时钟信号的正缘领先接续在所述第一时钟信号的所述正缘之后的所述第一时钟信号的负缘;
所述第四时钟信号的负缘领先所述第三时钟信号的正缘;及
接续在所述第四时钟信号的所述负缘之后的所述第四时钟信号的正缘领先接续在所述第三时钟信号的所述正缘之后的所述第三时钟信号的负缘。
2.如权利要求1所述的电荷泵电路,其特征在于所述第一电荷泵单元包括:
输入端,用以接收所述输入电压;
输出端,用以输出所述第一抬升电压;
第一N型晶体管,具有耦接于所述输入端的第一端,第二端,及控制端;
第二N型晶体管,具有耦接于所述输入端的第一端,耦接于所述第一N型晶体管的所述控制端的第二端,及耦接于所述第一N型晶体管的所述第二端的控制端;
第三N型晶体管,具有耦接于所述输入端的第一端,耦接于所述第一N型晶体管的所述第二端的第二端,及耦接于所述第三N型晶体管的所述第一端的控制端;
第一电容,具有用以接收所述第一时钟信号的第一端,及耦接于所述第一N型晶体管的所述第二端的第二端;
第一P型晶体管,具有耦接于所述第一N型晶体管的所述第二端的第一端,耦接于所述输出端的第二端,控制端,及耦接于所述第一P型晶体管的所述第二端的基极端;
第二P型晶体管,具有耦接于所述第一P型晶体管的所述控制端的第一端,耦接于所述输出端的第二端,耦接于所述第一P型晶体管的所述第一端的控制端,及耦接于所述第二P型晶体管的所述第二端的基极端;
第二电容,具有用以接收所述第二时钟信号的第一端,及耦接于所述第一P型晶体管的所述控制端的第二端;及
第三电容,具有用以接收所述第三时钟信号的第一端,及耦接于所述第一N型晶体管的所述控制端的第二端。
3.如权利要求2所述的电荷泵电路,其特征在于所述第一电荷泵单元另包括:
第四N型晶体管,具有耦接于所述第一N型晶体管的所述第一端的第一端,耦接于所述第一N型晶体管的基极端的第二端,耦接于所述第一N型晶体管的所述第二端的控制端,及耦接于所述第一N型晶体管的所述基极端的基极端;及
第五N型晶体管,具有耦接于所述第一N型晶体管的所述基极端的第一端,耦接于所述第一N型晶体管的所述第二端的第二端,耦接于所述第一N型晶体管的所述第一端的控制端,及耦接于所述第一N型晶体管的所述基极端的基极端。
4.如权利要求2所述的电荷泵电路,其特征在于所述第一电荷泵单元另包括放电电路,耦接于所述第一N型晶体管的所述控制端及***电压端之间,用以接收***电压。
5.如权利要求4所述的电荷泵电路,其特征在于所述放电电路包括:
第六N型晶体管,具有耦接于所述第一N型晶体管的所述控制端的第一端,第二端,及用以接收偏压电压的控制端;及
第七N型晶体管,具有耦接于所述第六N型晶体管的所述第二端的第一端,耦接于所述***电压端的第二端,及用以接收控制信号的控制端,及耦接于所述第七N型晶体管的所述第二端的基极端。
6.如权利要求5所述的电荷泵电路,其特征在于所述第六N型晶体管是为N型横向扩散金氧半晶体管。
7.如权利要求2所述的电荷泵电路,其特征在于所述第二电容及所述第三电容是为金属-氧化物-金属电容。
8.一种电荷泵电路,其特征在于,包括:
电压输入端口;
电压输出端口;及
M个电荷泵单元,包括:
第i电荷泵,包括:
输入端;
输出端;
第一N型晶体管,具有耦接于所述第i电荷泵单元的所述输入端的第一端,第二端,及控制端;
第二N型晶体管,具有耦接于所述第i电荷泵单元的所述输入端的第一端,耦接于所述第i电荷泵单元的所述第一N型晶体管的所述控制端的第二端,及耦接于所述第i电荷泵单元的所述第一N型晶体管的所述第二端的控制端;
第三N型晶体管,具有耦接于所述第i电荷泵单元的所述输入端的第一端,耦接于所述第i电荷泵单元的所述第一N型晶体管的所述第二端的第二端,及耦接于所述第i电荷泵单元的所述第三N型晶体管的所述第一端的控制端;
第一电容,具有用以接收第一时钟信号的第一端,及耦接于所述第i电荷泵单元的所述第一N型晶体管的所述第二端的第二端;
第一P型晶体管,具有耦接于所述第i电荷泵单元的所述第一N型晶体管的所述第二端的第一端,耦接于所述第i电荷泵单元的所述输出端的第二端,控制端,及耦接于所述第i电荷泵单元的所述第一P型晶体管的所述第二端的基极端;
第二P型晶体管,具有耦接于所述第i电荷泵单元的所述第一P型晶体管的所述控制端的第一端,耦接于所述第i电荷泵单元的所述输出端的第二端,耦接于所述第i电荷泵单元的所述第一P型晶体管的所述第一端的控制端,及耦接于所述第i电荷泵单元的所述第二P型晶体管的所述第二端的基极端;
第二电容,具有用以接收第二时钟信号的第一端,及耦接于所述第i电荷泵单元的所述第一P型晶体管的所述控制端的第二端;及
第三电容,具有用以接收第三时钟信号的第一端,及耦接于所述第i电荷泵单元的所述第一N型晶体管的所述控制端的第二端;及
第(i+1)电荷泵,包括:
输入端,耦接于所述第i电荷泵单元的所述输出端;
输出端;
第一N型晶体管,具有耦接于所述第(i+1)电荷泵单元的所述输入端的第一端,第二端,及控制端;
第二N型晶体管,具有耦接于所述第(i+1)电荷泵单元的所述输入端的第一端,耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述控制端的第二端,及耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述第二端的控制端;
第三N型晶体管,具有耦接于所述第(i+1)电荷泵单元的所述输入端的第一端,耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述第二端的第二端,及耦接于所述第(i+1)电荷泵单元的所述第三N型晶体管的所述第一端的控制端;
第一电容,具有用以接收所述第三时钟信号的第一端,及耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述第二端的第二端;
第一P型晶体管,具有耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述第二端的第一端,耦接于所述第(i+1)电荷泵单元的所述输出端的第二端,控制端,及耦接于所述第(i+1)电荷泵单元的所述第一P型晶体管的所述第二端的基极端;
第二P型晶体管,具有耦接于所述第(i+1)电荷泵单元的所述第一P型晶体管的所述控制端的第一端,耦接于所述第(i+1)电荷泵单元的所述输出端的第二端,耦接于所述第(i+1)电荷泵单元的所述第一P型晶体管的所述第一端的控制端,及耦接于所述第(i+1)电荷泵单元的所述第二P型晶体管的所述第二端的基极端;
第二电容,具有用以接收第四时钟信号的第一端,及耦接于所述第(i+1)电荷泵单元的所述第一P型晶体管的所述控制端的第二端;及
第三电容,具有用以接收所述第一时钟信号的第一端,及耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述控制端的第二端;
其中:
M是为大于1的正整数;
i是为小于M的正整数;及
所述第一时钟信号及所述第三时钟信号为非重迭的两个时钟信号。
9.如权利要求8所述的电荷泵电路,其特征在于:
所述第二时钟信号的负缘领先所述第一时钟信号的正缘;
接续在所述第二时钟信号的所述负缘之后的所述第二时钟信号的正缘领先接续在所述第一时钟信号的所述正缘之后的所述第一时钟信号的负缘;
所述第四时钟信号的负缘领先所述第三时钟信号的正缘;及
接续在所述第四时钟信号的所述负缘之后的所述第四时钟信号的正缘领先接续在所述第三时钟信号的所述正缘之后的所述第三时钟信号的负缘。
10.如权利要求1或9所述的电荷泵电路,其特征在于,另包括时钟产生电路,包括:
时钟输入端,用以接收主要时钟信号;
非重迭时钟产生器,耦接于所述时钟输入端,用以制造第一中介时钟信号及第二中介时钟信号,其中所述第一中介时钟信号及所述第二中介时钟信号为非重迭的两个时钟信号;
第一逆变器,具有用以接收所述第一中介时钟信号的输入端,及用以输出所述第二时钟信号的输出端;
第二逆变器,具有耦接于所述第一逆变器的所述输出端的输入端,及用以输出所述第一时钟信号的输出端;
第三逆变器,具有用以接收所述第二中介时钟信号的输入端,及用以输出所述第四时钟信号的输出端;及
第四逆变器,具有耦接于所述第三逆变器的所述输出端的输入端,及用以输出所述第三时钟信号的输出端。
11.如权利要求1或9所述的电荷泵电路,其特征在于,另包括时钟产生电路,包括:
时钟输入端,用以接收主要时钟信号;
非重迭时钟产生器,耦接于所述时钟输入端,用以制造第一中介时钟信号及第二中介时钟信号,其中所述第一中介时钟信号及所述第二中介时钟信号为非重迭的两个时钟信号;
第一逆变器,具有用以接收所述第一中介时钟信号的输入端,及用以输出所述第二时钟信号的输出端;
第一延迟组件,具有耦接于所述第一逆变器的所述输出端的输入端,及输出端;
第二逆变器,具有耦接于所述第一延迟组件的所述输出端的输入端,及用以输出所述第一时钟信号的输出端;
第三逆变器,具有用以接收所述第二中介时钟信号的输入端,及用以输出所述第四时钟信号的输出端;
第二延迟组件,具有耦接于所述第三逆变器的所述输出端的输入端,及输出端;及
第四逆变器,具有耦接于所述第二延迟组件的所述输出端的输入端,及用以输出所述第三时钟信号的输出端。
12.如权利要求8所述的电荷泵电路,其特征在于所述第i电荷泵单元另包括:
第四N型晶体管,具有耦接于所述第i电荷泵单元的所述第一N型晶体管的所述第一端的第一端,耦接于所述第i电荷泵单元的所述第一N型晶体管的一基极端的第二端,耦接于所述第i电荷泵单元的所述第一N型晶体管的所述第二端的控制端,及耦接于所述第i电荷泵单元的所述第一N型晶体管的所述基极端的基极端;及
第五N型晶体管,具有耦接于所述第i电荷泵单元的所述第一N型晶体管的所述基极端的第一端,耦接于所述第i电荷泵单元的所述第一N型晶体管的所述第二端的第二端,耦接于所述第i电荷泵单元的所述第一N型晶体管的所述第一端的控制端,及耦接于所述第i电荷泵单元的所述第一N型晶体管的所述基极端的基极端。
13.如权利要求8所述的电荷泵电路,其特征在于所述第i电荷泵单元另包括放电电路,耦接于所述第i电荷泵单元的所述第一N型晶体管的所述控制端及***电压端之间,用以接收***电压。
14.如权利要求13所述的电荷泵电路,其特征在于所述放电电路包括:
第六N型晶体管,具有耦接于所述第i电荷泵单元的所述第一N型晶体管的所述控制端的第一端,第二端,及用以接收偏压电压的控制端;
及
第七N型晶体管,具有耦接于所述第i电荷泵单元的所述第六N型晶体管的所述第二端的第一端,耦接于所述***电压端的第二端,用以接收控制信号的控制端,及耦接于所述第i电荷泵单元的所述第七N型晶体管的所述第二端的基极端。
15.如权利要求14所述的电荷泵电路,其特征在于所述第i电荷泵单元的所述第六N型晶体管是为N型横向扩散金氧半晶体管。
16.如权利要求8所述的电荷泵电路,其特征在于所述第(i+1)电荷泵单元另包括:
第四N型晶体管,具有耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述第一端的第一端,耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的基极端的第二端,耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述第二端的控制端,及耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述基极端的基极端;
及
第五N型晶体管,具有耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述基极端的第一端,耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述第二端的第二端,耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述第一端的控制端,及耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述基极端的基极端。
17.如权利要求8所述的电荷泵电路,其特征在于所述第(i+1)电荷泵单元另包括放电电路,耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述控制端及***电压端之间,用以接收***电压。
18.如权利要求17所述的电荷泵电路,其特征在于所述放电电路包括:
第六N型晶体管,具有耦接于所述第(i+1)电荷泵单元的所述第一N型晶体管的所述控制端的第一端,第二端,及用以接收偏压电压的控制端;及
第七N型晶体管,具有耦接于所述第(i+1)电荷泵单元的所述第六N型晶体管的所述第二端的第一端,耦接于所述***电压端的第二端,用以接收控制信号的控制端,及耦接于所述第(i+1)电荷泵单元的所述第七N型晶体管的所述第二端的基极端。
19.如权利要求18所述的电荷泵电路,其特征在于所述第(i+1)电荷泵单元的所述第六N型晶体管是为N型横向扩散金氧半晶体管。
20.如权利要求8所述的电荷泵电路,其特征在于所述第i电荷泵单元的所述第二电容及所述第三电容以及所述第(i+1)电荷泵单元的所述第二电容及所述第三电容是为金属-氧化物-金属电容。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662341105P | 2016-05-25 | 2016-05-25 | |
US15/604,664 US10003258B2 (en) | 2016-05-25 | 2017-05-25 | Charge pump circuit with a low reverse current |
US15/604,664 | 2017-05-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN108964444A true CN108964444A (zh) | 2018-12-07 |
CN108964444B CN108964444B (zh) | 2020-05-29 |
Family
ID=60418184
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710687034.6A Active CN108964444B (zh) | 2016-05-25 | 2017-08-11 | 电荷泵电路及电荷泵单元 |
CN201710729296.4A Active CN108964446B (zh) | 2016-05-25 | 2017-08-23 | 电荷泵单元及电荷泵电路 |
CN201710932265.9A Active CN108932965B (zh) | 2016-05-25 | 2017-10-10 | 非挥发性内存及程序化内存数组的方法 |
CN201710972339.1A Active CN108962332B (zh) | 2016-05-25 | 2017-10-18 | 内存***及感测装置 |
Family Applications After (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710729296.4A Active CN108964446B (zh) | 2016-05-25 | 2017-08-23 | 电荷泵单元及电荷泵电路 |
CN201710932265.9A Active CN108932965B (zh) | 2016-05-25 | 2017-10-10 | 非挥发性内存及程序化内存数组的方法 |
CN201710972339.1A Active CN108962332B (zh) | 2016-05-25 | 2017-10-18 | 内存***及感测装置 |
Country Status (5)
Country | Link |
---|---|
US (5) | US10090027B2 (zh) |
EP (1) | EP3407355B1 (zh) |
JP (2) | JP6389925B1 (zh) |
CN (4) | CN108964444B (zh) |
TW (4) | TWI666865B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110299173A (zh) * | 2019-07-05 | 2019-10-01 | 合肥联诺科技有限公司 | 一种用于nor flash编程处理的可控放电模块 |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW202404049A (zh) | 2016-12-14 | 2024-01-16 | 成真股份有限公司 | 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器 |
US11625523B2 (en) | 2016-12-14 | 2023-04-11 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips |
US10447274B2 (en) | 2017-07-11 | 2019-10-15 | iCometrue Company Ltd. | Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells |
US10957679B2 (en) | 2017-08-08 | 2021-03-23 | iCometrue Company Ltd. | Logic drive based on standardized commodity programmable logic semiconductor IC chips |
US10630296B2 (en) | 2017-09-12 | 2020-04-21 | iCometrue Company Ltd. | Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells |
US10608642B2 (en) | 2018-02-01 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells |
US10623000B2 (en) | 2018-02-14 | 2020-04-14 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
US10608638B2 (en) | 2018-05-24 | 2020-03-31 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips |
KR102577262B1 (ko) | 2018-08-14 | 2023-09-11 | 삼성전자주식회사 | 확산 방지 영역을 갖는 반도체 소자 |
US10892011B2 (en) | 2018-09-11 | 2021-01-12 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
US11309334B2 (en) | 2018-09-11 | 2022-04-19 | iCometrue Company Ltd. | Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells |
US10937762B2 (en) | 2018-10-04 | 2021-03-02 | iCometrue Company Ltd. | Logic drive based on multichip package using interconnection bridge |
US11616046B2 (en) | 2018-11-02 | 2023-03-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
US11056197B2 (en) | 2018-11-08 | 2021-07-06 | Samsung Electronics Co., Ltd. | Charge pump and memory device including the same |
KR20200053324A (ko) * | 2018-11-08 | 2020-05-18 | 삼성전자주식회사 | 차지 펌프 및 차지 펌프를 포함하는 메모리 장치 |
TWI708253B (zh) | 2018-11-16 | 2020-10-21 | 力旺電子股份有限公司 | 非揮發性記憶體良率提升的設計暨測試方法 |
US11211334B2 (en) | 2018-11-18 | 2021-12-28 | iCometrue Company Ltd. | Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip |
US11360704B2 (en) * | 2018-12-21 | 2022-06-14 | Micron Technology, Inc. | Multiplexed signal development in a memory device |
US10818592B1 (en) * | 2019-04-29 | 2020-10-27 | Nanya Technology Corporation | Semiconductor memory device including decoupling capacitor array arranged overlying one-time programmable device |
US10985154B2 (en) | 2019-07-02 | 2021-04-20 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits |
US11227838B2 (en) | 2019-07-02 | 2022-01-18 | iCometrue Company Ltd. | Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits |
US11404415B2 (en) * | 2019-07-05 | 2022-08-02 | Globalfoundries U.S. Inc. | Stacked-gate transistors |
US11887930B2 (en) | 2019-08-05 | 2024-01-30 | iCometrue Company Ltd. | Vertical interconnect elevator based on through silicon vias |
US11637056B2 (en) | 2019-09-20 | 2023-04-25 | iCometrue Company Ltd. | 3D chip package based on through-silicon-via interconnection elevator |
US10957701B1 (en) * | 2019-11-11 | 2021-03-23 | Globalfoundries U.S. Inc. | Fin-based anti-fuse device for integrated circuit (IC) products, methods of making such an anti-fuse device and IC products comprising such an anti-fuse device |
US11600526B2 (en) | 2020-01-22 | 2023-03-07 | iCometrue Company Ltd. | Chip package based on through-silicon-via connector and silicon interconnection bridge |
US11328957B2 (en) * | 2020-02-25 | 2022-05-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US11270780B2 (en) | 2020-03-31 | 2022-03-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory readout circuit and method |
US11183502B1 (en) * | 2020-08-20 | 2021-11-23 | Nanya Technology Corporation | Memory cell and Method for reading out data therefrom |
CN112039335A (zh) * | 2020-08-21 | 2020-12-04 | 厦门半导体工业技术研发有限公司 | 一种电压发生器和半导体器件 |
US20220199622A1 (en) * | 2020-12-18 | 2022-06-23 | Ememory Technology Inc. | Resistive memory cell and associated cell array structure |
CN116137493A (zh) | 2021-11-17 | 2023-05-19 | 科奇芯有限公司 | 电荷泵电路 |
US20230016311A1 (en) * | 2021-12-03 | 2023-01-19 | Wuxi Esiontech Co., Ltd. | Clock skew-adjustable chip clock architecture of progarmmable logic chip |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10243636A (ja) * | 1997-02-26 | 1998-09-11 | Toshiba Corp | 昇圧回路及び半導体記憶装置 |
US20050195017A1 (en) * | 2004-03-03 | 2005-09-08 | Tien-Tzu Chen | High efficiency charge pump with prevention from reverse current |
CN102646387A (zh) * | 2011-05-19 | 2012-08-22 | 京东方科技集团股份有限公司 | 移位寄存器及行扫描驱动电路 |
CN104205594A (zh) * | 2012-03-23 | 2014-12-10 | Soitec公司 | 包含多栅极晶体管的电荷泵电路及其操作方法 |
US20160197551A1 (en) * | 2015-01-07 | 2016-07-07 | Ememory Technology Inc. | Charge pump circuit capable of reducing reverse currents |
CN205883044U (zh) * | 2016-07-06 | 2017-01-11 | 西安紫光国芯半导体有限公司 | 电荷泵电路及其单级电路 |
Family Cites Families (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2537264B2 (ja) | 1988-04-13 | 1996-09-25 | 株式会社東芝 | 半導体記憶装置 |
JP3076606B2 (ja) | 1990-12-14 | 2000-08-14 | 富士通株式会社 | 半導体記憶装置およびその検査方法 |
US5126590A (en) * | 1991-06-17 | 1992-06-30 | Micron Technology, Inc. | High efficiency charge pump |
JP3178946B2 (ja) | 1993-08-31 | 2001-06-25 | 沖電気工業株式会社 | 半導体記憶装置及びその駆動方法 |
JPH0778465A (ja) | 1993-09-10 | 1995-03-20 | Oki Micro Design Miyazaki:Kk | 半導体集積回路 |
DE69408665T2 (de) | 1994-08-12 | 1998-10-15 | Cons Ric Microelettronica | Spannungserhöher vom Ladungspumpentype |
KR0142403B1 (ko) * | 1994-12-20 | 1998-07-15 | 김광호 | 반도체 메모리장치의 전원승압회로 |
KR0149220B1 (ko) | 1994-12-27 | 1998-12-01 | 김주용 | 챠지 펌프 회로 |
US5729493A (en) | 1996-08-23 | 1998-03-17 | Motorola Inc. | Memory suitable for operation at low power supply voltages and sense amplifier therefor |
JP3557090B2 (ja) | 1998-03-31 | 2004-08-25 | 株式会社東芝 | 半導体記憶装置 |
US6483377B2 (en) | 2001-01-10 | 2002-11-19 | Texas Instruments Incorporated | Low slew rate charge pump |
US6501325B1 (en) * | 2001-01-18 | 2002-12-31 | Cypress Semiconductor Corp. | Low voltage supply higher efficiency cross-coupled high voltage charge pumps |
US6661682B2 (en) * | 2001-02-16 | 2003-12-09 | Imec (Interuniversitair Microelectronica Centrum) | High voltage generating charge pump circuit |
JP2003077282A (ja) | 2001-08-31 | 2003-03-14 | Fujitsu Ltd | 不揮発性半導体記憶装置 |
KR100454144B1 (ko) * | 2001-11-23 | 2004-10-26 | 주식회사 하이닉스반도체 | 멀티 뱅크 구조의 플래쉬 메모리 장치 |
KR100404001B1 (ko) * | 2001-12-29 | 2003-11-05 | 주식회사 하이닉스반도체 | 차지 펌프 회로 |
KR100538883B1 (ko) * | 2003-04-29 | 2005-12-23 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
CN1455574A (zh) * | 2003-05-30 | 2003-11-12 | 无敌科技(西安)有限公司 | 选择性信息储存***及其实现方法 |
US7411840B2 (en) * | 2004-03-02 | 2008-08-12 | Via Technologies, Inc. | Sense mechanism for microprocessor bus inversion |
JP4727261B2 (ja) * | 2005-03-16 | 2011-07-20 | 三菱電機株式会社 | 分周回路、電源回路及び表示装置 |
US7551503B2 (en) * | 2005-06-24 | 2009-06-23 | Macronix International Co., Ltd. | Method for refreshing a flash memory |
JP4728726B2 (ja) * | 2005-07-25 | 2011-07-20 | 株式会社東芝 | 半導体記憶装置 |
JP2007034943A (ja) * | 2005-07-29 | 2007-02-08 | Sony Corp | 共有メモリ装置 |
US7301380B2 (en) | 2006-04-12 | 2007-11-27 | International Business Machines Corporation | Delay locked loop having charge pump gain independent of operating frequency |
KR20080029696A (ko) * | 2006-09-29 | 2008-04-03 | 주식회사 하이닉스반도체 | 리던던시 회로를 구비한 반도체 메모리 장치 |
CN101154683B (zh) * | 2006-09-29 | 2011-03-30 | 旺宏电子股份有限公司 | 晶体管结构及其制造方法 |
JP4883780B2 (ja) * | 2006-11-14 | 2012-02-22 | ルネサスエレクトロニクス株式会社 | チャージポンプ回路 |
KR100818710B1 (ko) * | 2006-11-21 | 2008-04-01 | 주식회사 하이닉스반도체 | 전압펌핑장치 |
TWI331447B (en) | 2007-03-20 | 2010-10-01 | Novatek Microelectronics Corp | Charge pump circuit |
JP4498374B2 (ja) * | 2007-03-22 | 2010-07-07 | 株式会社東芝 | 半導体記憶装置 |
US7656731B2 (en) * | 2007-03-30 | 2010-02-02 | Qualcomm, Incorporated | Semi-shared sense amplifier and global read line architecture |
US7446596B1 (en) | 2007-05-25 | 2008-11-04 | Atmel Corporation | Low voltage charge pump |
CN101409554B (zh) * | 2007-10-11 | 2012-05-16 | 北京朗波芯微技术有限公司 | 用于电荷泵锁相环的环路滤波电路 |
KR101102776B1 (ko) | 2008-02-13 | 2012-01-05 | 매그나칩 반도체 유한회사 | 비휘발성 메모리 소자의 단위 셀 및 이를 구비한 비휘발성메모리 소자 |
US7859043B2 (en) * | 2008-02-25 | 2010-12-28 | Tower Semiconductor Ltd. | Three-terminal single poly NMOS non-volatile memory cell |
CN101685677A (zh) * | 2008-09-27 | 2010-03-31 | 英华达(上海)科技有限公司 | 闪存检测装置及其方法 |
US8144537B2 (en) | 2008-11-11 | 2012-03-27 | Stmicroelectronics Pvt. Ltd. | Balanced sense amplifier for single ended bitline memory architecture |
US8742833B2 (en) | 2008-12-02 | 2014-06-03 | Himax Technologies Limited | Charge pump circuit and method thereof |
US8154936B2 (en) * | 2008-12-30 | 2012-04-10 | Stmicroelectronics Pvt. Ltd. | Single-ended bit line based storage system |
US8305790B2 (en) | 2009-03-16 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical anti-fuse and related applications |
US9042173B2 (en) | 2010-01-29 | 2015-05-26 | Texas Instruments Incorporated | Efficient memory sense architecture |
TW201203253A (en) | 2010-07-06 | 2012-01-16 | Maxchip Electronics Corp | One time programmable memory and the manufacturing method and operation method thereof |
JP5673935B2 (ja) * | 2010-12-28 | 2015-02-18 | セイコーエプソン株式会社 | 不揮発性記憶装置、電子機器 |
KR20130093303A (ko) * | 2012-02-14 | 2013-08-22 | 에스케이하이닉스 주식회사 | 전하 펌프 장치 및 그 단위 셀 |
JP5444414B2 (ja) | 2012-06-04 | 2014-03-19 | 株式会社東芝 | 磁気ランダムアクセスメモリ |
CN103456711B (zh) * | 2012-06-05 | 2016-03-23 | 中芯国际集成电路制造(上海)有限公司 | 鳍型反熔丝结构及其制造方法 |
US9070424B2 (en) | 2012-06-29 | 2015-06-30 | Samsung Electronics Co., Ltd. | Sense amplifier circuitry for resistive type memory |
US9536883B2 (en) * | 2012-07-12 | 2017-01-03 | Broadcom Corporation | Dual anti-fuse |
US9337318B2 (en) * | 2012-10-26 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with dummy gate on non-recessed shallow trench isolation (STI) |
US9601499B2 (en) * | 2013-05-16 | 2017-03-21 | Ememory Technology Inc. | One-time programmable memory cell capable of reducing leakage current and preventing slow bit response, and method for programming a memory array comprising the same |
TWI502722B (zh) | 2013-07-24 | 2015-10-01 | Ememory Technology Inc | 改善讀取特性的反熔絲單次可程式記憶胞及記憶體的操作方法 |
US20150078103A1 (en) * | 2013-09-13 | 2015-03-19 | Lsi Corporation | Sensing technique for single-ended bit line memory architectures |
US20150194433A1 (en) * | 2014-01-08 | 2015-07-09 | Broadcom Corporation | Gate substantial contact based one-time programmable device |
CN104979362B (zh) * | 2014-04-10 | 2019-11-19 | 三星电子株式会社 | 具有翅片式有源图案和栅极节点的半导体装置 |
US9171752B1 (en) | 2014-08-12 | 2015-10-27 | Globalfoundries Inc. | Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product |
US9460761B2 (en) * | 2014-08-14 | 2016-10-04 | Stmicroelectronics (Rousset) Sas | Lower power sense amplifier for reading non-volatile memory cells |
KR102179169B1 (ko) * | 2014-09-02 | 2020-11-18 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 제조방법 |
DE102014115433A1 (de) * | 2014-10-23 | 2016-05-12 | Infineon Technologies Ag | Ladungspumpe |
US9620176B2 (en) | 2015-09-10 | 2017-04-11 | Ememory Technology Inc. | One-time programmable memory array having small chip area |
US10109364B2 (en) | 2015-10-21 | 2018-10-23 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Non-volatile memory cell having multiple signal pathways to provide access to an antifuse of the memory cell |
US9613714B1 (en) * | 2016-01-19 | 2017-04-04 | Ememory Technology Inc. | One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method |
JP6200983B2 (ja) * | 2016-01-25 | 2017-09-20 | 力旺電子股▲ふん▼有限公司eMemory Technology Inc. | ワンタイムプログラマブルメモリセル、該メモリセルを含むメモリアレイのプログラム方法及び読み込み方法 |
US9536991B1 (en) | 2016-03-11 | 2017-01-03 | Globalfoundries Inc. | Single diffusion break structure |
CN107306082B (zh) * | 2016-04-18 | 2020-05-22 | 晶门科技(深圳)有限公司 | 电荷泵电路 |
US9589970B1 (en) | 2016-08-02 | 2017-03-07 | United Microelectronics Corp. | Antifuse one-time programmable memory |
-
2017
- 2017-05-24 US US15/603,478 patent/US10090027B2/en active Active
- 2017-05-25 US US15/604,662 patent/US10224079B2/en active Active
- 2017-05-25 US US15/604,672 patent/US9935113B2/en active Active
- 2017-05-25 US US15/604,664 patent/US10003258B2/en active Active
- 2017-06-02 JP JP2017109618A patent/JP6389925B1/ja active Active
- 2017-06-08 JP JP2017113074A patent/JP2018201002A/ja active Pending
- 2017-06-26 EP EP17177772.5A patent/EP3407355B1/en active Active
- 2017-07-27 TW TW106125243A patent/TWI666865B/zh active
- 2017-08-11 CN CN201710687034.6A patent/CN108964444B/zh active Active
- 2017-08-17 TW TW106127886A patent/TWI636652B/zh active
- 2017-08-23 CN CN201710729296.4A patent/CN108964446B/zh active Active
- 2017-09-28 TW TW106133409A patent/TWI630708B/zh active
- 2017-10-06 TW TW106134435A patent/TWI630621B/zh active
- 2017-10-10 CN CN201710932265.9A patent/CN108932965B/zh active Active
- 2017-10-18 CN CN201710972339.1A patent/CN108962332B/zh active Active
-
2019
- 2019-01-15 US US16/247,584 patent/US10714155B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10243636A (ja) * | 1997-02-26 | 1998-09-11 | Toshiba Corp | 昇圧回路及び半導体記憶装置 |
US20050195017A1 (en) * | 2004-03-03 | 2005-09-08 | Tien-Tzu Chen | High efficiency charge pump with prevention from reverse current |
CN102646387A (zh) * | 2011-05-19 | 2012-08-22 | 京东方科技集团股份有限公司 | 移位寄存器及行扫描驱动电路 |
CN104205594A (zh) * | 2012-03-23 | 2014-12-10 | Soitec公司 | 包含多栅极晶体管的电荷泵电路及其操作方法 |
US20160197551A1 (en) * | 2015-01-07 | 2016-07-07 | Ememory Technology Inc. | Charge pump circuit capable of reducing reverse currents |
CN205883044U (zh) * | 2016-07-06 | 2017-01-11 | 西安紫光国芯半导体有限公司 | 电荷泵电路及其单级电路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110299173A (zh) * | 2019-07-05 | 2019-10-01 | 合肥联诺科技有限公司 | 一种用于nor flash编程处理的可控放电模块 |
Also Published As
Publication number | Publication date |
---|---|
US20190147922A1 (en) | 2019-05-16 |
US10003258B2 (en) | 2018-06-19 |
US10714155B2 (en) | 2020-07-14 |
US20170346393A1 (en) | 2017-11-30 |
TWI666865B (zh) | 2019-07-21 |
CN108932965A (zh) | 2018-12-04 |
US10090027B2 (en) | 2018-10-02 |
US20170345464A1 (en) | 2017-11-30 |
TWI636652B (zh) | 2018-09-21 |
TW201902096A (zh) | 2019-01-01 |
JP2018201002A (ja) | 2018-12-20 |
TW201901674A (zh) | 2019-01-01 |
EP3407355A1 (en) | 2018-11-28 |
CN108962332B (zh) | 2021-03-23 |
CN108932965B (zh) | 2020-12-01 |
US10224079B2 (en) | 2019-03-05 |
JP2018198105A (ja) | 2018-12-13 |
CN108964444B (zh) | 2020-05-29 |
JP6389925B1 (ja) | 2018-09-12 |
CN108964446B (zh) | 2020-08-25 |
CN108962332A (zh) | 2018-12-07 |
US9935113B2 (en) | 2018-04-03 |
TW201901929A (zh) | 2019-01-01 |
US20170345828A1 (en) | 2017-11-30 |
US20170346394A1 (en) | 2017-11-30 |
EP3407355B1 (en) | 2020-04-29 |
TWI630708B (zh) | 2018-07-21 |
TW201902097A (zh) | 2019-01-01 |
CN108964446A (zh) | 2018-12-07 |
TWI630621B (zh) | 2018-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108964444A (zh) | 电荷泵电路及电荷泵单元 | |
CN106941317B (zh) | 电荷泵单元及电荷泵电路 | |
CN104300782B (zh) | 电荷泵电路 | |
US8026755B2 (en) | Signal output apparatus, charge pump, voltage doubler and method for outputting current | |
CN109039059B (zh) | 一种高效的多模式电荷泵 | |
CN108390556A (zh) | 一种电荷泵电路 | |
CN101951144A (zh) | 高效电荷泵及其工作方法 | |
CN108418420A (zh) | 一种基于多路非交叠时钟的电荷泵电路 | |
CN103036544A (zh) | 一种上电复位电路 | |
CN102457179B (zh) | 具有低噪声及高输出电压电流的电子泵 | |
CN207490762U (zh) | 一种快速升压电荷泵电路 | |
CN104714589A (zh) | 一种cmos片上直流负电压产生电路 | |
CN102324840B (zh) | 电荷泵及工作方法 | |
CN111509973B (zh) | 一种减小输出电压纹波的电荷泵 | |
TW201131954A (en) | Charge pump | |
CN108551257A (zh) | 一种电荷泵结构 | |
CN102456395B (zh) | 用于低供应电压的电子泵 | |
TW201012069A (en) | Voltage level shifter with voltage boost mechanism | |
CN101005236B (zh) | 升压电路 | |
CN107546976A (zh) | 电荷泵电路及电荷泵 | |
CN207304374U (zh) | 电荷泵和存储装置 | |
CN207743865U (zh) | 基于开关电容的微能量收集升压dc-dc转换电路 | |
CN103684380B (zh) | 一种开关电容电路 | |
CN107968564B (zh) | 基于开关电容的微能量收集升压dc-dc转换电路 | |
CN107453602A (zh) | 电荷泵和存储装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |