CN108957960A - A kind of promotion substrate Effective number of chips purpose exposure method - Google Patents
A kind of promotion substrate Effective number of chips purpose exposure method Download PDFInfo
- Publication number
- CN108957960A CN108957960A CN201810574721.1A CN201810574721A CN108957960A CN 108957960 A CN108957960 A CN 108957960A CN 201810574721 A CN201810574721 A CN 201810574721A CN 108957960 A CN108957960 A CN 108957960A
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- China
- Prior art keywords
- pcm
- layer
- exposure
- chips
- effective number
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Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70058—Mask illumination systems
- G03F7/70125—Use of illumination settings tailored to particular mask patterns
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
- G03F7/7085—Detection arrangement, e.g. detectors of apparatus alignment possibly mounted on wafers, exposure dose, photo-cleaning flux, stray light, thermal load
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Epidemiology (AREA)
- Public Health (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The present invention relates to a kind of promotion substrate Effective number of chips purpose exposure methods, comprise the following steps: 1) make mask: every layer of litho pattern of the mask includes two kinds of domains of pure chip layer and PCM layer, and two kinds of layout sizes are identical；2) set exposure position: according to the requirement of PCM test position, in the position setting exposure PCM layer that need to carry out PCM test, the setting of other regions exposes corresponding pure chip layer；3) it sets exposure parameter: PCM layer and pure chip layer exposure parameter is respectively set；4) PCM is tested.Advantage: 1) being effectively reduced PCM figure duty ratio on disk, improves unit disk Effective number of chips mesh, cost of implementation saving and improved efficiency.2) it is not limited to wafer substrate, is not limited to litho machine brand and model etc., suitable for all semiconductor fabrication process using step printing and PCM measuring technology.3) design also may extend to the mask manufacture of contact photoetching machine 1:1.
Description
Technical field
The present invention is a kind of promotion substrate Effective number of chips purpose exposure method, belongs to technical field of manufacturing semiconductors.
Background technique
In semiconductor chip fabrication, PCM (process control monitor) test is a kind of effective process
Control means monitor influence and technique of the online process to wafer performance parameter by specific design configuration in measurement PCM
Fluctuation etc..
In the chip manufacturing process using step-by-step movement (stepper) litho machine, due to the introducing of PCM technology, in mask
When version design, PCM figure and graphics chip can be pressed certain arrangement mode, are placed in every layer mask version jointly.We claim
Single exposure is a shot, and the mode of Stepper photo-etching machine exposal is that the stepping of shot by shot repeats, until exposure region
Domain is booked entire disk.PCM figure and graphics chip are transferred on disk from mask simultaneously, by stepper litho machine work
It is determined as mode, includes one group of PCM figure and graphics chip in each shot.
For maturation or connect maturescent semiconductor technology, it is contemplated that testing cost and flow period often utilize disk
The test result of certain several (such as 5 or 9) PCM sample is gone up to characterize the behavior pattern of entire disk.In this situation
Under, the densely covered PCM figure of full sheet is a kind of wasting of resources actually, it is necessary to by a kind of exposure strategies of optimization, guarantee PCM
Under the premise of number of samples meets process monitoring demand, duty ratio of the PCM figure on entire disk is reduced, it is effective to increase disk
Core number.
Summary of the invention
Proposed by the present invention is a kind of promotion substrate Effective number of chips purpose exposure method, and its object is to close for full sheet
The defect of the wasting of resources existing for the PCM figure of cloth reduces PCM figure in entire disk by adjusting photo-etching machine exposal strategy
On duty ratio, to improve unit disk Effective number of chips mesh.
Technical solution of the invention: a kind of promotion substrate Effective number of chips purpose exposure method comprises the following steps:
1) make mask: every layer of litho pattern of the mask includes two kinds of domains of pure chip layer and PCM layer, two kinds of domains
Size is identical；
2) it sets exposure position: according to the requirement of PCM test position, exposing PCM layer in the position setting that need to carry out PCM test,
The setting of other regions exposes corresponding pure chip layer；
3) it sets exposure parameter: PCM layer and pure chip layer exposure parameter is respectively set；
4) PCM is tested.
Beneficial effects of the present invention:
1) PCM figure duty ratio on disk is effectively reduced, improves unit disk Effective number of chips mesh, cost of implementation saving and efficiency
It is promoted.It is a kind of economical and practical process strategies especially for the semiconductors manufacture of volume production.
2) be not limited to wafer substrate, be not limited to litho machine brand and model etc., be suitable for it is all using step printings and
The semiconductor fabrication process of PCM measuring technology.
3) design also may extend to the mask manufacture of contact photoetching machine 1:1.
Detailed description of the invention
Attached drawing 1 is traditional stepper photolithography edition territory schematic diagram.
Attached drawing 2 is to promote substrate Effective number of chips purpose stepper photolithography edition territory schematic diagram, wherein figure (a) is pure core
Lamella, figure (b) are the mixed layers that PCM layer or PCM+ chip are constituted.
Attached drawing 3 is traditional disk exposure arrangement schematic diagram.
Attached drawing 4 is to promote substrate Effective number of chips purpose disk exposure arrangement schematic diagram.
Specific embodiment
A kind of promotion substrate Effective number of chips purpose exposure method, comprises the following steps:
1) make mask: every layer of litho pattern of the mask includes two kinds of domains of pure chip layer and PCM layer, two kinds of domains
Size is identical；
2) it sets exposure position: according to the requirement of PCM test position, exposing PCM layer in the position setting that need to carry out PCM test,
The setting of other regions exposes corresponding pure chip layer；
3) it sets exposure parameter: PCM layer and pure chip layer exposure parameter is respectively set；
4) PCM is tested.
The exposure method uses stepper litho machine chip manufacturing process.
In the step 1) production mask, the typesetting of pure chip layer domain is made of graphics chip completely.
In step 1) production mask, the typesetting of PCM layer domain regards PCM dimension of picture size, by pure PCM figure or
The mode that PCM figure is mixed with graphics chip is constituted, and layout size is identical as pure chip layer layout size.Specifically, work as PCM
When graphics area is suitable with exposure shot size, PCM layer domain is by pure PCM figure constitution；And when PCM graphics area is much smaller than exposure
When light shot size, PCM layer domain can be made of the mode that PCM figure is mixed with graphics chip.
In the step 2 setting exposure position, position of the PCM layer on disk is uniformly arranged, to realize PCM sampling prison
Control the representativeness to entire disk performance parameter.
In the step 2 setting exposure position, PCM layer and pure chip layer position are not overlapped, and the two is covered with entire circle jointly
Piece.
It is identical to PCM layer and the setting of pure chip layer when carrying out disk exposure technology in the step 3) setting exposure parameter
Exposure parameter, to realize PCM monitoring to the representativeness of chip performance parameter.
In step 4) PCM test, during progress or when final PCM test, the selection of test position with 2) set
Determine the position consistency set in exposure position.
The substrate is wafer substrate.
Further explanation of the technical solution of the present invention with reference to the accompanying drawing
As shown in attached drawing 1,2, a set of product dedicated mask version is made, the mask (see figure 2) and normal mask version (see figure 1)
Difference be its every layer litho pattern need to comprising two kinds of domains, i.e., pure chip layer and PCM layer (or PCM+ chip constitute it is mixed
Close layer), two kinds of domains are same size, later in schematic diagram, respectively referred to as with C and P+C.It should be pointed out that for this
Kind PCM layer has many restrictions to the selection of shot size in by the layout design of pure PCM figure constitution.Such as shot size
It selects excessive, although ensure that exposure efficiency, will cause disk area loss；If shot size selection is too small, although saving
Disk area, but due to too small shot size, the time for exposure of single disk can greatly increase.And PCM layer is schemed by PCM
The design that shape adds graphics chip mixing to constitute can evade the problem, while it is effective with disk area to realize that exposure efficiency is promoted
It utilizes.In practical application, it is proposed that preferentially select the latter as far as possible.
It, should be according to PCM test position in working out litho machine when every layer of exposure file of the product as shown in attached drawing 3,4
It is required that in the position setting exposure PCM layer that need to carry out PCM test, the corresponding pure chip layer of other regional exposures.Specific visible figure
4, what it is in most of regional exposure is pure chip " C " layer, only places " P+C " layer in the position of sampling monitoring PCM data.Exposure
The number of " P+C " layer shot can be generally similar to be shown on disk and uniformly place according to the maturity unrestricted choice of technique.
PCM layer and pure chip layer exposure parameter need to be respectively set in the exposure technology stage in disk；In general, PCM layer and pure
Chip layer need to use identical exposure condition setting, this is to make subsequent PCM monitoring that can preferably represent chip region.
In the process or final PCM test position and it is above-mentioned 2) in be consistent.
According to above-mentioned steps, the present invention can realize by the design of domain and the optimization of exposure strategies and improve unit disk
Core number, so as to cost of implementation saving and improved efficiency.
Claims (9)
1. a kind of promotion substrate Effective number of chips purpose exposure method, characterized by comprising the steps of:
1) make mask: every layer of litho pattern of the mask includes two kinds of domains of pure chip layer and PCM layer, two kinds of domains
Size is identical；
2) it sets exposure position: according to the requirement of PCM test position, exposing PCM layer in the position setting that need to carry out PCM test,
The setting of other regions exposes corresponding pure chip layer；
3) it sets exposure parameter: PCM layer and pure chip layer exposure parameter is respectively set；
4) PCM is tested.
2. promotion substrate Effective number of chips purpose exposure method according to claim 1, it is characterised in that the exposure side
Method uses stepper litho machine chip manufacturing process.
3. promotion substrate Effective number of chips purpose exposure method according to claim 1, it is characterised in that the step 1)
It makes in mask, the typesetting of pure chip layer domain is made of graphics chip completely.
4. promotion substrate Effective number of chips purpose exposure method according to claim 1, it is characterised in that the step 1)
It makes in mask, the typesetting of PCM layer domain is made of the mode that pure PCM figure or PCM figure are mixed with graphics chip, domain
Size is identical as pure chip layer layout size.
5. promotion substrate Effective number of chips purpose exposure method according to claim 1, it is characterised in that the step 2
It sets in exposure position, position of the PCM layer on disk is uniformly arranged, to realize that entire disk performance is joined in PCM sampling monitoring
Several representativenesses.
6. promotion substrate Effective number of chips purpose exposure method according to claim 1, it is characterised in that the step 2
It sets in exposure position, PCM layer and pure chip layer position are not overlapped, and the two is covered with entire disk jointly.
7. promotion substrate Effective number of chips purpose exposure method according to claim 1, it is characterised in that the step 3)
It sets in exposure parameter, when carrying out disk exposure technology, identical exposure parameter is arranged to PCM layer and pure chip layer, to realize
PCM monitors the representativeness to chip performance parameter.
8. promotion substrate Effective number of chips purpose exposure method according to claim 1, it is characterised in that the step 4)
In PCM test, during progress or when final PCM test, set in the selection of test position and 2) setting exposure position
Position consistency.
9. promotion substrate Effective number of chips purpose exposure method according to claim 1, it is characterised in that the substrate is
Wafer substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810574721.1A CN108957960A (en) | 2018-06-06 | 2018-06-06 | A kind of promotion substrate Effective number of chips purpose exposure method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810574721.1A CN108957960A (en) | 2018-06-06 | 2018-06-06 | A kind of promotion substrate Effective number of chips purpose exposure method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108957960A true CN108957960A (en) | 2018-12-07 |
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ID=64493135
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810574721.1A Pending CN108957960A (en) | 2018-06-06 | 2018-06-06 | A kind of promotion substrate Effective number of chips purpose exposure method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111929987A (en) * | 2020-09-25 | 2020-11-13 | 歌尔股份有限公司 | Nano-imprinting process monitoring device and method and nano-imprinting equipment |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1636273A (en) * | 2001-02-27 | 2005-07-06 | 皇家菲利浦电子有限公司 | Semiconductor wafer with process control modules |
| CN1898796A (en) * | 2003-12-23 | 2007-01-17 | 皇家飞利浦电子股份有限公司 | Wafer with optical control modules in dicing paths |
| CN101533229A (en) * | 2008-03-10 | 2009-09-16 | 精工电子有限公司 | Reticle for projection exposure apparatus and exposure method using the same |
| CN101689540A (en) * | 2007-07-12 | 2010-03-31 | Nxp股份有限公司 | methods for manufacturing integrated circuits |
| CN104793467A (en) * | 2014-01-20 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Exposure apparatus, mask plate and exposure method |
-
2018
- 2018-06-06 CN CN201810574721.1A patent/CN108957960A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1636273A (en) * | 2001-02-27 | 2005-07-06 | 皇家菲利浦电子有限公司 | Semiconductor wafer with process control modules |
| CN1898796A (en) * | 2003-12-23 | 2007-01-17 | 皇家飞利浦电子股份有限公司 | Wafer with optical control modules in dicing paths |
| CN101689540A (en) * | 2007-07-12 | 2010-03-31 | Nxp股份有限公司 | methods for manufacturing integrated circuits |
| CN101533229A (en) * | 2008-03-10 | 2009-09-16 | 精工电子有限公司 | Reticle for projection exposure apparatus and exposure method using the same |
| CN104793467A (en) * | 2014-01-20 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Exposure apparatus, mask plate and exposure method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111929987A (en) * | 2020-09-25 | 2020-11-13 | 歌尔股份有限公司 | Nano-imprinting process monitoring device and method and nano-imprinting equipment |
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Application publication date: 20181207 |