CN108828382A

CN108828382A - Multi-chip integration test method

Info

Publication number: CN108828382A
Application number: CN201810832859.7A
Authority: CN
Inventors: 吴苑
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2018-07-26
Filing date: 2018-07-26
Publication date: 2018-11-16

Abstract

The invention discloses a kind of multi-chip integration test methods, include the following steps：One step 1, production probe card, the quantity of the probe on probe clamp cover multiple products in multi-project wafer MPW；Step 2, program end using the test program of multiple products as subprogram management below main program；It when step 3, test, is had an acupuncture treatment simultaneously multiple products in multi-project wafer MPW, by test program Row control, successively or the multiple products of selectivity test.The present invention can be effectively reduced testing cost, improve testing efficiency.

Description

Multi-chip integration test method

Technical field

The present invention relates to the wafer manufactures and testing field in semiconductor integrated circuit, more particularly to a kind of multi-chip (MPW) integration test method.

Background technique

MPW (Multi Project Wafer multi-project wafer) refers to and produces a plurality of chips on same wafer, Include multiple independent products, its purpose is to improve design efficiency, reduces cost of manufacture.

Although MPW effectively reduces the plate-making expense of designing new product chip, but since its test is usually that correspondence is more What probe card respectively tested different product chips, the test program of each product chips be also it is independent, therefore Also improve testing cost.

With the increase of the integrated level, complexity of integrated circuit, the cost of integrated circuit how is effectively reduced, becomes industry The target that unremitting effort always is pursued.Among these not only include the production development cost that reduce integrated circuit, also includes dropping The testing cost of low integrated circuit.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of multi-chip integration test method, can be effectively reduced test at This, improves testing efficiency.

In order to solve the above technical problems, multi-chip integration test method of the invention is to adopt the following technical scheme that realization 's：

One step 1, production probe card, the quantity of the probe on probe clamp cover multiple products in multi-project wafer MPW；

Step 2, program end using the test program of multiple products as subprogram management below main program；

When step 3, test, had an acupuncture treatment simultaneously multiple products in multi-project wafer MPW, by test program Row control, Successively or the multiple products of selectivity test.

Using method of the invention, it is possible to make TCH test channel be fully used, reduction probe card cost of manufacture can not With switching slide glass, different product follow-on test is realized.Therefore it can be effectively reduced testing cost, improve testing efficiency.And it is described Combined probe card can not only be used designing and developing the new product stage, and the monadic product test after can also be used as volume production makes With.

Detailed description of the invention

Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments：

Fig. 1 is the schematic layout pattern of the MPW multicore flake products；

Fig. 2 is the one embodiment flow diagram of multi-chip integration test method；

Fig. 3 is using the test program of multiple products as the flow diagram of subprogram management.

Specific embodiment

Referring to fig. 2, the multi-chip integration test method is realized in the following way in the following embodiments：

Step 1, as shown in connection with fig. 1, makes a probe card, the quantity of the probe on probe clamp covers multiple productions in MPW Product.Five products of A, B, C, D, E are shared in the embodiment shown in fig. 1, and the number of probes in made probe card should be contained Cover five products of A~E.What the small rectangle in Fig. 1 indicated is the contact pad (PAD) of each chip, i.e. the spy of chip design Needle contact area.

Step 2, as shown in connection with fig. 3, in program end using the test program of multiple products as subprogram management in main program Below.The test program of five product A, product B, products C, product D, product E products is shared in the embodiment shown in fig. 3, It regard the test program of this five products as subprogram, is managed by main program, five productions can be activated according to actual needs One or more product subprograms in product.

Step 3 can be grouped the probe in probe card according to product, and every group of probe can be adjusted up and down in height, Product probe groups without being tested raise not contact product chip.The height of separately adjustable corresponding chip test probe group, So that the probe of trial product to be measured is in needle-shaped state.Before test starts, the one or more products selected in MPW are gone out simultaneously Needle after first the connectivity of confirmation chip and test equipment meets on state, then by test program Row control, successively or selects The selected one or more products of selecting property test.

Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these It should be regarded as protection scope of the present invention.

Claims

1. a kind of multi-chip integration test method, which is characterized in that include the following steps：

2. the method as described in claim 1, it is characterised in that：Probe in probe card is grouped according to product, every group Probe can be adjusted up and down in height, and the product probe groups without being tested raise not contact product chip.

3. the method as described in claim 1, it is characterised in that：The height of separately adjustable corresponding chip test probe group, so that The probe of trial product to be measured is in needle-shaped state.

4. the method as described in claim 1, it is characterised in that：Before test starts, to one selected in multi-project wafer MPW Or multiple products needle out simultaneously, after first confirming that the connectivity of chip and test equipment meets on state, then pass through test program Row control, successively or the selected one or more products of selectivity test.