CN115101509B - Wafer structure and chip yield detection method - Google Patents

Wafer structure and chip yield detection method Download PDF

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CN115101509B
CN115101509B CN202211025890.2A CN202211025890A CN115101509B CN 115101509 B CN115101509 B CN 115101509B CN 202211025890 A CN202211025890 A CN 202211025890A CN 115101509 B CN115101509 B CN 115101509B
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chip
yield
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CN115101509A (en
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黄普嵩
冯亚
蔡信裕
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Hefei Xinjing Integrated Circuit Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

The disclosure relates to a wafer structure and a chip yield detection method, and relates to the technical field of semiconductors. The wafer structure includes: the device comprises a wafer, at least one chip and at least one test module, wherein the chip and the test module are arranged on the wafer; the chip comprises at least one module to be tested; any module to be tested corresponds to at least one test module, and the test module is used for testing the performance to be tested of the module to be tested; the test module includes: the characteristic dimension of the reference test pattern is the reference characteristic dimension; reducing the reference characteristic size relative to the characteristic size to be detected of the module to be detected according to a preset proportion; and a plurality of series of test patterns, the plurality of series of test patterns having different feature sizes, and any one of the plurality of series of test patterns having a shift in feature size from a reference feature size. The wafer structure can reduce the use number of wafers in the chip yield improvement research and development process, and is beneficial to shortening the chip yield detection time and shortening the research and development time of chip yield improvement.

Description

Wafer structure and chip yield detection method
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a wafer structure and a chip yield detection method.
Background
The yield of chips is an important economic indicator for wafer factories, and particularly in the research and development stage, the yield needs to be improved as soon as possible in order to shorten the research and development cycle.
In order to increase the yield, a lot of experiments are required in the development stage. Many experiments were conducted on the variation of the critical dimension of the pattern. To ensure that the data obtained from the experiment is reliable, it is necessary to ensure that each experimental design has enough chips on a wafer to repeat the experiment to avoid chance. Typically, each cd variation experiment is performed on each wafer individually. Therefore, several wafers are needed to verify the effect of a set of experiments, and when several wafers are produced simultaneously, the wafers are lost due to accidental accidents, so that a great amount of manpower and material resources are needed to be invested to obtain the experiment result, and the risk that the experiment result data cannot be obtained is also caused.
Therefore, it is an urgent need to solve the problem of reducing wafer usage and shortening the chip yield detection time.
Disclosure of Invention
Accordingly, there is a need for a wafer structure and a method for detecting a chip yield, which can reduce the number of wafers used in a development process of improving the chip yield, and is beneficial to shortening the chip yield detection time and the development time of improving the chip yield.
The application provides a wafer structure, its characterized in that includes: the device comprises a wafer, at least one chip and at least one test module, wherein the chip and the test module are arranged on the wafer; the chip comprises at least one module to be tested; any module to be tested corresponds to at least one test module, and the test module is used for testing the performance to be tested of the module to be tested; the test module includes: the characteristic dimension of the reference test pattern is a reference characteristic dimension; reducing the reference characteristic size relative to the characteristic size to be detected of the module to be detected according to a preset proportion; and a plurality of series of test patterns, the plurality of series of test patterns having different feature sizes, and any one of the plurality of series of test patterns having a shift in feature size from a reference feature size.
Above-mentioned wafer structure, reduce according to the preset proportion through the characteristic dimension with the benchmark test pattern for the characteristic dimension that awaits measuring of module that awaits measuring for the area that the benchmark test pattern took up on the wafer reduces, in addition, under the characteristic dimension of benchmark test pattern reduces, the characteristic dimension of other a plurality of series test patterns also correspondingly reduces, make the area that other a plurality of series test patterns took up on the wafer also reduce, the occupation area of test pattern on the wafer has been reduced to the event this wafer structure, that is, the occupation area of test module on the wafer has been reduced. Therefore, the wafer structure can realize that more test patterns are placed on one wafer, namely more test modules are placed, and the problem of wafer waste caused by the fact that each module to be tested needs one wafer to complete testing in the prior art is solved, so that the wafer structure saves the use of the wafer, the manpower and material resource investment for producing the wafer can be greatly reduced, and the research and development time for improving the yield of the chip is shortened.
Optionally, in any test module, the plurality of series of test patterns includes: a plurality of first series of test patterns having a feature size smaller than the reference feature size, and a plurality of second series of test patterns having a feature size larger than the reference feature size; wherein the feature sizes of the plurality of first series of test patterns are reduced in equal gradient relative to the reference feature size; the feature sizes of the plurality of second series of test patterns increase in equal gradient relative to the reference feature size.
In the wafer structure, any test module designs a plurality of series of test patterns on the basis of the reference characteristic pattern, and the plurality of series of test patterns can be divided into a plurality of first series of test patterns and a plurality of second series of test patterns according to the variation trend of the characteristic dimension relative to the characteristic dimension of the reference test pattern. In this way, the feature sizes of the first series of test patterns are reduced relative to the equal gradient of the reference feature size, the feature sizes of the second series of test patterns are increased relative to the equal gradient of the reference feature size, and the test results which are obtained by taking the test result of the reference feature pattern as the reference result and uniformly changing along the change directions of different feature sizes can be obtained, so that the test precision and the reliability of the analysis result according to the test result can be ensured.
Optionally, the number of the test modules is multiple; the module to be tested has a plurality of performances to be tested; any module to be tested corresponds to a plurality of test modules, wherein different test modules are different in test performance to be tested.
In the wafer structure, a plurality of test modules can be correspondingly arranged for each module to be tested, so that independent tests of a plurality of performances to be tested can be carried out on any module to be tested. Therefore, after the plurality of test modules corresponding to each performance to be tested are arranged on the same wafer, the same wafer is convenient to test the same module to be tested on a plurality of different performances to be tested, so that the yield of the module to be tested is conveniently comprehensively determined according to a plurality of test results, the yield of the chip is further determined, the test efficiency of the yield of the chip is improved, and the research and development time for improving the yield of the chip is effectively shortened.
Optionally, the chip comprises a logic chip; the module to be tested comprises a static random access module.
In the wafer structure, the static random access module is used as an important structure influencing the yield of the logic chip. After the to-be-tested performance of the static random access module is tested through the plurality of test modules, the yield of the static random access module can be determined, and then the yield of the logic chip is determined.
Optionally, a test accommodating area is arranged on the chip, and at least part of the test modules are arranged in the test accommodating area; and/or, the periphery of the chip is provided with a cutting channel, and at least part of the test module is arranged in the cutting channel.
In the wafer structure, the test accommodating area can be arranged on the chip, so that at least part of test modules can be placed in the test accommodating area of the chip, and the problem that the test modules cannot be placed on a cutting path when the number of the test modules is large or the occupied area of test patterns is large is solved.
Based on the same inventive concept, the application also provides a chip yield detection method which is applied to the wafer structure in any one of the schemes; the detection method comprises the following steps: selecting a test module prepared on the same wafer as a target test module to test according to the performance to be tested of the module to be tested; obtaining test results corresponding to the reference test pattern and the series of test patterns in the target test module respectively so as to determine the yield of each test pattern in the target test module according to the test results; determining the yield of the module to be tested according to the yield of each test pattern in the target test module; and determining the yield of the chip according to the yield of the module to be tested.
In the above chip yield detection method, by applying to the wafer structure according to any of the above schemes, the feature size of the reference test pattern is reduced according to a preset proportion relative to the feature size to be tested of the module to be tested, and further the area occupied by the reference test pattern on the wafer is reduced. Therefore, in the chip yield detection method, more test patterns can be placed on one wafer, namely more test modules can be placed, so that the test of a plurality of test patterns in the target test module corresponding to the module to be tested can be conveniently completed by using one wafer, the yield of the target test module can be determined according to the test result of each test pattern, and the yield of the module to be tested and the yield of the chips can be further determined. The chip yield detection method can greatly reduce the manpower and material resource input of wafer production and shorten the research and development time for improving the chip yield.
Optionally, the chip yield detection method further includes: and analyzing the failure type of the module to be tested according to the test results respectively corresponding to the reference test pattern and the series of test patterns in the target test module.
According to the chip yield detection method, the failure type of the module to be tested can be determined according to the test result analysis through the test results corresponding to the reference test pattern and the series of test patterns in the target test module, and then the failure type of the chip is determined, so that data support is provided for research and development of chip yield improvement.
Optionally, the module to be tested has a plurality of performances to be tested, and any module to be tested corresponds to a plurality of test modules, wherein different test modules have different performances to be tested for testing; the chip yield detection method further comprises the following steps: respectively testing the test modules corresponding to the performances to be tested so as to determine the yield of the modules to be tested on a plurality of different performances to be tested; and comprehensively determining the yield of the module to be tested according to the yields of the module to be tested on a plurality of different performances to be tested.
Optionally, the module under test includes a static random access module; the properties to be measured include: gate threshold voltage, leakage current, or saturation current.
In the chip yield detection method, more test modules can be placed on one wafer for any module to be tested, that is, the test of the same module to be tested on multiple performances to be tested, such as the performance test of gate threshold voltage, leakage current or saturation current, can be completed on one wafer. Therefore, the yield of the module to be tested can be comprehensively determined conveniently according to the multi-aspect test results, the yield of the chip can be further determined, the chip yield test efficiency can be improved, and the research and development time for improving the chip yield can be effectively shortened.
Optionally, the chip yield detection method further includes: and analyzing and determining the failure type of the module to be tested and the weight of each failure type relative to the yield of the module to be tested according to the test results respectively corresponding to the reference test pattern and the series of test patterns in each target test module.
In the chip yield detection method, the failure type of the test module and the weight of each failure type relative to the yield of the module to be tested can be analyzed and determined according to the test result of each test pattern in the target test module, so that the failure reasons of the module to be tested and the chip can be more accurately analyzed, and the research and development time for improving the yield of the chip can be further shortened.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a wafer structure provided in an embodiment;
FIG. 2 is a schematic diagram of another wafer structure provided in an embodiment;
fig. 3 is a schematic structural diagram of a chip structure provided in an embodiment;
FIG. 4 is a schematic diagram of another chip structure provided in an embodiment;
fig. 5 is a flowchart of a chip yield detection method according to an embodiment.
Description of the reference numerals:
10-a wafer; 20-chip; 21-a module to be tested; 22-a test accommodation zone; 23-cutting a street; 24-a device integration region; 30-a module to be tested; 31-benchmark test pattern; 32-series test patterns; 321-a first series of test patterns; 322-second series of test patterns.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Embodiments of the present disclosure are presented in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the disclosure. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," or "having," and the like, specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, as used in this specification, the term "and/or" includes any and all combinations of the associated listed items.
The yield of chips is an important economic indicator of a wafer foundry, and particularly, in order to shorten the research and development period in the research and development stage, the yield needs to be increased as soon as possible.
In order to increase the yield, a lot of experiments are required in the development stage. Many experiments were conducted on the variation of the critical dimension of the pattern. In order to ensure that the data obtained by the experiment is reliable, it is necessary to ensure that each experimental design has enough chips on one wafer to repeat the experiment to avoid contingency. Typically, each cd variation experiment is performed on each wafer individually. However, in the process development stage, since many small chips which cannot have independent functions are integrated and placed on one chip, the number of chips on a wafer developed is small. Therefore, several wafers are needed to verify the effect of a set of experiments, and when several wafers are produced simultaneously, the wafers are lost due to accidental accidents, so that a great amount of manpower and material resources are needed to be invested to obtain the experiment result, and the risk that the experiment result data cannot be obtained is also caused. The static random access memory is used as an important structure influencing the yield of a logic chip, and the improvement effect is often confirmed by experiments, so that the yield improvement progress is greatly influenced.
Therefore, research and development for reducing the manpower and material resources for wafer production and shortening the yield are needed to solve the problems.
In view of the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a wafer structure and a method for detecting a chip yield, so as to reduce the number of wafers used in a development process of improving the chip yield, and facilitate shortening the chip yield detection time and the development time of improving the chip yield.
Referring to fig. 1, an embodiment of the present application provides a wafer structure, including: a wafer 10, and at least one chip 20 and at least one test module 30 disposed on the wafer 10; the chip 20 comprises at least one module under test 21; any module to be tested 21 corresponds to at least one test module 30, and the test module 30 is used for testing the performance to be tested of the module to be tested 21; the test module 30 includes: a reference test pattern 31, wherein the characteristic dimension of the reference test pattern 31 is a reference characteristic dimension; the reference characteristic size is reduced relative to the characteristic size to be measured of the module to be measured 21 according to a preset proportion; and a plurality of series of test patterns 32, the plurality of series of test patterns 32 having different feature sizes, and any one of the series of test patterns 32 having a shift in feature size from a reference feature size.
Here, it can be understood that, at a fixed wafer 10 size, the preset ratio is determined comprehensively according to the feature size to be tested of the module to be tested 21, the number of the test modules 30, and the number of each test pattern (including the reference test pattern and the series of test patterns) in the test module 30. For example, the greater the number of each test pattern in the test module 30, the smaller the preset proportion, the smaller the reference feature size; in the case of a reduced reference feature size, the feature size corresponding to each series of test patterns 32 is also reduced to ensure that all of the test patterns can be placed on the wafer 10. Alternatively, the preset proportion can be selected and set according to the test requirement.
In the wafer structure, the area occupied by the reference test pattern 31 on the wafer 10 is reduced by reducing the feature size of the reference test pattern 31 relative to the feature size to be tested of the module to be tested 21 according to the preset proportion, and in addition, when the feature size of the reference test pattern 31 is reduced, the feature sizes of the other series of test patterns 32 are correspondingly reduced, so that the area occupied by the other series of test patterns 32 on the wafer 10 is also reduced, and therefore, the wafer structure 10 reduces the area occupied by the test patterns on the wafer, that is, the area occupied by the test module 30 on the wafer 10. Therefore, the wafer structure can realize that more test patterns are placed on one wafer 10, that is, more test modules 30 are placed, and the problem of waste of the wafer 10 caused by the fact that each module to be tested 21 needs one wafer 10 to complete testing in the prior art is solved, so that the wafer structure saves the use of the wafer 10, the manpower and material resource investment for producing the wafer 10 can be greatly reduced, and the research and development time for improving the yield of the chips 20 is shortened.
Here, it should be noted that, in the wafer structure shown in fig. 1 and fig. 2, only one chip 20 is provided on the wafer 10 as an example, but it is not intended that only one chip 20 is provided on the wafer 10. That is, more chips 20 and test modules 30 can be arranged on the wafer 10 according to the arrangement of the chips 20 and the corresponding test modules 30. The number of chips 20 on the wafer 10 is not limited in the embodiments of the present application.
In some examples, with continued reference to fig. 1, in any test module 30, the plurality of test patterns 32 includes: a plurality of first series of test patterns 321 having a feature size smaller than a reference feature size, and a plurality of second series of test patterns 322 having a feature size larger than the reference feature size; wherein the feature sizes of the plurality of first series of test patterns 321 are reduced in equal gradient with respect to the reference feature size; the feature sizes of the plurality of second series of test patterns 322 increase in equal gradient with respect to the reference feature size.
In the wafer structure, a plurality of series of test patterns 32 are designed on the basis of the reference feature pattern 31 for any test module 30, and the plurality of series of test patterns 32 can be divided into a plurality of first series of test patterns 321 and a plurality of second series of test patterns 322 according to the variation trend of the feature size relative to the feature size of the reference test pattern 31. In this way, the feature sizes of the first series of test patterns 321 are decreased in gradient with respect to the standard feature size, and the feature sizes of the second series of test patterns 322 are increased in gradient with respect to the standard feature size 31, so that test results obtained by uniformly changing the test results of the standard feature pattern 31 in different feature size changing directions can be obtained, thereby ensuring the test accuracy and the reliability of the analysis results based on the test results.
In some examples, referring to fig. 2, the number of the test modules 30 is plural; the module to be tested 21 has a plurality of performances to be tested; any module under test 21 corresponds to a plurality of test modules 30, wherein different test modules 30 have different test performances for testing.
It should be noted that different performances to be tested can be tested by controlling different experimental conditions, for example, one performance to be tested can be embodied by one experimental condition. Thus, the test module 30 can be designed to match the experimental conditions of the performance to be tested.
In the wafer structure, a plurality of test modules 30 may be correspondingly disposed for each module to be tested 21, so as to perform independent tests on a plurality of performances to be tested for any module to be tested 21. Therefore, after the plurality of test modules 30 corresponding to each performance to be tested are arranged on the same wafer 10, the same wafer 10 is convenient to test the same module 21 to be tested on a plurality of different performances to be tested, so that the yield of the module 21 to be tested is conveniently determined comprehensively according to a plurality of test results, the yield of the chip 20 is further determined, the test efficiency of the yield of the chip 20 is improved, and the research and development time for improving the yield of the chip 20 is effectively shortened.
Optionally, the performance to be measured includes: the gate threshold voltage, the leakage current, or the saturation current, and the performance to be measured may further include a voltage at a specific current, and the like, which is not limited in the embodiment of the present application. Accordingly, the experimental condition corresponding to the performance to be measured may be at least one of an active region critical dimension, a gate critical dimension, an offset between an active region symmetry axis and a gate symmetry axis, an N-well dimension, or a P-well dimension, for example. The embodiment of the present application does not limit this, and the setting may be specifically selected according to the test requirement.
In some examples, chip 20 comprises a logic chip; the module under test 21 comprises a static random access module.
Optionally, the logic chip includes a main chip and a plurality of functionally independent sub-chips integrated on the main chip.
In the wafer structure, the sram module is used as an important structure that affects the yield of the logic chip, and after the performance to be tested of the sram module is tested by the plurality of test modules 30, the yield of the sram module can be determined, and thus the yield of the logic chip can be determined.
For example, taking the chip 20 as a logic chip and the module under test 21 as a sram module as an example, in order to obtain the yield data of the largest number of sram modules with the least investment, a plurality of test modules 30 for the sram modules may be designed within one wafer 10, so that each test module 30 designs a corresponding reference test pattern 31 and a plurality of series of test patterns 32 for one experimental condition, and thus can be used for testing the corresponding performance under test. In any test module 30, the area of each test pattern may be designed according to the area actually allowed to be reserved for the wafer 10. Thus, by testing the yield conditions of the test patterns in the test module 30 corresponding to different experimental conditions on one wafer 10, the yield influence of the different experimental conditions on the sram module can be preliminarily known, and further the yield influence of the different experimental conditions on the whole logic chip can be known.
Referring to table 1, table 1 exemplarily shows several experimental conditions for a corresponding design test module 30. Matching the experimental conditions given in table 1, the plurality of test modules 30 may be, for example: the characteristic dimension of a series of test patterns can be increased by 4nm to 8nm relative to the equal gradient of the reference characteristic dimension and reduced by 4nm to 8nm relative to the equal gradient of the reference characteristic dimension; the characteristic dimension of a series of test patterns can be increased by 4nm to 8nm relative to the equal gradient of the reference characteristic dimension and reduced by 4nm to 8nm relative to the equal gradient of the reference characteristic dimension; the characteristic dimension of a series of test patterns can be increased by 4nm to 8nm in a gradient manner relative to the standard characteristic dimension and the like, and can be reduced by 4nm to 8nm in a gradient manner relative to the standard characteristic dimension and the like; the characteristic dimension of a series of test patterns can be increased by 4nm to 8nm relative to the equal gradient of the reference characteristic dimension and reduced by 4nm to 8nm relative to the equal gradient of the reference characteristic dimension; and the characteristic dimension of a series of test patterns can be increased by 4nm to 8nm relative to the equal gradient of the reference characteristic dimension and reduced by 4nm to 8nm relative to the equal gradient of the reference characteristic dimension.
In addition, the specific experimental conditions in some embodiments of the present application may also be other items related to the sram module, which may be affected by the size, and are not limited to the items listed in the table.
TABLE 1 Parametric change scales for different experimental conditions
Figure 536688DEST_PATH_IMAGE002
In some examples, referring to fig. 3, a test accommodating area 22, such as the area a and the area B in fig. 3, is disposed on the chip 20, and at least a part of the test modules 30 are disposed in the test accommodating area 22; and/or, a cutting channel 23 is disposed on the periphery of the chip 20, and at least a part of the test module 30 is disposed in the cutting channel 23. The partial test modules 30 disposed in the scribe line 23 may include a reference test pattern 31, or may include any series of test patterns 32.
It should be understood that the present disclosure may be implemented in various ways for the position of the test module 30 on the wafer 10, for example, the test module 30 may be integrated in the idle area of the chip 20 to use the idle area as the test accommodating area 22; alternatively, the test module 30 may be disposed in the scribe line 23 at the periphery of the chip 20; alternatively, the test module 30 may also be disposed in the chip 20 and other areas around the scribe line; and so on.
In an example where the chip 20 is a logic chip, the logic chip includes a main chip and a plurality of functionally independent sub-chips integrated on the main chip. The chip of the test module 30 may be, for example, the master chip. In this way, the main chip may have a device integration region 24 besides the test accommodation region 22 for binding each sub-chip or other functional devices. For example, as shown in the areas a to e in fig. 3, the specific number and distribution of the device integration areas 24 may be designed according to actual requirements, which is not limited in the embodiment of the present application.
In the wafer structure, at least a part of the test modules 30 may be placed in the test accommodating area 22 of the chip 20, so as to solve the problem that the test modules cannot be placed on the scribe line when the number of the test modules is large or the area occupied by the test patterns is large.
For example, in the development stage of a logic chip, a chip may be generally divided into several regions, please refer to fig. 4, and the chip 20 is divided into 19 regions, for example; wherein, the areas A-D can be designed as the test accommodation area 22 for placing the test module 30; the a-region to the p-region can be designed as a device integration region 24 for bonding devices (e.g., chiplets or other functional devices).
In addition, a scribe line 23 is formed on the periphery of the chip 20, and at least a portion of the test module 30 (e.g., a portion of the pattern) may be disposed in the scribe line 23.
It can be understood that a great deal of test patterns need to be designed in the development stage of the logic chip, in order to: according to the test patterns matched with different experimental conditions, the performance to be tested of the same module to be tested 21 in multiple aspects can be tested respectively, so that the design windows of the process and the device can be obtained in advance according to the test results, and the problem that the traditional test patterns only focus on single characteristics but do not focus on the influence of the experimental design on the yield of the whole chip is solved. On the basis, in the subsequent mass production stage of the chips, only a small number of test patterns which are the same as mass production standard conditions need to be selected and arranged on the wafer.
Based on the same inventive concept, referring to fig. 5, the present application further provides a method for detecting a chip yield, which is applied to the wafer structure in any of the above embodiments. The detection method comprises the following steps.
S10: and selecting the test module prepared on the same wafer as a target test module to test according to the performance to be tested of the module to be tested.
S20: and obtaining test results corresponding to the benchmark test pattern and the series of test patterns in the target test module respectively so as to determine the yield of each test pattern in the target test module according to the test results.
S30: and determining the yield of the module to be tested according to the yield of each test pattern in the target test module.
S40: and determining the yield of the chip according to the yield of the module to be tested.
In the above chip yield detection method, by applying to the wafer structure according to any of the above schemes, the feature size of the reference test pattern is reduced according to a preset proportion relative to the feature size to be tested of the module to be tested, and further the area occupied by the reference test pattern on the wafer is reduced. Therefore, in the chip yield detection method, more test patterns can be placed on one wafer, namely more test modules are placed, so that the test of a plurality of test patterns in the target test module corresponding to the module to be tested can be conveniently completed by using one wafer, the yield of the target test module is determined according to the test result of each test pattern, and the yield of the module to be tested and the yield of the chip are further determined. The chip yield detection method can greatly reduce the manpower and material resource input of wafer production and shorten the research and development time for improving the chip yield.
In step S10, according to the performance to be tested of the module to be tested, the test module prepared on the same wafer is selected as the target test module for testing.
For example, a Static Random-Access Memory (SRAM) is an important structure that affects the yield of logic chips, and therefore, in order to detect the yield of logic chips, the SRAM can be used as a module to be tested. In addition, the critical dimension of the lower part of the contact hole has influence on the yield of the SRAM, so that contact hole patterns with different dimensions of the SRAM can be used as a test module for testing.
In step S20, test results corresponding to the reference test pattern and the plurality of series test patterns in the target test module are obtained, so as to determine the yield of each test pattern in the target test module according to the test results.
Illustratively, the reference test pattern is an SRAM contact hole pattern with a reference size, the plurality of series test patterns are SRAM contact hole patterns with +/-8 nm on the basis of the reference size, and after the wafer is completely processed, the yield corresponding to each SRAM contact hole pattern is obtained.
In step S30, the yield of the module to be tested is determined according to the yields of the test patterns in the target test module.
Illustratively, according to the yield of each SRAM contact hole pattern, the yield of the corresponding SRAM is determined.
In step S40, the yield of the chip is determined according to the yield of the module to be tested.
Illustratively, the yield of the logic chip is determined according to the yield of the SRAM.
In some examples, the chip yield detection method further comprises: and analyzing the failure type of the module to be tested according to the test results respectively corresponding to the reference test pattern and the series of test patterns in the target test module.
According to the chip yield detection method, the failure type of the module to be tested can be determined according to the test result analysis through the test results corresponding to the reference test pattern and the series of test patterns in the target test module, and then the failure type of the chip is determined, so that data support is provided for research and development of chip yield improvement.
In some examples, the module under test has a plurality of performances under test, and any module under test corresponds to a plurality of test modules, wherein the performances under test for testing are different for different test modules; the chip yield detection method further comprises the following steps: respectively testing the test modules corresponding to the performances to be tested so as to determine the yield of the modules to be tested on a plurality of different performances to be tested; and comprehensively determining the yield of the module to be tested according to the yields of the module to be tested on a plurality of different performances to be tested.
In some examples, the module under test comprises a static random access module; the properties to be measured include: the gate threshold voltage, the leakage current, or the saturation current, and the performance to be measured may further include a voltage at a specific current, and the like, which is not limited in the embodiment of the present application.
In the chip yield detection method, more test modules can be placed on one wafer for any module to be tested, that is, the test of the same module to be tested on multiple performances to be tested, such as the performance test of gate threshold voltage, leakage current or saturation current, can be completed on one wafer. Therefore, the yield of the module to be tested can be comprehensively determined conveniently according to the multi-aspect test results, the yield of the chip can be further determined, the chip yield test efficiency can be improved, and the research and development time for improving the chip yield can be effectively shortened.
In some examples, the chip yield detection method further comprises: and analyzing and determining the failure type of the module to be tested and the weight of each failure type relative to the yield of the module to be tested according to the test results respectively corresponding to the reference test pattern and the series of test patterns in each target test module.
In the chip yield detection method, the failure type types of the test module and the weight of each failure type relative to the yield of the module to be tested can be analyzed and determined according to the test result of each test pattern in the target test module, so that the failure reasons of the module to be tested and the chip can be analyzed more accurately, and the research and development time for improving the yield of the chip can be further shortened.
In the description of the present specification, various technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments are not described, but should be considered as being within the scope of the description, as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present disclosure, and the description thereof is specific and detailed, but not construed as limiting the scope of the claims. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the concept of the present disclosure, and these changes and modifications are all within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the appended claims.

Claims (10)

1. A wafer structure, comprising: the device comprises a wafer, at least one chip and at least one test module, wherein the chip and the test module are arranged on the wafer; the chip comprises at least one module to be tested; any module to be tested corresponds to at least one test module, and the test module is used for testing the performance to be tested of the module to be tested;
the test module includes:
the characteristic dimension of the reference test pattern is a reference characteristic dimension; the reference characteristic size is reduced relative to the characteristic size to be detected of the module to be detected according to a preset proportion;
and a plurality of series of test patterns, the plurality of series of test patterns having different feature sizes, and any one of the plurality of series of test patterns having a feature size offset from the reference feature size.
2. The wafer structure of claim 1, wherein in any of the test modules, the plurality of test patterns comprises: a plurality of first series of test patterns having a feature size smaller than the reference feature size, and a plurality of second series of test patterns having a feature size larger than the reference feature size;
wherein the feature sizes of the plurality of first series of test patterns are reduced in equal gradient relative to the reference feature size; the feature sizes of the plurality of second series of test patterns increase in equal gradient relative to the reference feature size.
3. The wafer structure of claim 1, wherein the number of the test modules is plural; the module to be tested has a plurality of performances to be tested; any module to be tested corresponds to a plurality of test modules, wherein different test modules are used for testing different performance to be tested.
4. The wafer structure of claim 1, wherein the chips comprise logic chips; the module to be tested comprises a static random access module.
5. The wafer structure of any one of claims 1~4,
the chip is provided with a test accommodating area, and at least part of the test module is arranged in the test accommodating area; and/or the presence of a gas in the gas,
the periphery of the chip is provided with a cutting channel, and at least part of the test module is arranged in the cutting channel.
6. A chip yield detection method, which is applied to the wafer structure of any one of claims 1~4; the detection method comprises the following steps:
selecting the test module prepared on the same wafer as a target test module to test according to the performance to be tested of the module to be tested;
obtaining test results corresponding to the reference test pattern and the series of test patterns in the target test module respectively, and determining the yield of each test pattern in the target test module according to the test results;
determining the yield of the module to be tested according to the yield of each test pattern in the target test module;
and determining the yield of the chip according to the yield of the module to be tested.
7. The method of claim 6, further comprising:
and analyzing the failure type of the module to be tested according to the test results respectively corresponding to the reference test pattern and the series of test patterns in the target test module.
8. The method of claim 6, wherein the module under test has a plurality of performance levels, and any module under test corresponds to a plurality of test modules, wherein the performance levels for testing are different for different test modules;
the chip yield detection method further comprises the following steps:
respectively testing the test modules corresponding to the performances to be tested so as to determine the yield of the modules to be tested on a plurality of different performances to be tested;
and comprehensively determining the yield of the module to be tested according to the yields of the module to be tested on a plurality of different performances to be tested.
9. The method of claim 8, further comprising:
and analyzing and determining the failure type types of the module to be tested and the weight of each failure type relative to the yield of the module to be tested according to the test results respectively corresponding to the reference test pattern and the series of test patterns in each target test module.
10. The method of any of claims 6~9 wherein the module under test comprises a static random access module; the performance to be tested comprises: gate threshold voltage, leakage current, or saturation current.
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