CN108919974B

CN108919974B - Matrix type keyboard state identification and coding method

Info

Publication number: CN108919974B
Application number: CN201810591942.XA
Authority: CN
Inventors: 凌云; 周维龙; 郭艳杰
Original assignee: Hunan University of Technology
Current assignee: Hunan University of Technology
Priority date: 2016-01-05
Filing date: 2016-01-05
Publication date: 2023-01-10
Anticipated expiration: 2036-01-05
Also published as: CN108847847A; CN108919974A; CN105700698A; CN105700698B; CN108847847B

Abstract

A matrix keyboard state identification and coding method is realized by a circuit consisting of a matrix keyboard, a first buffer register, a second buffer register and a coder, the matrix keyboard comprising X rows and Y columns outputs N-bit keyboard state signals, the buffer register is controlled by clock pulses to carry out secondary buffer latch on the N-bit keyboard state signals, data output by primary buffer is a current state key value, and data output by secondary buffer is a previous state key value; the present state key value and the previous state key value jointly form a 2 multiplied by N state code; encoding the status code and outputting a key number; different single key operation, combined key operation and keyboard maintenance state operation are only reflected on the difference of the state codes; if the key operation function needs to be increased or decreased or adjusted, the circuit structure does not need to be modified, and the encoding content of the encoder only needs to be changed according to the corresponding relation between the increased or decreased state code and the key number. The method does not need to write and run programs and works reliably.

Description

Matrix type keyboard state identification and coding method

The invention discloses a matrix type keyboard state identification and coding circuit, which is a divisional application, has an original application number of 201610004249.9 and an application date of 2016, 1 and 5.

Technical Field

The invention relates to a scanning and positioning method of a keyboard, in particular to a matrix type keyboard state identification and coding method.

Background

With the continuous development of embedded technology, various electronic products generally adopt a microcontroller as a control core and a keyboard as a main input device, and are widely applied.

The existing keyboard scanning is mainly controlled by a microcontroller, and is performed by running a program in the microcontroller, so that the program runs off due to interference, and the scanning program cannot work normally.

The invention patent with application number CN201010153560.2, a fast scanning and positioning method for matrix keyboard, adopts a keyboard interrupt triggering mode to enter a keyboard scanning and positioning process, adopts a method of repeating the keyboard scanning step for multiple times to judge whether the key is valid, and judges the state of the obtained key value; if the multiple sampling states are the same, the key value is in a stable state and is valid; if the multiple sampling states are different, the key value is invalid. The single key operation or the combined key operation needs to be judged separately, if the single key operation is carried out, the single key processing mode is entered; if the operation is a combination key operation, a combination key processing mode is entered. The method described in this patent solves the problem of errors such as wrong keys, continuous touch keys, etc. caused by keyboard shaking due to the mechanical properties of the keyboard itself, as well as the problem of support for combination keys and repeated keys. But the single key operation and the combined key operation of the method need to be processed respectively; a keyboard operation function of executing effective operation after a certain period of time of maintaining the keyboard state is not considered; when the key operation function is increased or decreased or adjusted, the structure of the keyboard scanning and positioning program needs to be modified.

Disclosure of Invention

In order to solve the technical problems of the existing keyboard scanning and positioning method, the invention provides a matrix type keyboard state identification and coding method, which comprises the steps that a matrix type keyboard with an X row-Y column key matrix outputs N-bit keyboard state signals, and N = X + Y; the clock pulse control buffer register performs secondary buffer latch on the N-bit keyboard state signal, data output by the primary buffer is a current state key value, and data output by the secondary buffer is a previous state key value; the present state key value and the previous state key value jointly form a 2 multiplied by N state code; encoding the status code and outputting a key number; the N-bit keyboard state signal is a level signal.

The current state key value of the N-bit keyboard state signal is the N-bit keyboard state signal at the effective triggering edge moment of the clock pulse, and the previous state key value of the N-bit keyboard state signal is the N-bit keyboard state signal at the effective triggering edge moment of the clock pulse; the clock pulse effective triggering edge is the rising edge of the clock pulse; the clock pulse active trigger edge is either a falling edge of the clock pulse.

The state code consists of an effective state code and an invalid state code and is used for identifying the current state and the operation state of the matrix keyboard; the key number is composed of a valid key number and an invalid key number; the effective state code is generated by the operation or the state of an effective keyboard, and a corresponding effective key number is correspondingly output; the invalid state code is generated by invalid keyboard operation or state and correspondingly outputs an invalid key number; the key number is M bits, and the selection of the M value should satisfy 2 ^M Greater than or equal to the sum of the number of valid key numbers and invalid key numbers.

The effective keyboard operation comprises single-key pressing operation, single-key releasing operation, single-key pressing maintaining operation and combined key operation; the combined key operation refers to the operation that after a single key is pressed down, other keys are pressed down; the invalid keyboard operation is an operation other than the valid keyboard operation.

The encoding of the state code and the output of the key number are realized by an encoder. When all invalid state codes are input by the encoder, the invalid key number is correspondingly output, and the invalid key number is a value except all valid key numbers. Furthermore, the encoder is a read only memory, and the key operation function is increased or decreased or adjusted by modifying the storage content of the read only memory.

The method for controlling the buffer register by the clock pulse to carry out secondary buffer latch on the N-bit keyboard state signal is realized by a first buffer register and a second buffer register; the first buffer register and the second buffer register are both N-bit binary registers; the N-bit data input end of the first buffer register is connected to the N-bit keyboard state signal output end, and the N-bit data input end of the second buffer register is connected to the N-bit data output end of the first buffer register; and the receiving pulse input end of the first buffer register and the receiving pulse input end of the second buffer register are both connected to a clock pulse.

The X row lines and the Y column lines of the matrix keyboard are connected with pull-up resistors, and the X row lines and the Y column lines are controlled to be in a low-level state alternately by sampling pulses; the Y row line state when the X row lines are at a low level is latched to obtain a Y-bit row state signal, and the X row line state when the Y row lines are at a low level is latched to obtain an X-bit row state signal; the X-bit row state signal and the Y-bit column state signal jointly form an N-bit keyboard state signal.

The sampling pulse controls X row lines and Y column lines to be alternately in a low level state, and the low level state is realized by a row tri-state buffer and a column tri-state buffer; the row lines of all the key matrixes are respectively connected to the output ends of the row three-state buffers, and the column lines of all the key matrixes are respectively connected to the output ends of the column three-state buffers; all input ends of the row tri-state buffer and the column tri-state buffer are connected to a low level; the row tri-state buffer is enabled at the low level of the sampling pulse and the column tri-state buffer is enabled at the high level of the sampling pulse, or the row tri-state buffer is enabled at the high level of the sampling pulse and the column tri-state buffer is enabled at the low level of the sampling pulse.

The Y-bit row state signal is obtained by latching the Y-column line state when the X-column lines are at a low level, and the X-bit row state signal is obtained by latching the X-column line state when the Y-column lines are at a low level, wherein the Y-bit row state signal is realized by a row state register and a column state register; the row lines of all the key matrixes are respectively connected to the input end of the row state register, and the column lines of all the key matrixes are respectively connected to the input end of the column state register; when the row tri-state buffer enables the effective low level of the sampling pulse and the column tri-state buffer enables the effective high level of the sampling pulse, the column state register performs data latch on the rising edge of the sampling pulse, and the row state register performs data latch on the falling edge of the sampling pulse; when the row three-state buffer is enabled to be effective at the high level of the sampling pulse and the column three-state buffer is enabled to be effective at the low level of the sampling pulse, the column state register performs data latch at the falling edge of the sampling pulse, and the row state register performs data latch at the rising edge of the sampling pulse.

The N bit, the 2 XN bit and the M bit are all binary bits; the period of the clock pulse is 20-100 ms; the period of the sampling pulse is not greater than the period of the clock pulse, and a specific example thereof is to use a clock pulse as a sampling pulse at the same time.

The matrix type keyboard state identification and coding method is realized by a matrix type keyboard state identification and coding circuit. The matrix keyboard, the first buffer register, the second buffer register and the encoder form a matrix keyboard state identification and encoding circuit.

Further, when the output key number is changed, a keyboard state change pulse is output. The matrix type keyboard state identification and coding circuit further comprises a keyboard state change pulse generating unit, wherein the keyboard state change pulse is output by a keyboard state change pulse generating unit consisting of an OR gate, an M-bit delay buffer and M XOR gates; the M-bit delay buffer is used for respectively carrying out signal delay on the M-bit key numbers output by the matrix keyboard; the inputs of the M exclusive-OR gates are input signals and output signals of the M-bit delay buffer respectively; the outputs of the M exclusive-OR gates are respectively connected to the input ends of the OR gates; the output end of the OR gate outputs a keyboard state change pulse.

The matrix type keyboard state identification and coding circuit further comprises an oscillator; the oscillator outputs a clock pulse and a sampling pulse.

The invention has the beneficial effects that: the single key operation, the combination key operation and the keyboard maintenance state operation are positioned and converted into state codes with the same binary length by clock pulse scanning, and are processed by adopting a uniform coding mode, wherein the single key operation, the combination key operation and the keyboard maintenance state operation are only reflected on the difference of the state codes; if the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the circuit structure does not need to be modified, and the encoding content of the encoder only needs to be changed according to the corresponding relation between the increased or decreased state code and the key number, namely the storage content written into the read-only memory is modified again. The method does not use microcontrollers such as a singlechip and an ARM, does not need running programs, and works reliably.

Drawings

FIG. 1 is a schematic block diagram of a matrix keyboard status recognition and encoding circuit;

FIG. 2 is a circuit diagram of a matrix keyboard according to an embodiment of the present invention;

FIG. 3 is a scan positioning circuit diagram according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention;

FIG. 5 is a waveform diagram illustrating the effective operation of the keyboard according to the embodiment of the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a schematic block diagram of a matrix keyboard status recognition and encoding circuit, which comprises a matrix keyboard 400, a first buffer 100, a second buffer 200, an encoder 300, and an oscillator 500.

The oscillator 500 is a multivibrator having a CP clock output terminal and a CK sampling pulse output terminal, the period of the CP clock is 20-100ms, and the period of the CK sampling pulse is not greater than the period of the CP clock.

Fig. 2 is a circuit diagram of a matrix keyboard 400 according to an embodiment of the present invention, which has 2 rows, 2 columns and 4 keys, and is composed of a key S1, a key S2, a key S3, a key S4, a pull-up resistor R1, a pull-up resistor R2, a pull-up resistor R3, a pull-up resistor R4 connected to a power supply + VCC, a row tri-state buffer 401, a column tri-state buffer 402, a row state register 403, and a column state register 404. 2 output ends Y1 and Y2 of the row tri-state buffer 401 are respectively connected to 2 row lines, and 2 output ends Y3 and Y4 of the column tri-state buffer 402 are respectively connected to 2 column lines; all the input terminals X1 to X4 of the row tri-state buffer 401 and the column tri-state buffer 402 are connected to the low level.

2 input ends D41 and D42 of the row status register 403 are respectively connected to 2 row lines, and 2 input ends D43 and D44 of the column status register 404 are respectively connected to 2 column lines; 2 output terminals Q41, Q42 of the row state register 403 output row state signals I1, I2, and 2 output terminals Q43, Q44 of the column state register 404 output column state signals I3, I4; the 2 output terminals of the row state register 403 and the 2 output terminals of the column state register 404 form a 4-bit keyboard state signal output terminal to output keyboard state signals I1, I2, I3, I4.

In an embodiment, the enable input EN1 of the row tri-state buffer 401 is active low, and the enable input EN2 of the column tri-state buffer 402 is active high; EN1 and EN2 are both connected to the CK sampling pulse output of oscillator 500. The receiving pulse input terminals CLK3 and CLK4 of the row state register 403 and the column state register 404 are both connected to the CK sampling pulse output terminal of the oscillator 500, the row state register 403 performs data latch at the falling edge of the CK sampling pulse, and the column state register 404 performs data latch at the rising edge of the CK sampling pulse.

When the row tri-state buffer 401 and the column tri-state buffer 402 use the same type of tri-state buffer, for example, the tri-state buffer 74HC241 is used at the same time, the enable input of 74HC241 is active high, and therefore, a not gate needs to be added between the CK sampling pulse output terminal and the enable input terminal EN1 of the row tri-state buffer 401. Similarly, when the row state register 403 and the column state register 404 use the same type of data register, for example, the row state register 403 and the column state register 404 both use the dual D flip-flop 74HC74 to form the data register, the rising edge of the flip-flop 74 is asserted, so that a not gate needs to be added between the CK sampling pulse output terminal and the receiving pulse input terminal CLK3 of the row state register 403.

The first buffer register 100, the second buffer register 200, and the encoder 300 in fig. 1 form a scan encoding circuit, and a circuit diagram of an embodiment thereof is shown in fig. 3. The keyboard status signal of the matrix keyboard is a 4-bit binary code, and therefore, the first buffer register 100 and the second buffer register 200 are required to register 4-bit binary data. 4 data input ends D10-D13 of the first buffer register 100 are connected to I1, I2, I3 and I4; 4 data input terminals D24 to D27 of the second buffer register 200 are connected to 4 output terminals Q10 to Q13 of the first buffer register 100; of the 8 input terminals A0 to A7 of the

encoder

300, 4 are connected to 4 output terminals Q10 to Q13 of the first buffer register 100, and the other 4 are connected to 4 output terminals Q24 to Q27 of the second buffer register 200. The encoder 300 outputs a 4-bit binary key number determined by the scan encoding.

In fig. 3, the flip-flop 101 constitutes a first buffer register 100, and the flip-flop 201 constitutes a second buffer register 200. The flip-flop 101 is composed of 4 edge flip-flops, and a trigger input terminal CLK1 of the 4 edge flip-flops is a pulse receiving input terminal of the first buffer register 100, and is connected to a CP clock pulse output terminal of the oscillator 500; the flip-flop 201 is composed of 4 edge flip-flops, and a trigger input terminal CLK2 of the 4 edge flip-flops is a receiving pulse input terminal of the second buffer register 200, and is connected to a CP clock pulse output terminal of the oscillator 500. The flip-

flops

101 and 201 are preferably composed of edge-triggered D flip-flops, for example, a dual D flip-flop 74HC74, a 4D flip-flop 74HC175, and an 8D flip-flop 74HC273. In the embodiment of fig. 3, the 8D flip-flop 74HC273 triggered by the rising edge is selected by the flip-

flops

101 and 201, and at this time, the clear input not shown in fig. 3 needs to be connected to a high level, so that the clear function of the 74HC273 is in an invalid state, and only has a trigger function. Both the flip-flop 101 and the flip-flop 201 only need 4D flip-flops, and each of the 4D flip-flops in the selected 8D flip-flop 74HC273 can be arbitrarily used. The trigger input of the 8D flip-flop 74HC273 is connected to CP.

In fig. 3, the rom 301 constitutes an encoder 300. The address input terminals A7-A0 of the ROM 301 are input terminals of the encoder 300, and the data output terminals D3-D0 of the ROM 301 are output terminals C3-C0 of the encoder 300.

The principle of the matrix type keyboard state identification and coding method is as follows:

in fig. 2, the 4 keys of the matrix keyboard are arranged in a 2 × 2 matrix, and all the row lines and column lines are connected to the power supply + VCC through pull-up resistors. The matrix keyboard is controlled by CK sampling pulses, and keyboard state signals I4, I3, I2 and I1 are obtained by adopting an inversion method. For example, the keyboard status signal of no key press is 1111, the keyboard status signal of S1 press is 1010, and the keyboard status signals of S1 and S2 press simultaneously are 0010. The 4-bit binary code of the keyboard status signal is called a key value.

The method for sampling and reading key values of the matrix keyboard by CK sampling pulse control comprises the following steps: at the low level of the CK sampling pulse, the row tri-state buffer 401 controls all row lines to output the low level, and the column tri-state buffer 402 outputs a high-resistance state to open a column line; the column state register 404 samples the read column line state as the high 2 bits of the key value on the rising edge of the CK sample pulse; at the high level of the CK sampling pulse, all column lines are controlled to output low level through the column tri-state buffer 402, and the row tri-state buffer 401 outputs high resistance state to open a row line; the row state is sampled and read by the row state register 403 as the lower 2 bits of the key value at the falling edge of the CK sampling pulse; the above process is repeated, and the 4-bit key value output by the column status register 404 and the row status register 403 is always the latest state of the matrix keyboard.

As can be seen from the method of sampling and reading key values for the matrix keyboard by using the CK sampling pulse control, the row tri-state buffer 401 requires the column state register 404 to perform data latch at the rising edge of the CK sampling pulse, the column tri-state buffer 402 to perform data latch at the high level of the CK sampling pulse, and the row state register 403 to perform data latch at the falling edge of the CK sampling pulse when the low level of the CK sampling pulse is enabled. Conversely, if the row tri-state buffer 401 is enabled at the high level of the CK sampling pulse, the column state register 404 is required to latch data at the falling edge of the CK sampling pulse, the column tri-state buffer 402 is enabled at the low level of the CK sampling pulse, and the row state register 403 latches data at the rising edge of the CK sampling pulse.

In the process of sampling and reading the key value by using the CK sampling pulse control, the sampling time of the row state register 403 and the column state register 404 is exactly the time of performing state inversion on the column tri-state buffer 402 and the row tri-state buffer 401, and the row state register 403 or the column state register 404 under normal operation can be correctly sampled. If a certain time sequence margin is required, the CK sampling pulse connected to the column tri-state buffer 402 and the row tri-state buffer 401 can be delayed, the method is to enable the CK sampling pulse to be connected to EN1 and EN2 of the row tri-state buffer 401 and the column tri-state buffer 402 through an RC delay circuit, the delay time is determined by the RC delay circuit, and the principle of determining the delay time of the RC delay circuit is that the phase of the delayed CK sampling pulse does not exceed 90 degrees; or the CK sampling pulse is buffered by several gates and then connected to EN1 and EN2 of the row tri-state buffer 401 and the column tri-state buffer 402, and the delay time at this time is the total delay time of the several gates.

Under the control of the CP clock pulse, the first buffer register 100 and the second buffer register 200 latch data at the active trigger edge of each period of the CP. In fig. 3, 74HC273 is active for rising edge triggers, so the active triggering edge of the CP clock pulse is a rising edge.

The 4-bit output data of the first buffer register 100 is subjected to only one-stage buffering, and the 4-bit output data of the second buffer register 200 is subjected to two-stage buffering. Therefore, at the effective triggering edge of the CP clock pulse, the data latched by the 4 data output terminals Q10 to Q13 corresponding to the first buffer register 100 is the current state of the matrix keyboard, and the 4 bits of data are called current state key values; the data latched by the 4 data output terminals Q24 to Q27 corresponding to the second buffer register 200 is the previous state of the matrix keyboard, and the 4 bits of data are referred to as previous state key values. The 4-bit current state key value and the 4-bit previous state key value jointly form an 8-bit state code.

The 8-bit state code is used for identifying the current state and the operation state of the matrix keyboard. For example, in the present embodiment, the status code of no key depression is 11111111; the status code of the single key pressing operation of the S1 key is 11111010; the state code of the S1 key pressed and maintained by the single key is 10101010; the state code of the S1 key single-key release operation is 10101111; the status code of the S2 key single key press operation is 11110110; the state code of the single key pressing operation of the S4 key is 11110101; the S1 press operation of the S2+ S1 combination operation indicates an operation of pressing S1 after pressing S2 first, and then maintaining the pressed state at S2, and the state code of the operation is 01100010.

The encoder 300 is used to convert the status code into a key number. In an embodiment, there are 6 valid keyboard operations and states, including:

operation 0: a single key of the key S1 is pressed down, and the key number is 0000;

operation 1: the single key of the key S2 is pressed down, and the key number is 0001;

and operation 2: a single key of the key S3 is pressed down, and the key number is 0010;

and operation 3: the key S3 is in a maintenance state after the single key is pressed, and the key number is 0011;

and operation 4: after a single key of the key S4 is pressed down, a combined key of the key S2 is pressed down for operation, and the key number is 0100;

operation 5: the single key release operation of the key S1 has a key number 0101.

The state code and key number obtained according to the above specification are shown in code table 1:

TABLE 1 coding table

Keyboard operation	Status code (Address)	Key number (storage data)
			S1 Single Key Press	11111010	0000
S2 Single Key Press	11110110	0001
			S3 Single Key Press	11111001	0010
S3 Single Key push sustain	10011001	0011
			S4+ S2 Combined operation	01010100	0100
S1 Single bond Release	10101111	0101
			Other operations or states	********	1111

The encoder 300 is a combinational logic circuit, and the circuit is designed to satisfy the logic relationship of table 1.

The encoder 300 of an embodiment is preferably comprised of a read only memory 301. The ROM 301 has 8-bit address, 2 in total ⁸ 4-bit binary memory cells. The 6 effective keyboard operations and states have 6 effective state codes corresponding to 6 effective key numbers; the state code is written as the address A7 to A0 of the read only memory 301, and the corresponding key number is written as the storage data in the storage unit corresponding to the 6 valid state codes. The status codes generated by the 6 valid keyboard operations and states are invalid status codes, that is, the status codes generated by the other operations or states in table 1 are invalid status codes; in the other memory cells, an invalid key number, which is a value other than the 6 valid key numbers, is written all over, and in the embodiment, the invalid key number is 1111.

The read only memory 301 is always operated in the data output state. When the rom 301 has functions of chip select control and data output buffer control, the chip select control and the data output buffer control should be enabled.

The key number in the embodiment is a 4-bit binary code. The number of binary digits of the key number may be increased or decreased as required, and in this case, only the rom 301 matched with the number of binary digits is selected. Assuming that the number of binary digits of the key number is M, the value of M should be selected to satisfy 2 ^M Greater than or equal to the number of valid and invalid keysAnd (d). When the matrix keyboard has N-bit keyboard status signal output, the rom 301 needs 2 × N bit address input and M-bit data output.

If the key operation function needs to be increased or decreased or adjusted, the table 1 needs to be modified as needed, and the modified content is rewritten into the storage content of the rom 301.

In the embodiment, when the matrix keyboard S1 single key is pressed, the encoder 300 outputs the key number 0000 from the effective trigger edge of the CP clock pulse after the S1 single key is pressed to the effective trigger edge of the next CP clock pulse through the encoding output terminals C3 to C0; when the matrix keyboard S2 single key is pressed, the encoder 300 outputs a key number 0001 from the effective triggering edge of the CP clock pulse after the S2 single key is pressed to the effective triggering edge of the next CP clock pulse; when the matrix keyboard is pressed S4 first and then S2, the encoder 300 outputs a key number 0100 from the effective trigger edge of the CP clock pulse after the combination key of S2 is pressed to the effective trigger edge of the next CP clock pulse; when the matrix keyboard S1 single key is released, the encoder 300 outputs the key number 0101 from the effective trigger edge of the CP clock pulse after the S1 single key is released to the effective trigger edge of the next CP clock pulse; therefore, it can be seen that when the effective key operation of the matrix keyboard is identified, the encoder 300 outputs an effective key number with a duration of one CP clock period width from the effective triggering edge of the CP clock after the effective key operation to the effective triggering edge of the next CP clock.

In the embodiment, when the matrix keyboard S3 single key is pressed, the encoder 300 outputs a key number 0010 from the effective trigger edge of the CP clock pulse after the S3 single key is pressed to the effective trigger edge of the next CP clock pulse; the encoder 300 outputs a key number 0011 from the start of the effective triggering edge of the next CP clock pulse to the effective triggering edge of the next CP clock pulse after the end of the S3 single key pressing maintenance state; it can thus be seen that when the sustained state of the matrix keyboard is identified, the duration of the encoder 300 outputting the valid key number is adapted to the duration of the sustained state.

When the state or operation of the keyboard is outside of the 6 valid keyboard operations and states described in table 1, the encoder 300 outputs an invalid key number 1111. Whether a valid key number is output or an invalid key number is output, the moment of changing the output content of the encoder 300 is the valid trigger edge of the CP clock pulse; in an embodiment, the moment when the encoder 300 changes the output content is the rising edge of the CP clock pulse.

The period of the CP clock pulse is the scanning period of the matrix keyboard. When the scanning period of the keyboard is more than 20ms, the influence of keyboard key jitter can be effectively avoided; when the keyboard scanning period is below 100ms, keyboard operation is not missed; therefore, the period of the CP clock should be controlled to 20-100 ms.

The period requirement of the CK sampling pulse is not more than that of the CP clock pulse, so that when the state code is acquired at each effective trigger edge of the CP clock pulse, 4-bit key values output by the column state register 404 and the row state register 403 can be ensured to be always in the latest state of the matrix keyboard. A specific example of the CK sampling pulse is to directly use the CP clock pulse as the CK sampling pulse.

In the embodiment, the CP clock pulse and the CK sampling pulse are generated and output by the oscillator 500. The CP clock pulses and CK sample pulses may also be provided by circuits or devices other than the matrix keyboard state identification and encoding circuitry.

Fig. 4 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention. When the effective key operation of the matrix keyboard is identified, the encoder 300 outputs an effective key number whose duration is one CP clock period width from the effective trigger edge of the CP clock after the effective key operation to the effective trigger edge of the next CP clock. And the device for receiving the matrix type keyboard output needs to inquire the matrix type keyboard output all the time to acquire the key number. The period interval of the inquiry must be smaller than the period of the CP clock pulse.

The circuit shown in fig. 4 is used for judging whether the key number output by the matrix keyboard is changed or not, when the key number output by the matrix keyboard is changed, a keyboard state change pulse is output, and the receiving device for assisting the matrix keyboard receives the key number output by the matrix keyboard, for example, the keyboard state change pulse is used as an interrupt request signal of the receiving device.

The circuit shown in fig. 4 is composed of a delay buffer 601, an xor gate 602, an xor gate 603, an xor gate 604, an xor gate 605, and an or gate 606. The delay buffer 601 is composed of 4 edge flip-flops only having a trigger function, and the trigger input ends of the 4 edge flip-flops are the receiving pulse input ends of the delay buffer 601 and are all connected to the CP clock pulse output end of the oscillator 500; the delay buffer 601 performs data latching on the active triggering edge of the CP clock pulse.

The delay buffer 601 delays the 4-bit data C3 to C0 at the encoding output terminal of the encoder 300. 4 data input ends D63-D60 of the delay buffer 601 are connected to the encoding output ends C3-C0 of the encoder 300, and the data correspondingly output by the 4 data output ends Q63-Q60 of the delay buffer 601 is C31-C01; after the signals of C31-C01 are buffered by the first stage of the delay buffer 601, the signals are delayed by one CP clock period from C3-C0, and fig. 5 is a waveform diagram related to the effective operation of the keyboard according to the embodiment of the present invention. And setting the interval T1 of the CP clock pulse, wherein the matrix keyboard has one effective operation, and the effective operation of the embodiment comprises the following steps: s1 single key press, S2 single key press, S3 single key press, S2 press by S4+ S2 combination operation, S1 single key release. At the next active trigger edge of an active operation, i.e. the rising edge after the interval of the CP clock pulse T1 in fig. 5, the codes C3 to C0 output by the encoder 300 change; in the interval T2, the encoder 300 outputs effective codes C3-C0 of one period; during the intervals T3, T4 and thereafter, the codes C3 to C0 output by the encoder 300 are changed again and enter the holding state, which may be, for example, the holding state after the S1 single key is pressed, the invalid key number is output, or the holding state after the S3 single key is pressed, the valid key number is output until the next valid operation.

The D6 pulse in fig. 5 schematically shows whether the codes C3 to C0 outputted from the encoder 300 are in the hold state, are not changed, or are changed, and the D6 pulse does not exist in the actual circuit. As shown in fig. 5, the D6 pulse is low, which schematically shows that the codes C3 to C0 output from the encoder 300 are in a hold state and do not change; the D6 pulse is high, which schematically indicates that the encoder 300 outputs one cycle of active codes C3C 0. Q6 in FIG. 5 reflects the variation of C31C 01, and it is apparent that Q6 is delayed by one CP clock period from D6. Also, the Q6 pulse is not present in the actual circuit.

In fig. 5, the codes C3 to C0 outputted from the encoder 300 are in a hold state, are not changed, or are changed, and are actually completed by a logic circuit including a 4-bit delay buffer 601, an xor gate 602, an xor gate 603, an xor gate 604, an xor gate 605, and an or gate 606. The 4 exclusive or gates respectively correspond to 1 bit of the encoding output terminals C3 to C0 of the encoder 300, and input signals are input and output signals of the 4-bit delay buffer 601. For example, two input signals of the xor-gate 602 are C0 and C01, respectively, and C01 is delayed from C0 by one CP clock period, so that when C0 changes, the xor-gate 602 outputs a positive pulse of 1 CP clock period width; when C0 is a CP clock period width change signal, the xor-gate 602 outputs a positive pulse of 2 CP clock period widths. The xor gate 603, the xor gate 604, and the xor gate 605 respectively determine whether or not C1 to C3 have changed, and the principle is the same as that for determining whether or not C0 has changed. The output ends of the exclusive or gate 602, the exclusive or gate 603, the exclusive or gate 604 and the exclusive or gate 605 are respectively connected to the input end of the or gate 606, the or gate 606 is used for comprehensively judging whether the C0-C3 change, and as long as the C0-C3 change, the or gate 606 outputs a keyboard state change pulse F, which is a positive pulse.

In an embodiment, the delay buffer 601 selects the rising edge triggered 8D flip-flop 74HC273.

Other schemes can be adopted for the delay buffer 601, for example, an RC circuit is adopted, and 4 RC circuits are used for respectively delaying C0 to C3; if the delay time of the RC circuit is less than one CP clock pulse period, when the encoder 300 outputs effective codes C3-C0 of one period, a keyboard state change pulse is generated at the beginning of outputting the effective codes C3-C0 and at the end of outputting the effective codes C3-C0, and the width of the keyboard state change pulse is equal to the delay time of the RC circuit; if the delay time of the RC circuit is greater than or equal to one CP clock pulse period, the encoder 300 generates a keyboard state change pulse at the beginning of outputting the valid codes C3 to C0 when outputting the valid codes C3 to C0 of one period, and the pulse width is greater than or equal to 2 CP clock pulse periods. The delay time of the RC circuit is required to not exceed 2 CP clock cycles to avoid false negatives.

In the circuit, the positioning of single key operation, combined key operation and keyboard maintenance state operation is converted into a state code with the same binary length by CP pulse scanning, and the state code is processed by adopting a uniform coding mode, wherein the single key operation, the combined key operation and the keyboard maintenance state operation are only reflected on the difference of the state code; if the key operation function needs to be increased or decreased or adjusted, the structure of the keyboard scanning circuit does not need to be modified, and the encoder 300 only needs to be updated according to the increased or decreased state code table, i.e., the storage content of the read-only memory 301 needs to be rewritten and updated. The circuit of the invention does not use microcontrollers such as a singlechip and an ARM, does not need running programs, and has reliable work.

Claims

1. A matrix type keyboard state identification and coding method is characterized in that: outputting an N-bit keyboard state signal by a matrix type keyboard comprising an X row-Y column key matrix, wherein N = X + Y; the buffer register is controlled by clock pulses to carry out secondary buffer latch on the N-bit keyboard state signals, data output by the primary buffer is a current state key value, and data output by the secondary buffer is a previous state key value; the present state key value and the previous state key value jointly form a 2 multiplied by N state code; encoding the status code and outputting a key number; said bits are binary bits;

the encoding of the state code and the output of the key number are realized by an encoder;

the method for controlling the buffer register by the clock pulse to carry out secondary buffer latch on the N-bit keyboard state signal is realized by a first buffer register and a second buffer register; the first buffer register and the second buffer register are both N-bit binary registers; the N-bit data input end of the first buffer register is connected to the N-bit keyboard state signal output end, and the N-bit data input end of the second buffer register is connected to the N-bit data output end of the first buffer register; the receiving pulse input end of the first buffer register and the receiving pulse input end of the second buffer register are both connected to a clock pulse;

the X row lines and the Y column lines of the matrix keyboard are connected with pull-up resistors, and the X row lines and the Y column lines are controlled to be in a low-level state alternately by sampling pulses; the Y row line state when the X row lines are at a low level is latched to obtain a Y-bit row state signal, and the X row line state when the Y row lines are at a low level is latched to obtain an X-bit row state signal; the X-bit row state signal and the Y-bit column state signal jointly form an N-bit keyboard state signal;

the sampling pulse controls X row lines and Y column lines to be alternately in a low level state, and the low level state is realized by a row tri-state buffer and a column tri-state buffer; the row lines of all the key matrixes are respectively connected to the output ends of the row tri-state buffers, and the column lines of all the key matrixes are respectively connected to the output ends of the column tri-state buffers; all input ends of the row tri-state buffer and the column tri-state buffer are connected to a low level; enabling the row tri-state buffer to be effective at the low level of the sampling pulse and enabling the column tri-state buffer to be effective at the high level of the sampling pulse, or enabling the row tri-state buffer to be effective at the high level of the sampling pulse and enabling the column tri-state buffer to be effective at the low level of the sampling pulse;

the Y-bit column state signal is obtained by latching the Y column line state when the X column lines are at a low level, and the X-bit row state signal is obtained by latching the X column line state when the Y column lines are at a low level, and the Y-bit column state signal is realized by a row state register and a column state register; the row lines of all the key matrixes are respectively connected to the input end of the row state register, and the column lines of all the key matrixes are respectively connected to the input end of the column state register; when the row tri-state buffer enables the effective low level of the sampling pulse and the column tri-state buffer enables the effective high level of the sampling pulse, the column state register performs data latch on the rising edge of the sampling pulse, and the row state register performs data latch on the falling edge of the sampling pulse; when the row three-state buffer enables to be effective at the high level of the sampling pulse and the column three-state buffer enables to be effective at the low level of the sampling pulse, the column state register performs data latch at the falling edge of the sampling pulse, and the row state register performs data latch at the rising edge of the sampling pulse;

the period of the sampling pulse is not greater than the period of the clock pulse.

2. The matrix keyboard state identification and encoding method of claim 1, wherein: the present key value of the N-bit keyboard state signal is the N-bit keyboard state signal at the effective triggering edge moment of the clock pulse, and the previous key value of the N-bit keyboard state signal is the N-bit keyboard state signal at the effective triggering edge moment of the clock pulse.

3. The matrix keyboard state identification and encoding method of claim 1, wherein: the state code consists of an effective state code and an invalid state code and is used for identifying the current state and the operation state of the matrix keyboard; the key number is composed of a valid key number and an invalid key number; the effective state code is generated by the operation or the state of an effective keyboard, and a corresponding effective key number is correspondingly output; the invalid state code is generated by invalid keyboard operation or state and correspondingly outputs an invalid key number.

4. The matrix keyboard state identification and encoding method of claim 3, wherein: the key number is M bits, and the selection of the M value should satisfy 2 ^M Greater than or equal to the sum of the number of valid and invalid key numbers.

5. The matrix keyboard state identification and encoding method of claim 3, wherein: the effective keyboard operation comprises single-key pressing operation, single-key releasing operation, single-key pressing maintaining operation and combined key operation; the combined key operation refers to the operation that after a single key is pressed down, other keys are pressed down; the invalid keyboard operation is an operation other than the valid keyboard operation.