CN108880560B - Matrix keyboard reversal method scanning circuit - Google Patents
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Abstract
A matrix keyboard inversion method scanning circuit, X row lines and Y row lines of the matrix keyboard are connected with pull-up resistors, and sampling pulses control the X row lines and the Y row lines to be in a low level state alternately; the Y row line state when the X row lines are at a low level is latched to obtain a Y-bit row state signal, and the X row line state when the Y row lines are at a low level is latched to obtain an X-bit row state signal; the X-bit row state signal and the Y-bit column state signal jointly form an N-bit keyboard state signal output by the matrix keyboard. The scanning of the matrix keyboard by the inversion method of the circuit is realized by adopting a sequential logic circuit, a microcontroller such as a single chip microcomputer and an ARM is not used, no running program is used, and the operation is reliable.
Description
The invention discloses a matrix type keyboard scanning circuit and a scanning coding method, wherein the matrix type keyboard scanning circuit is a divisional application, the original application number is 201610003404.5, and the application date is 2016, 1 and 5.
Technical Field
The invention relates to a scanning circuit of a keyboard, in particular to a matrix type keyboard inversion method scanning circuit.
Background
With the continuous development of embedded technology, various electronic products generally adopt a microcontroller as a control core and a keyboard as a main input device, and are widely applied.
The existing keyboard scanning is mainly controlled by a microcontroller, and is performed by running a program in the microcontroller, so that the program runs off due to interference, and the scanning program cannot work normally.
The invention patent with application number CN201010153560.2, "a method for fast scanning and positioning matrix keyboard", adopts a mode of keyboard interrupt triggering to enter the scanning and positioning process of keyboard, adopts a method of repeating the keyboard scanning step for many times to judge whether the key is valid, and makes state judgment on the obtained key value; if the multiple sampling states are the same, the key value is in a stable state and is valid; if the multiple sampling states are different, the key value is invalid. The single key operation or the combined key operation needs to be judged separately, if the single key operation is carried out, the single key processing mode is entered; if the operation is a combination key operation, a combination key processing mode is entered. The method disclosed in the patent solves the problems of wrong keys, continuous key touch and other errors caused by keyboard shaking due to the mechanical characteristics of the keyboard, and the problem of supporting combined keys and repeated keys. But the single key operation and the combined key operation of the method need to be processed respectively; a keyboard operation function of executing effective operation after a certain period of time of maintaining the keyboard state is not considered; when the key operation function is increased or decreased or adjusted, the structure of the keyboard scanning and positioning program needs to be modified.
Disclosure of Invention
In order to solve the technical problems of the existing keyboard scanning and positioning method, the invention provides a matrix type keyboard inversion method scanning circuit which is composed of an X row-Y column key matrix, a row tri-state buffer, a column tri-state buffer, a row state register and a column state register. The row lines of all the key matrixes are respectively connected to the output ends of the row tri-state buffers, and the column lines of all the key matrixes are respectively connected to the output ends of the column tri-state buffers; all input ends of the row tri-state buffer and the column tri-state buffer are connected to a low level; the row lines of all the key matrixes are respectively connected to the input end of the row state register, and the column lines of all the key matrixes are respectively connected to the input end of the column state register; the output end of the row state register and the output end of the column state register output N-bit keyboard state signals together; the N-bit keyboard state signal is a level signal; and N is X + Y. .
The sampling pulse controls the alternating enabling of the row tri-state buffer and the column tri-state buffer. The column state register is used for latching data at the moment when the enabling of the row tri-state buffer is effectively and alternately converted into the enabling of the column tri-state buffer; the row state register latches the data at the time the column tri-state buffer enable is effectively toggled to the row tri-state buffer enable. Specifically, the row tri-state buffer is enabled to be effective at the low level of the sampling pulse, and the column tri-state buffer is enabled to be effective at the high level of the sampling pulse; the column state register latches data at a rising edge of the sampling pulse, and the row state register latches data at a falling edge of the sampling pulse. Or, the row three-state buffer is enabled to be effective at the high level of the sampling pulse, and the column three-state buffer is enabled to be effective at the low level of the sampling pulse; the column state register latches data at a falling edge of the sampling pulse, and the row state register latches data at a rising edge of the sampling pulse.
Furthermore, in order to solve the problem of matrix keyboard scanning positioning, the scanning circuit of the matrix keyboard inversion method further comprises a scanning encoding circuit consisting of a first shift register, a second shift register, a state code register and an encoder, and the scanning encoding circuit is synchronously controlled by scanning pulses and shifting pulses.
The first shift register has N-bit parallel input, N-bit parallel output and serial output functions; the second shift register has serial input and N-bit parallel output functions.
The N-bit parallel input end of the first shift register is connected to the N-bit keyboard state signal output end; the serial input end of the second shift register is connected to the serial output end of the first shift register; the shift pulse input ends of the first shift register and the second shift register are connected to shift pulses, and the preset pulse input end of the first shift register is connected to the scanning pulse. The preset pulse of the first shift register is used for inputting and latching N-bit parallel input data of the first shift register.
The state code register is a 2 XN bit binary register; an N-bit data input end in the state code register is connected to an N-bit parallel output end of the first shift register, and the other N-bit data input end is connected to an N-bit parallel output end of the second shift register; and the receiving pulse input end of the state code register is connected to the scanning pulse.
The encoder has a 2 xn bit encoding input connected to the 2 xn bit data output of the status code register. The time sequence of the scanning pulse and the shifting pulse meets the following requirements: the scan pulse is an N-division signal of the shift pulse, and is a positive narrow pulse or a negative narrow pulse. The period of the scanning pulse is 20-100 ms.
The first shift register and the second shift register shift at the rising edge of the shift pulse at the same time, and the positive narrow pulse or the negative narrow pulse of the scanning pulse is positioned between the rising edges of the front shift pulse and the back shift pulse; or, the first shift register and the second shift register shift at the same time at the falling edge of the shift pulse, and the positive narrow pulse or the negative narrow pulse of the scan pulse is between the falling edges of the two shift pulses.
When the preset pulse of the first shift register is effective in edge and the scanning pulse is a positive narrow pulse, the preset pulse of the first shift register is required to be effective in rising edge, and the receiving pulse of the state code register is required to be effective in falling edge; when the preset pulse of the first shift register is effective in edge and the scanning pulse is negative narrow pulse, the preset pulse of the first shift register is required to be effective in falling edge, and the receiving pulse of the state code register is required to be effective in rising edge; when the preset pulse of the first shift register is high-level effective, the scanning pulse is required to be a positive narrow pulse, and the receiving pulse of the state code register is effective at a falling edge; when the preset pulse of the first shift register is effective at a low level, the scanning pulse is required to be a negative narrow pulse, and the receiving pulse of the state code register is effective at a rising edge.
The 2 XN bit data output end of the state code register outputs a 2 XN bit state code; the state code consists of a valid state code and an invalid state code; the key number output by the encoder consists of an effective key number and an ineffective key number; the effective state codes are generated by the operation or the state of an effective keyboard, and corresponding effective key numbers are correspondingly output when the encoder inputs each effective state code; the invalid state code is generated by invalid keyboard operation or state, and when the encoder inputs all the invalid state codes, the encoder correspondingly outputs invalid key numbers.
The encoder has an M-bit key number output, and M should be selected to satisfy 2MGreater than or equal to the sum of the number of valid and invalid key numbers.
The matrix type keyboard inversion method scanning circuit further comprises a keyboard state change pulse generating unit which is used for judging whether the key number output by the matrix type keyboard changes or not, and when the key number output by the matrix type keyboard changes, the keyboard state change pulse is output.
The keyboard state change pulse generation unit consists of an OR gate, an M-bit delay buffer and M XOR gates; the M-bit delay buffer is used for respectively carrying out signal delay on the M-bit key numbers output by the matrix keyboard; the inputs of the M exclusive-OR gates are input signals and output signals of the M-bit delay buffer respectively; the outputs of the M exclusive-OR gates are respectively connected to the input ends of the OR gates; the output end of the OR gate outputs a keyboard state change pulse.
The N bits, 2 XN bits and M bits all refer to binary bit data.
The invention has the beneficial effects that: the scanning of the matrix keyboard by the inversion method is realized by adopting a sequential logic circuit, a microcontroller such as a single chip microcomputer and an ARM is not used, no program is required to run, and the operation is reliable. The keyboard positioning method is characterized in that scanning positioning of single key operation, combined key operation and keyboard maintenance state operation is controlled and converted into state codes with the same binary length by scanning pulses and shifting pulses meeting specific time sequence requirements, and the state codes are processed in a uniform coding mode, wherein the single key operation, the combined key operation and the keyboard maintenance state operation are only reflected on different state codes; if the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the circuit structure does not need to be modified, and the encoding content of the encoder only needs to be changed according to the corresponding relation between the increased or decreased state code and the key number, namely the storage content written into the read-only memory is modified again.
Drawings
FIG. 1 is a schematic block diagram of a matrix keyboard inversion method scan circuit including a scan encoding circuit;
FIG. 2 illustrates an embodiment of a scanning circuit for matrix keyboard inversion;
FIG. 3 is a circuit diagram of scan encoding according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a first shift register according to an embodiment of the present invention;
FIG. 5 is a pulse timing diagram of an embodiment of the present invention;
FIG. 6 is a schematic diagram of a pulse circuit of an embodiment of the present invention;
FIG. 7 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention;
FIG. 8 is a waveform diagram illustrating the effective operation of a keyboard according to an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic block diagram of a matrix keyboard scan circuit including scan encoding circuitry. The matrix keyboard inversion method scanning circuit can be composed of the matrix keyboard 400 in fig. 1 alone, or further comprises the first shift register 100, the second shift register 200, the status code register 500 and the encoder 300 in fig. 1. The first shift register 100, the second shift register 200, the status code register 500, and the encoder 300 constitute a scan encoding circuit.
Fig. 2 shows an embodiment of a matrix keyboard inversion scanning circuit comprising a matrix keyboard 400 alone, i.e. an embodiment of a matrix keyboard 400 having 2 rows, 2 columns and 4 keys, and comprising a key S1, a key S2, a key S3, a key S4, a pull-up resistor R1 connected to + VCC, a pull-up resistor R2, a pull-up resistor R3, a pull-up resistor R4, a row tristate buffer 401, a column tristate buffer 402, a row status register 403 and a column status register 404. 2 output terminals Y1 and Y2 of the row tri-state buffer 401 are respectively connected to 2 row lines, and 2 output terminals Y3 and Y4 of the column tri-state buffer 402 are respectively connected to 2 column lines; all the inputs X1-X4 of the row tri-state buffer 401 and the column tri-state buffer 402 are connected to low level.
The 2 input terminals D41, D42 of the row status register 403 are connected to 2 row lines, respectively, and the 2 input terminals D43, D44 of the column status register 404 are connected to 2 column lines, respectively; the 2 output terminals Q41, Q42 of the row state register 403 output row state signals I1, I2, and the 2 output terminals Q43, Q44 of the column state register 404 output column state signals I3, I4; the 2 output terminals of the row state register 403 and the 2 output terminals of the column state register 404 form a 4-bit keyboard state signal output terminal for outputting keyboard state signals I1, I2, I3 and I4.
In an embodiment, the enable input EN1 of row tri-state buffer 401 is active low, and the enable input EN2 of column tri-state buffer 402 is active high; EN1 and EN2 are both connected to the sampling pulse CK output of the oscillator 500. The receiving pulse input terminals CLK3 and CLK4 of the row state register 403 and the column state register 404 are connected to the output terminal of the sampling pulse CK of the oscillator 500, the row state register 403 latches data at the falling edge of the sampling pulse CK, and the column state register 404 latches data at the rising edge of the sampling pulse CK.
When the row tri-state buffer 401 and the column tri-state buffer 402 use the same type of tri-state buffer, for example, the tri-state buffer 74HC241 is used at the same time, the enable input of 74HC241 is active high, and therefore, a not gate needs to be added between the output of the sampling pulse CK and the enable input EN1 of the row tri-state buffer 401. Similarly, when the row state register 403 and the column state register 404 use the same type of data register, for example, the row state register 403 and the column state register 404 both use the dual D flip-flop 74HC74 to form the data register, the trigger input of 74HC74 is active at the rising edge, and therefore, a not gate needs to be added between the output terminal of the sampling pulse CK and the input terminal CLK3 of the receiving pulse of the row state register 403.
The first shift register 100, the second shift register 200, the status code register 500, and the encoder 300 in fig. 1 form a scan encoding circuit, and a circuit diagram of an embodiment thereof is shown in fig. 3. The output status signal of the matrix keyboard 400 is 4 bits, so the first shift register 100 and the second shift register 200 are both 4-bit binary shift registers, wherein the first shift register 100 has parallel input, parallel output and serial output functions, and the second shift register 200 has serial input and parallel output functions; the 4 parallel input ends L0-L3 of the first shift register 100 are connected to I1, I2, I3 and I4 in sequence, and the serial input end D2 of the second shift register 200 is connected to the serial output end Q13 of the first shift register 100. The shift pulse inputs CLK1 and CLK2 of the first and second shift registers 100 and 200 are connected to a shift pulse CP2, and the preset pulse input CLK0 of the first shift register 100 is connected to a scan pulse CP 1.
The status code register 500 is required to register 8-bit binary data, 4 bits of the 8-bit data input terminals D57-D50 thereof are connected to the parallel output terminals Q13-Q10 of the first shift register 100, and the other 4 bits are connected to the parallel output terminals Q23-Q20 of the second shift register 200; in the embodiment, D57-D54 are connected to Q23-Q20, and D53-D50 are connected to Q13-Q10. The receiving pulse input terminal CLK5 of the state code register 500 is connected to the scan pulse CP 1.
The 8 inputs A7-A0 of the encoder 300 are connected to the 8 data outputs Q57-Q50 of the status code register 500. The encoder 300 outputs a 4-bit binary key number determined by the scan encoding.
In the embodiment of fig. 3, the second shift register 200 may alternatively be composed of various kinds of middle-scale integrated shift registers, or may alternatively be composed of edge flip-flops; when the second shift register 200 is formed of edge flip-flops, it is preferably formed of edge-triggered D flip-flops. The status code register 500 is composed of edge flip-flops, preferably edge-triggered D flip-flops, for example, a select dual D flip-flop CD4013, or a 4D flip-flop 74HC175, or an 8D flip-flop 74HC 273.
FIG. 4 is a circuit diagram of a first shift register 100 according to an embodiment of the present invention, which includes 4D flip-flops 101-104 with both set and reset functions active at high level, and 8 NOR gates 105-112. In one embodiment, D flip-flops 101-104 are selected to be dual D flip-flops CD4013, which have active rising edges of the trigger pulses. The scan pulse CP1 controls the set and reset functions of the D flip-flops 101 to 104 through 8 NOR gates 105 to 112. Taking the D flip-flop 101 as an example, when the scan pulse CP1 is at a high level, the nor gate 105 and the nor gate 106 output a low level, and the set and reset functions of the D flip-flop 101 are disabled; when the scan pulse CP1 is low and L0 is 0, the output of the nor gate 105 is
The output of the nor gate 106 is L0, that is, the set function and the reset function of the D flip-flop 101 are disabled, so that Q10 is 0; when the scan pulse CP1 is low and L0 is 1, the output of the nor gate 105 is
NOR gate 10The output of 6 is L0, i.e., the set function and the reset function of the D flip-flop 101 are enabled and disabled, and Q10 is set to 1. The working principle of the D flip-flops 102 to 104 is the same as that of the D flip-flop 101, and when the scan pulse CP1 is at a low level, Q10 is L0, Q11 is L1, Q12 is L2, and Q13 is L3; when the scan pulse CP1 is at a high level, the trigger pulse inputs CLK10, CLK11, CLK12, and CLK13 of the D flip-flops 101 to 104 are all connected to the CP2, so that the first shift register 100 shifts one bit at the rising edge of each shift pulse CP2, i.e., Q13 equals Q12, Q12 equals Q11, Q11 equals Q10, and Q10 equals 0.
In the embodiment of fig. 3, the encoder 300 is a read-only memory. The address input ends A7-A0 of the ROM are the input ends of the encoder 300, and the data output ends D3-D0 of the ROM are the encoding output ends C3-C0 of the encoder 300.
The working principle of the matrix keyboard inversion method scanning circuit is as follows:
the scan encoding circuit operates under the control of the scan pulse CP1 and the shift pulse CP2, and the timing of the pulses is shown in fig. 5.
The timing of CP1 and CP2 in the embodiment meets the following requirements: the scan pulse CP1 is a 4-frequency division signal of the shift pulse CP2, and is a positive narrow pulse or a negative narrow pulse and is between the two shifting operations controlled by the shift pulse CP 2. When the state signal output by the scanning circuit of the matrix keyboard inversion method is N bits, the scanning pulse CP1 is an N frequency division signal of the shift pulse CP 2.
Fig. 6 is a schematic diagram of a pulse circuit according to an embodiment of the present invention, which is composed of an oscillator 801, a frequency divider 802, and a monostable generator 803. The CP2 pulse in fig. 5 is generated by an oscillator, CP2 is fed to a frequency divider 802 for division by 4, the output of the frequency divider 802 is fed to the input of a monostable generator 803, and the monostable generator 803 outputs a CP1 pulse.
In fig. 2, the 4 keys of the matrix keyboard are arranged in a 2 × 2 matrix, and all the row lines and column lines are connected to the power supply + VCC through pull-up resistors. The matrix keyboard inversion method scanning circuit is controlled by a sampling pulse CK, and keyboard state signals I4, I3, I2 and I1 are obtained by adopting an inversion method. For example, the keyboard status signal of no key press is 1111, the keyboard status signal of S1 press is 1010, and the keyboard status signal of S1, S2 press simultaneously is 0010. The 4-bit binary code of the keyboard status signal is called a key value. The sampling pulse CK may be one of the scan pulse CP1 and the shift pulse CP2, and the shift pulse CP2 is preferably used as the sampling pulse CK at the same time.
The method for sampling and reading key values of the matrix keyboard by the control of the sampling pulse CK comprises the following steps: at the low level of the sampling pulse CK, the row tri-state buffer 401 controls all row lines to output the low level, and the column tri-state buffer 402 outputs a high-resistance open column line; the upper 2 bits of the read column line state as the key value are sampled by the column state register 404 on the rising edge of the sampling pulse CK; at the high level of the sampling pulse CK, the column tri-state buffer 402 controls all column lines to output low level, and the row tri-state buffer 401 outputs high resistance state to open a row line; the row state register 403 samples and reads the lower 2 bits of the row line state as the key value at the falling edge of the sampling pulse CK; the above process is repeated, and the 4-bit key value output by the column status register 404 and the row status register 403 is always the latest status of the matrix keyboard.
In the method for controlling the matrix keyboard to sample and read the key value by the sampling pulse CK, the row tri-state buffer 401 requires the column state register 404 to perform data latch at the rising edge of the sampling pulse CK, the column tri-state buffer 402 to perform data latch at the high level of the sampling pulse CK, and the row state register 403 to perform data latch at the falling edge of the sampling pulse CK when the low level of the sampling pulse CK is enabled. Conversely, if the row tri-state buffer 401 is enabled at the high level of the sampling pulse CK, the column state register 404 is required to latch data at the falling edge of the sampling pulse CK, the column tri-state buffer 402 is enabled at the low level of the sampling pulse CK, and the row state register 403 latches data at the rising edge of the sampling pulse CK.
In the process of controlling the sampling read key value by the sampling pulse CK, the sampling time of the row state register 403 and the column state register 404 is just the time of performing state inversion on the column tri-state buffer 402 and the row tri-state buffer 401, and the row state register 403 or the column state register 404 under normal operation can be correctly sampled. If a certain timing margin is required, the sampling pulse CK connected to the column tri-state buffer 402 and the row tri-state buffer 401 can be delayed by connecting the sampling pulse CK to EN1 and EN2 of the row tri-state buffer 401 and the column tri-state buffer 402 through an RC delay circuit, wherein the delay time is determined by the RC delay circuit, and the delay time of the RC delay circuit is determined by the principle that the phase of the delayed sampling pulse CK is not more than 90 °; or the sampling pulse CK is buffered by several gates and then connected to EN1 and EN2 of the row tri-state buffer 401 and the column tri-state buffer 402, and the delay time is the total delay time of the several gates.
Under the control of a scan pulse CP1, the first shift register 100 latches the state signals I1, I2, I3 and I4 output by the matrix keyboard inversion method scan circuit, and at this time, the output of the first shift register 100 is called the current state key value; the second shift register 200 shifts the output of the scan pulse CP1 latched to the first shift register 100 in the previous period to the output of the second shift register 200 under the control of 4 CP2 pulses in the previous period, so the output of the second shift register 200 at this time is called the previous state key value.
The scan pulse CP1 latches the current key value output by the first shift register 100 and the previous key value output by the second shift register 200 at the output terminal of the status code register 500, and the outputs of the status code register 500 are the previous key value and the current key value.
The shift of the first and second shift registers 100 and 200 is performed on the same edge of the shift pulse CP 2. In the embodiment, the first shift register 100 and the second shift register 200 shift at the same time on the rising edge of the shift pulse CP 2.
When the scanning pulse CP1 is a positive narrow pulse, its rising edge is the leading edge, and its falling edge is the trailing edge; when the scan pulse CP1 is a negative narrow pulse, its falling edge is a leading edge and its rising edge is a trailing edge.
When the first shift register 100 and the second shift register 200 are shifted at the same time at the rising edge of the shift pulse CP2, the leading edge and the trailing edge of the scan pulse CP1 are between the rising edges of the two shift pulses CP2, as shown in fig. 5, the scan pulse CP1 is a negative narrow pulse, the leading edge (falling edge) of each negative narrow pulse of the CP1 is at the falling edge of the shift pulse CP2, the trailing edge (rising edge) of the negative narrow pulse is controlled by the monostable generator 803, and is in front of the rising edge of the next shift pulse CP2, and the leading edge and the trailing edge of the scan pulse CP1 are between the rising edges of the two shift pulses CP 2; when the first and second shift registers 100 and 200 shift at the same time at the falling edge of the shift pulse CP2, the leading edge and the trailing edge of the scan pulse CP1 are between the falling edges of the two shift pulses CP 2.
When the preset pulse of the first shift register 100 is edge-active and the scan pulse CP1 is a positive narrow pulse, it is required that the preset pulse of the first shift register 100 is rising edge-active and the received pulse of the status code register 500 is falling edge-active; when the preset pulse of the first shift register 100 is edge-active and the scan pulse CP1 is negative narrow pulse, the preset pulse of the first shift register 100 is required to be edge-active, and the received pulse of the status code register 500 is required to be edge-active. When the preset pulse of the first shift register 100 is active at a high level, the scan pulse CP1 is required to be a positive narrow pulse, and the received pulse of the status code register 500 is active at a falling edge; when the preset pulse of the first shift register 100 is active low, the scan pulse CP1 is required to be a negative narrow pulse, and the received pulse of the status code register 500 is active on the rising edge. In the embodiment, the preset pulse of the first shift register 100 is active low, so the scan pulse CP1 is a negative narrow pulse, and the received pulse of the status code register 500 is active on the rising edge.
In the embodiment, the 4-bit present key value and the 4-bit previous key value output by the data output terminal of the status code register 500 together form an 8-bit status code. The 8-bit state code is used for identifying the current state and the operation state of the matrix keyboard. For example, in the present embodiment, the status code of no key depression is 11111111; the state code of the single key press operation of the S1 key is 11111010; the state code of the pressed and maintained single key of the S1 key is 10101010; the status code of the S1 key single key release operation is 10101111; the status code of the single key press operation of the S2 key is 11110110; the state code of the single key press operation of the S4 key is 11110101; the S1 pressing operation of the S2+ S1 combination operation indicates an operation of pressing S1 after pressing S2, and the state code of this operation is 01100010 while maintaining the pressed state at S2.
The encoder 300 is used to convert the status code into a key number. In an embodiment, there are 6 valid keyboard operations and states, including:
operation 0: a single key press operation of the key S1, the key number being 0000;
operation 1: a single key of the key S2 is pressed, and the key number is 0001;
operation 2: a single key of the key S3 is pressed, with the key number 0010;
operation 3: the key S3 is in a maintenance state after the single key is pressed, and the key number is 0011;
and operation 4: after the single key of the key S4 is pressed, the combined key of the key S2 is pressed for operation, and the key number is 0100;
operation 5: the single key release operation of the key S1 has a key number 0101.
The state code and key number obtained according to the above specification are shown in code table 1:
TABLE 1 coding table
| Keyboard operation | Status code (Address) | Key number (storage data) |
| S1 Single Key Pushing | 11111010 | 0000 |
| S2 Single Key Pushing | 11110110 | 0001 |
| S3 Single Key Pushing | 11111001 | 0010 |
| S3 Single Key Press Retention | 10011001 | 0011 |
| Combined operation of S4+ S2 | 01010100 | 0100 |
| S1 Single bond Release | 10101111 | 0101 |
| Other operations or states | ******** | 1111 |
The encoder 300 is a combinational logic circuit, and the designed encoding circuit satisfies the logical relationship of table 1.
The encoder 300 of an embodiment is preferably comprised of read only memory. The ROM has 8-bit address, 284 bit binary memory cells. The 6 effective keyboard operations and states have 6 effective state codes corresponding to 6 effective key numbers; the state codes are written as the addresses a7 to a0 of the read only memory, and the corresponding key numbers are written as the storage data in the storage cells corresponding to the 6 valid state codes. The status codes generated for the other than the 6 valid keyboard operations and statuses are invalid status codes, i.e. the status codes generated for the other operations or statuses in Table 1 are invalid statusesCode; in the other memory cells, an invalid key number, which is a value other than the 6 valid key numbers, is written all over, and in the embodiment, the invalid key number is 1111.
The read-only memory is always operated in a data output state. When the read-only memory has chip selection control and data output buffer control functions, the chip selection control and the data output buffer control are in an effective state.
The key number in the embodiment is a 4-bit binary code. The binary digit number of the key number can be increased or decreased according to the requirement, and at the moment, only the matched read-only memory is needed to be selected. Assuming that the number of binary digits of the key number is M, the value of M should be selected to satisfy 2MGreater than or equal to the sum of the number of valid and invalid key numbers. When the matrix keyboard has N-bit keyboard state signal output, the ROM needs 2 XN-bit address input and M-bit data output.
The N-bit parallel input end of the first shift register is connected to the N-bit keyboard state signal output end; the serial input end of the second shift register is connected to the serial output end of the first shift register; the shift pulse input ends of the first shift register and the second shift register are connected to shift pulses, and the preset pulse input end of the first shift register is connected to the scanning pulse.
The status code register is 2 × N bits.
If the key operation function needs to be increased or decreased or adjusted, the table 1 is modified as needed, and the modified content is rewritten into the storage content of the read-only memory.
An edge of the scan pulse CP1 at the time when the state code register 500 latches data is referred to as a state latch edge, in the embodiment, a rising edge of the CP 1. In the embodiment, when a matrix keyboard S1 is pressed by a single key, after presetting and latching by a CP1, the key number 0000 is output by the encoding output ends C3-C0 from the state latching edge of the CP1 to the state latching edge of the next CP 1; when the matrix keyboard S2 single key is pressed down and is preset and latched by CP1, the key number 0001 is output from the state latching edge of CP1 to the state latching edge of the next CP 1; when the matrix keyboard is pressed S4 first and then S2 is pressed, the encoder 300 outputs a key number 0100 after the combination key is pressed at S2, preset and latched by CP1, starting from the state latch edge of CP1 and ending at the state latch edge of the next CP 1; when the matrix keyboard S1 single key is released and preset and latched by CP1, the key number 0101 is output from the state latching edge of CP1 to the state latching edge of the next CP 1; therefore, it can be seen that when a valid key operation of the matrix keyboard is recognized, the encoder 300 outputs a valid key number having a duration of one CP1 cycle width from the state latch edge of CP1 after the valid key operation to the state latch edge of the next CP 1.
In the embodiment, when the matrix keyboard S3 is pressed by a single key, the encoder 300 outputs a key number 0010 after presetting and latching by CP1 by the single key at S3, starting from the state latching edge of CP1 to the state latching edge of the next CP 1; after the CP1 presets and latches after the state latch edge of the next CP1 starts, the state latch edge of the next CP1 ends until the holding state of the single key press of S3 ends, and the encoder 300 outputs a key number 0011 from the state latch edge of the CP1 to the state latch edge of the next CP 1; it can thus be seen that when the sustained state of the matrix keyboard is identified, the duration of the encoder 300 outputting the valid key number is adapted to the duration of the sustained state.
When the state or operation of the keyboard is outside of the 6 valid keyboard operations and states described in table 1, the encoder 300 outputs an invalid key number 1111. Whether a valid key number is output or an invalid key number is output, the timing at which the encoder 300 changes the output content is the state latch edge of CP 1; in an embodiment, the moment when the encoder 300 changes the output content is the rising edge of CP 1.
The period of CP1 is the scan period of the matrix keyboard. When the scanning period of the keyboard is more than 20ms, the influence of keyboard key jitter can be effectively avoided; when the keyboard scanning period is below 100ms, keyboard operation is not missed; therefore, the period of the CP1 should be controlled to be 20-100 ms.
Fig. 7 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention. When a valid key operation of the matrix keyboard is recognized, the encoder 300 outputs a valid key number having a duration of one CP1 cycle width from the state latch edge of CP1 to the state latch edge of the next CP1 after the valid key operation. And the device for receiving the matrix type keyboard output signal needs to inquire the output of the matrix type keyboard at any time to acquire the key number. The periodic interval of the query must be less than the period of CP 1.
The circuit shown in fig. 7 is used for judging whether the key number output by the matrix keyboard is changed or not, when the key number output by the matrix keyboard is changed, a keyboard state change pulse is output, and the receiving device for assisting the matrix keyboard receives the key number output by the matrix keyboard, for example, the keyboard state change pulse is used as an interrupt request signal of the receiving device.
The circuit shown in fig. 7 is composed of a delay buffer 601, an xor gate 602, an xor gate 603, an xor gate 604, an xor gate 605, and an or gate 606. The delay buffer 601 is composed of 4 edge flip-flops only having a trigger function, and trigger input ends of the 4 edge flip-flops are receiving pulse input ends of the delay buffer 601 and are all connected to the CP 1; the delay buffer 601 performs data latching at the state latching edge of CP 1.
The delay buffer 601 delays the 4-bit data C3 to C0 at the encoding output terminal of the encoder 300. 4 data input ends D63-D60 of the delay buffer 601 are connected to encoding output ends C3-C0 of the encoder 300, and data correspondingly output by 4 data output ends Q63-Q60 of the delay buffer 601 are C31-C01; after the signals of C31-C01 are buffered by the first stage of the delay buffer 601, the signals are delayed by one CP1 pulse period compared with the signals of C3-C0, and FIG. 8 is a waveform diagram related to the effective operation of the keyboard according to the embodiment of the present invention. And setting the interval T1 of CP1 pulse, the matrix keyboard has one effective operation, and the effective operation of the embodiment comprises the following steps: an S1 single key press, an S2 single key press, an S3 single key press, an S1 press for the combined S4+ S1 operation, an S2 press for the combined S4+ S2 operation, and an S1 single key release. At the next state latch edge of an active operation, i.e., the rising edge after the interval of the CP1 pulse T1 in FIG. 8, the encodings C3-C0 output by the encoder 300 change; in the interval T2, the encoder 300 outputs effective codes C3-C0 with a CP1 pulse period; during the intervals T3, T4, and thereafter, the codes C3-C0 output by the encoder 300 change again and enter a hold state, which may be, for example, the S1 single key pressing the following hold state, outputting an invalid key number, or the S3 single key pressing the following hold state, outputting a valid key number, until the next valid operation.
The D6 pulse in fig. 8 schematically shows whether the codes C3 to C0 outputted from the encoder 300 are in the hold state, unchanged, or changed, and the D6 pulse does not exist in the actual circuit. As shown in fig. 8, the D6 pulse is low, which schematically shows that the codes C3 to C0 outputted from the encoder 300 are in a hold state and do not change; the D6 pulse is high, which schematically indicates that the encoder 300 outputs one cycle of valid codes C3-C0. Q6 in FIG. 8 reflects the change from C31 to C01, and it is clear that Q6 is delayed by one CP1 pulse period from D6. Also, the Q6 pulse is not present in an actual circuit.
In fig. 8, the codes C3 to C0 outputted from the encoder 300 are in a hold state, are unchanged, or are changed, and are actually completed by a logic circuit including a 4-bit delay buffer 601, an exclusive or gate 602, an exclusive or gate 603, an exclusive or gate 604, an exclusive or gate 605, and an or gate 606. The 4 exclusive or gates correspond to 1 bit of the encoding output terminals C3 to C0 of the encoder 300, and input signals of the 4-bit delay buffer 601 are input and output signals of the 4-bit delay buffer. For example, the two input signals of the xor gate 602 are C0 and C01, respectively, and C01 is delayed from C0 by one CP1 pulse period, so that when C0 changes, the xor gate 602 outputs a positive pulse of 1 CP1 pulse period width; when C0 is a CP1 pulse period width change signal, xor-gate 602 outputs a positive pulse of 2 CP1 pulse period widths. The xor gate 603, the xor gate 604, and the xor gate 605 respectively determine whether or not C1 to C3 have changed, and the principle is the same as that of determining whether or not C0 has changed. The output ends of the exclusive-or gate 602, the exclusive-or gate 603, the exclusive-or gate 604 and the exclusive-or gate 605 are respectively connected to the input end of the or gate 606, and the or gate 606 is used for comprehensively judging whether the C0-C3 change or not, so long as the C0-C3 change, the or gate 606 outputs a keyboard state change pulse F, and the pulse is a positive pulse.
In an embodiment, the delay buffer 601 selects the rising edge triggered 8D flip-flop 74HC 273.
Other schemes can be adopted for the delay buffer 601, for example, an RC circuit is adopted, and 4 RC circuits are used for respectively delaying C0-C3; if the delay time of the RC circuit is less than a CP1 pulse period, when the encoder 300 outputs effective codes C3-C0 of one period, a keyboard state change pulse is generated at the beginning of outputting the effective codes C3-C0 and at the end of outputting the effective codes C3-C0, and the width of the keyboard state change pulse is equal to the delay time of the RC circuit; if the delay time of the RC circuit is more than or equal to one CP1 pulse period, when the encoder 300 outputs the effective codes C3-C0 of one period, a keyboard state change pulse is generated at the beginning of outputting the effective codes C3-C0, and the pulse width is more than or equal to 2 CP1 pulse periods. The delay time of the RC circuit is required to not exceed 2 CP1 pulse periods in order to avoid false negatives.
In the circuit, the positioning of single key operation, combined key operation and keyboard maintenance state operation is controlled and converted into a state code with the same binary length by 2 pulses meeting specific time sequence requirements, and the state code is processed in a uniform coding mode, wherein the single key operation, the combined key operation and the keyboard maintenance state operation are only reflected on the difference of the state code; if the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the structure of the keyboard scanning circuit does not need to be modified, and the encoder 300 only needs to be updated according to the increased or decreased state code table, namely, the storage content of the read-only memory is rewritten and updated. The circuit of the invention does not use microcontrollers such as a singlechip and an ARM, does not need running programs, and has reliable work.
Claims (4)
1. A matrix keyboard reversal method scanning circuit which characterized in that: byXColumn-YThe device comprises a column key matrix, a row three-state buffer, a column three-state buffer, a row state register, a column state register, a first shift register, a second shift register, a state code register and an encoder;
the row lines of all the key matrixes are respectively connected to the output ends of the row three-state buffers, and the column lines of all the key matrixes are respectively connected to the column three-state buffersAn output terminal of (a); all input ends of the row tri-state buffer and the column tri-state buffer are connected to a low level; the row lines of all the key matrixes are respectively connected to the input end of the row state register, and the column lines of all the key matrixes are respectively connected to the input end of the column state register; the output end of the row state register and the output end of the column state register output togetherNA keyboard status signal; the above-mentionedN＝X＋Y；
The sampling pulse controls the alternate enabling of the row tri-state buffer and the column tri-state buffer to be effective; the column state register is used for latching data at the moment when the enabling of the row tri-state buffer is effectively and alternately converted into the enabling of the column tri-state buffer; the row state register performs data latch at the moment when the enabling of the column tri-state buffer is effectively and alternately converted into the enabling of the row tri-state buffer;
the first shift register, the second shift register and the state code register are synchronously controlled by scanning pulses and shifting pulses;
the first shift register hasNBit parallel input,NBit parallel output and serial output functions; the second shift register has a serial input,NA bit parallel output function; of said first shift registerNBit parallel input terminal connected toNA keyboard status signal output terminal; the serial input end of the second shift register is connected to the serial output end of the first shift register; the shift pulse input ends of the first shift register and the second shift register are connected to shift pulses, and the preset pulse input end of the first shift register is connected to the scanning pulse;
the status code register is 2NA bit binary register; in status code registersNWith bit data input connected to first shift registerNBit-parallel output, otherwiseNWith bit data input connected to second shift registerNA bit parallel output; the receiving pulse input end of the state code register is connected to the scanning pulse;
the encoder has 2 piecesNBit-coded input, said 2 inN2 in which the bit-encoded input is connected to the status code registerNBit data transmissionOutputting;
the time sequence of the scanning pulse and the shifting pulse meets the following requirements: the scanning pulses being shifting pulsesNDividing the frequency signal; the scanning pulse is a positive narrow pulse or a negative narrow pulse; the first shift register and the second shift register shift at the rising edge of the shift pulse at the same time, and the positive narrow pulse or the negative narrow pulse of the scanning pulse is positioned between the rising edges of the front shift pulse and the back shift pulse; or, the first shift register and the second shift register shift at the same time at the falling edge of the shift pulse, and the positive narrow pulse or the negative narrow pulse of the scanning pulse is between the falling edges of the two shift pulses;
when the preset pulse of the first shift register is effective in edge and the scanning pulse is a positive narrow pulse, the preset pulse of the first shift register is required to be effective in rising edge, and the receiving pulse of the state code register is required to be effective in falling edge; when the preset pulse of the first shift register is effective in edge and the scanning pulse is negative narrow pulse, the preset pulse of the first shift register is required to be effective in falling edge, and the receiving pulse of the state code register is required to be effective in rising edge; when the preset pulse of the first shift register is high-level effective, the scanning pulse is required to be a positive narrow pulse, and the receiving pulse of the state code register is effective at a falling edge; when the preset pulse of the first shift register is effective at a low level, the scanning pulse is required to be a negative narrow pulse, and the receiving pulse of the state code register is effective at a rising edge.
2. The matrix keyboard inversion scanning circuit of claim 1, wherein: enabling the row tri-state buffer to be effective at the low level of the sampling pulse, and enabling the column tri-state buffer to be effective at the high level of the sampling pulse; the column state register latches data at a rising edge of the sampling pulse, and the row state register latches data at a falling edge of the sampling pulse.
3. The matrix keyboard inversion scanning circuit of claim 1, wherein: enabling the row tri-state buffer to be effective at the high level of the sampling pulse, and enabling the column tri-state buffer to be effective at the low level of the sampling pulse; the column state register latches data at a falling edge of the sampling pulse, and the row state register latches data at a rising edge of the sampling pulse.
4. The matrix keyboard inversion scanning circuit according to any one of claims 1-3, wherein: 2 register of the state codeNBit data output 2 inNA status code of the bit; the state code consists of a valid state code and an invalid state code; the key number output by the encoder consists of an effective key number and an ineffective key number; the effective state codes are generated by the operation or the state of an effective keyboard, and corresponding effective key numbers are correspondingly output when the encoder inputs each effective state code; the invalid state code is generated by invalid keyboard operation or state, and when the encoder inputs all the invalid state codes, the encoder correspondingly outputs invalid key numbers; the encoder hasMA bit key number output terminal for outputting a bit key number,Mthe value should be selected to satisfy 2 M Greater than or equal to the sum of the number of valid and invalid key numbers.
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| CN201610003404.5A CN105680874B (en) | 2016-01-05 | 2016-01-05 | Matrix keyboard scanning circuit and scanning encoding method |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3675239A (en) * | 1970-09-14 | 1972-07-04 | Ncr Co | Unlimited roll keyboard circuit |
| US4282516A (en) * | 1979-06-13 | 1981-08-04 | Rca Corporation | Keyboard encoding arrangement |
| CN1034650A (en) * | 1988-01-19 | 1989-08-09 | Rca许可公司 | Keyboard identfication apparatus |
| JP2005165401A (en) * | 2003-11-28 | 2005-06-23 | Toshiba Corp | Electronic device and method for obtaining code |
| CN201251769Y (en) * | 2008-08-12 | 2009-06-03 | 无敌科技(西安)有限公司 | Device capable of locking keystroke |
| CN101789793A (en) * | 2010-01-15 | 2010-07-28 | 电子科技大学中山学院 | Determinant linear array coordinate scanning circuit |
| CN101840268A (en) * | 2010-04-23 | 2010-09-22 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
| CN202059394U (en) * | 2011-05-09 | 2011-11-30 | 广州励丰声光科技有限公司 | Matrix keyboard scanning device based on programmable element |
| CN103279197A (en) * | 2013-06-08 | 2013-09-04 | 湖南工业大学 | Keyboard scanning positioning method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101609370A (en) * | 2009-07-21 | 2009-12-23 | 李治勋 | A kind of keyboard and method of work thereof |
-
2016
- 2016-01-05 CN CN201810455310.0A patent/CN108880560B/en not_active Expired - Fee Related
- 2016-01-05 CN CN201610003404.5A patent/CN105680874B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3675239A (en) * | 1970-09-14 | 1972-07-04 | Ncr Co | Unlimited roll keyboard circuit |
| US4282516A (en) * | 1979-06-13 | 1981-08-04 | Rca Corporation | Keyboard encoding arrangement |
| CN1034650A (en) * | 1988-01-19 | 1989-08-09 | Rca许可公司 | Keyboard identfication apparatus |
| JP2005165401A (en) * | 2003-11-28 | 2005-06-23 | Toshiba Corp | Electronic device and method for obtaining code |
| CN201251769Y (en) * | 2008-08-12 | 2009-06-03 | 无敌科技(西安)有限公司 | Device capable of locking keystroke |
| CN101789793A (en) * | 2010-01-15 | 2010-07-28 | 电子科技大学中山学院 | Determinant linear array coordinate scanning circuit |
| CN101840268A (en) * | 2010-04-23 | 2010-09-22 | 中国电子科技集团公司第五十四研究所 | Method for fast scanning and positioning of matrix keyboard |
| CN202059394U (en) * | 2011-05-09 | 2011-11-30 | 广州励丰声光科技有限公司 | Matrix keyboard scanning device based on programmable element |
| CN103279197A (en) * | 2013-06-08 | 2013-09-04 | 湖南工业大学 | Keyboard scanning positioning method |
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| CN105680874B (en) | 2018-06-26 |
| CN108880560A (en) | 2018-11-23 |
| CN105680874A (en) | 2016-06-15 |
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