CN108649962B

CN108649962B - Independent keyboard scanning coding method

Info

Publication number: CN108649962B
Application number: CN201810455342.0A
Authority: CN
Inventors: 聂辉; 凌云; 孔玲爽
Original assignee: Hunan University of Technology
Current assignee: Hunan University of Technology
Priority date: 2016-01-05
Filing date: 2016-01-05
Publication date: 2022-01-21
Anticipated expiration: 2036-01-05
Also published as: CN108649962A; CN105680873A; CN105680873B

Abstract

A scanning coding method for an independent keyboard comprises the steps that an independent keyboard with N keys outputs N-bit keyboard state signals; carrying out data latch on the N-bit keyboard state signal according to the scanning pulse to obtain a current state key value, carrying out state latch on the current state key value and a previous state key value by the scanning pulse to obtain a 2 multiplied by N-bit state code, shifting the current state key value by the N shifting pulses to obtain the sequence of the previous state key value, and carrying out corresponding operation repeatedly; the state code is encoded and the key number is output, and the state code is realized by a circuit comprising an independent keyboard, a first shift register, a second shift register, a state code register and an encoder. If the key operation function needs to be increased or decreased or adjusted, the circuit structure does not need to be modified, and the encoding content of the encoder only needs to be changed according to the corresponding relation between the increased or decreased state code and the key number. The method does not need to write and run programs and works reliably.

Description

Independent keyboard scanning coding method

The invention discloses a separated application, which has an original application number of 201610003266.0 and an application date of 2016, 1 and 5 and is named as an independent keyboard scanning coding circuit.

Technical Field

The invention relates to a scanning and positioning method of a keyboard, in particular to a scanning and encoding method of an independent keyboard.

Background

With the continuous development of embedded technology, various electronic products generally adopt a microcontroller as a control core and a keyboard as a main input device, and are widely applied.

The existing keyboard scanning is mainly controlled by a microcontroller, and is performed by running a program in the microcontroller, so that the program runs off due to interference, and the scanning program cannot work normally.

The invention patent with application number CN201010153560.2, "a method for fast scanning and positioning matrix keyboard", adopts a mode of keyboard interrupt triggering to enter the scanning and positioning process of keyboard, adopts a method of repeating the keyboard scanning step for many times to judge whether the key is valid, and makes state judgment on the obtained key value; if the multiple sampling states are the same, the key value is in a stable state and is valid; if the multiple sampling states are different, the key value is invalid. The single key operation or the combined key operation needs to be judged separately, if the single key operation is carried out, the single key processing mode is entered; if the operation is a combination key operation, a combination key processing mode is entered. The method disclosed in the patent solves the problems of wrong keys, continuous key touch and other errors caused by keyboard shaking due to the mechanical characteristics of the keyboard, and the problem of supporting combined keys and repeated keys. But the single key operation and the combined key operation of the method need to be processed respectively; a keyboard operation function of executing effective operation after a certain period of time of maintaining the keyboard state is not considered; when the key operation function is increased or decreased or adjusted, the structure of the keyboard scanning and positioning program needs to be modified.

Disclosure of Invention

In order to solve the technical problems of the existing keyboard scanning and positioning method, the invention provides a scanning and encoding method of an independent keyboard, which comprises the steps that the independent keyboard with N keys outputs N-bit keyboard state signals; carrying out data latch on the N-bit keyboard state signal according to the scanning pulse to obtain a current state key value, carrying out state latch on the current state key value and a previous state key value by the scanning pulse to obtain a 2 multiplied by N-bit state code, shifting the current state key value by the N shifting pulses to obtain the sequence of the previous state key value, and carrying out corresponding operation repeatedly; the status code is encoded and the key number is output. The N-bit keyboard state signal is a level signal.

The time sequence of the scanning pulse and the shifting pulse meets the following requirements: in one period, the scan pulse has 1 pulse, and the shift pulse has N pulses; the scanning pulse and the shifting pulse are repeated according to the sequence of 1 scanning pulse and N shifting pulses. The period of the scanning pulse is 20-100 ms.

The scanning pulse and the shifting pulse are generated by a circuit consisting of an oscillator, a counter and a pulse distributor; the clock pulse output by the oscillator is sent to a counter for counting, the output of the counter is sent to the input of a pulse distributor, and the pulse distributor outputs a scanning pulse and a shifting pulse.

The pulse distributor is realized by adopting a ROM (read only memory); the address input of the ROM is connected to the output of the counter, and the 2-bit data output end of the ROM outputs scanning pulse and shifting pulse.

The state code consists of an effective state code and an ineffective state code and is used for identifying the current state and the operation state of the independent keyboard; the key number is composed of a valid key number and an invalid key number; the effective state code is generated by the operation or the state of an effective keyboard, and a corresponding effective key number is correspondingly output; the invalid state code is generated by invalid keyboard operation or state and correspondingly outputs an invalid key number; the key number is M bits, and the selection of the M value should satisfy 2^MGreater than or equal to the sum of the number of valid and invalid key numbers.

The effective keyboard operation comprises single-key pressing operation, single-key releasing operation, single-key pressing maintaining operation and combined key operation; the combined key operation refers to the operation that after a single key is pressed down, other keys are pressed down; the invalid keyboard operation is an operation other than the valid keyboard operation.

The encoding of the state code and the output of the key number are realized by an encoder. Further, the encoder is a read-only memory; the key operation function is increased or decreased or adjusted by modifying the storage content of the read-only memory.

The scanning pulse carries out data latch on the N-bit keyboard state signals to obtain the current state key value, and the N shifting pulses carry out shifting on the current state key value to obtain the previous state key value and are realized by the first shifting register and the second shifting register. The first shift register has N-bit parallel input, N-bit parallel output and serial output functions; the second shift register has serial input and N-bit parallel output functions. The N-bit parallel input end of the first shift register is connected to the N-bit keyboard state signal output end; the serial input end of the second shift register is connected to the serial output end of the first shift register; the shift pulse input ends of the first shift register and the second shift register are connected to shift pulses, and the preset pulse input end of the first shift register is connected to the scanning pulse.

The scanning pulse performs state latch on the current state key value and the previous state key value to obtain a 2 multiplied by N state code which is realized by a state code register. The state code register is a 2 XN bit binary register; an N-bit data input end in the state code register is connected to an N-bit parallel output end of the first shift register, and the other N-bit data input end is connected to an N-bit parallel output end of the second shift register; and the receiving pulse input end of the state code register is connected to the scanning pulse.

And the shifting pulse edges of the first shifting register and the second shifting register are effective.

When the preset pulse of the first shift register is effective in edge and the scanning pulse is positive pulse, the preset pulse of the first shift register is required to be effective in rising edge, and the receiving pulse of the state code register is required to be effective in falling edge; when the preset pulse of the first shift register is edge-effective and the scan pulse is negative pulse, the preset pulse of the first shift register is required to be falling edge-effective, and the receiving pulse of the state code register is required to be rising edge-effective. When the preset pulse of the first shift register is high-level effective, the scanning pulse is required to be positive pulse, and the receiving pulse of the state code register is effective at a falling edge; when the preset pulse of the first shift register is in low level and effective, the scanning pulse is required to be a negative pulse, and the receiving pulse of the state code register is in rising edge and effective.

The N-bit keyboard state signals and the N keys meet one-to-one correspondence. The N bits, 2 XN bits and M bits all refer to binary bit data.

The independent keyboard scanning and encoding method is realized by an independent keyboard scanning and encoding circuit, and the independent keyboard operation identification and encoding circuit comprises an independent keyboard, a first shift register, a second shift register, a state code register and an encoder.

Furthermore, the scanning and encoding method of the independent keyboard further comprises a keyboard state change pulse generating unit which is used for judging whether the key number output by the independent keyboard changes or not, and outputting the keyboard state change pulse when the key number output by the independent keyboard changes.

The keyboard state change pulse generation unit consists of an OR gate, an M-bit delay buffer and M XOR gates; the M-bit delay buffer is used for respectively carrying out signal delay on the M-bit key numbers output by the independent keyboard; the inputs of the M exclusive-OR gates are input signals and output signals of the M-bit delay buffer respectively; the outputs of the M exclusive-OR gates are respectively connected to the input ends of the OR gates; the output end of the OR gate outputs a keyboard state change pulse.

The invention has the beneficial effects that: scanning and positioning of single key operation, combined key operation and keyboard maintenance state are controlled and converted into state codes with the same binary length by scanning pulses and shifting pulses meeting specific time sequence requirements, and the state codes are processed in a unified coding mode, wherein the single key operation, the combined key operation and the keyboard maintenance state operation are only reflected on the difference of the state codes; if the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the circuit structure does not need to be modified, and the encoding content of the encoder only needs to be changed according to the corresponding relation between the increased or decreased state code and the key number, namely the storage content written into the read-only memory is modified again. The method does not use microcontrollers such as a single chip microcomputer and an ARM, does not need running programs, and works reliably.

Drawings

FIG. 1 is a functional block diagram of a stand alone keyboard scan encoding circuit;

FIG. 2 is a circuit diagram of a stand alone keyboard according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of scan encoding according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a first shift register according to an embodiment of the present invention;

FIG. 5 is a pulse timing diagram of an embodiment of the present invention;

FIG. 6 is a schematic diagram of a pulse circuit of an embodiment of the present invention;

FIG. 7 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention;

FIG. 8 is a waveform diagram illustrating the effective operation of a keyboard according to an embodiment of the present invention.

Detailed Description

The invention is further described below with reference to the accompanying drawings.

Fig. 1 is a schematic block diagram of a stand-alone keyboard scanning encoding circuit, which is composed of a stand-alone keyboard 400, a first shift register 100, a second shift register 200, a status code register 500 and an encoder 300.

Fig. 2 is a circuit diagram of a stand-alone keyboard 400 of an embodiment of the present invention, having 4 keys, which is composed of a key S1, a key S2, a key S3, a key S4, and a pull-up resistor R1, a pull-up resistor R2, a pull-up resistor R3, and a pull-up resistor R4 connected to a power supply + VCC. The 4 output ends of the independent keyboard 400 respectively output status signals I1, I2, I3 and I4 of a key S1, a key S2, a key S3 and a key S4 in a one-to-one correspondence mode, and when the key is pressed down, the status signal of the corresponding output end is at a low level; when the key is not pressed, the state signal of the corresponding output end is high level.

The first shift register 100, the second shift register 200, the status code register 500, and the encoder 300 in fig. 1 form a scan encoding circuit, and a circuit diagram of an embodiment thereof is shown in fig. 3. The status signal output by the independent keyboard circuit of the embodiment has 4 bits, therefore, the first shift register 100 and the second shift register 200 are both 4-bit binary shift registers, wherein the first shift register 100 has the functions of parallel input, parallel output and serial output, and the second shift register 200 has the functions of serial input and parallel output; the 4 parallel input ends L0-L3 of the first shift register 100 are connected to I1, I2, I3 and I4 in sequence, and the serial input end D2 of the second shift register 200 is connected to the serial output end Q13 of the first shift register 100. The shift pulse inputs CLK1 and CLK2 of the first and

second shift registers

100 and 200 are connected to a shift pulse CP2, and the preset pulse input CLK0 of the first shift register 100 is connected to a scan pulse CP 1.

The status code register 500 is required to register 8-bit binary data, 4 bits of the 8-bit data input terminals D57-D50 thereof are connected to the parallel output terminals Q13-Q10 of the first shift register 100, and the other 4 bits are connected to the parallel output terminals Q23-Q20 of the second shift register 200; in the embodiment, D57-D54 are connected to Q23-Q20, and D53-D50 are connected to Q13-Q10. The receiving pulse input terminal CLK5 of the state code register 500 is connected to the scan pulse CP 1.

The 8 inputs A7-A0 of the encoder 300 are connected to the 8 data outputs Q57-Q50 of the status code register 500. The encoder 300 outputs a 4-bit binary key number determined by the scan encoding.

In the embodiment of fig. 3, the second shift register 200 may alternatively be composed of various kinds of middle-scale integrated shift registers, or may alternatively be composed of edge flip-flops; when the second shift register 200 is formed of edge flip-flops, it is preferably formed of edge-triggered D flip-flops. The status code register 500 is composed of edge flip-flops, preferably edge-triggered D flip-flops, for example, a select dual D flip-flop CD4013, or a 4D flip-flop 74HC175, or an 8D flip-flop 74HC 273.

FIG. 4 is a circuit diagram of a first shift register 100 according to an embodiment of the present invention, which includes 4D flip-flops 101-104 with both set and reset functions active at high level, and 8 NOR gates 105-112. In one embodiment, D flip-flops 101-104 are selected to be dual D flip-flops CD4013, which have active rising edges of the trigger pulses. The scan pulse CP1 controls the set and reset functions of the D flip-flops 101 to 104 through 8 NOR gates 105 to 112. Taking the D flip-flop 101 as an example, when the scan pulse CP1 is at a high level, the nor gate 105 and the nor gate 106 output a low level, and the set and reset functions of the D flip-flop 101 are disabled; when the scan pulse CP1 is low and L0 is 0, the output of the nor gate 105 is

The output of the nor gate 106 is L0, that is, the set function and the reset function of the D flip-flop 101 are disabled, so that Q10 is 0; when the scan pulse CP1 is low and L0 is 1, the output of the nor gate 105 is

The output of the nor gate 106 is L0, i.e., the set function and the reset function of the D flip-flop 101 are enabled and disabled, making Q10 equal to 1. The working principle of the D flip-flops 102 to 104 is the same as that of the D flip-flop 101, and when the scan pulse CP1 is at a low level, Q10 is L0, Q11 is L1, Q12 is L2, and Q13 is L3; when the scan pulse CP1 is at a high level, the trigger pulse inputs CLK10, CLK11, CLK12, and CLK13 of the D flip-flops 101 to 104 are all connected to the CP2, so that the first shift register 100 shifts one bit at the rising edge of each shift pulse CP2, i.e., Q13 equals Q12, Q12 equals Q11, Q11 equals Q10, and Q10 equals 0.

In the embodiment of fig. 3, the encoder 300 is a read-only memory. The address input ends A7-A0 of the ROM are the input ends of the encoder 300, and the data output ends D3-D0 of the ROM are the encoding output ends C3-C0 of the encoder 300.

The working principle of the independent keyboard scanning and encoding method is as follows:

the scan encoding circuit operates under the control of the scan pulse CP1 and the shift pulse CP2, and the timing chart of the pulses is as shown in fig. 5.

The timing of CP1 and CP2 in the embodiment meets the following requirements: in one cycle, CP1 has 1 pulse and CP2 has 4 pulses; the pulses are repeated in the order of 1 CP1 pulse and 4 CP2 pulses.

The CP1 and CP2 pulses meeting the timing requirement can be generated by various pulse distributors, and fig. 6 is a schematic diagram of a pulse circuit of an embodiment of the present invention, which is composed of an oscillator 801, a counter 802, and a pulse distributor 803. The clock pulse CP in fig. 5 is generated by an oscillator, CP is sent to the counter 802 for counting, the counter 802 is a 10-ary counter, and the 10 states (values) of the result P are sequentially P0 → P9, as shown in fig. 5. The pulse distributor 803 in an embodiment is implemented using a ROM memory, referred to herein as a pulse distribution ROM memory. The address input of the pulse allocation ROM memory is connected to the count output of the counter 802, and the 2-bit data output of the pulse allocation ROM memory is respectively output as a CP1 pulse and a CP2 pulse. The write contents of the burst allocation ROM memory are shown in table 1.

TABLE 1 pulse Allocation ROM memory data sheet

The ROM memory address, i.e. the counter output, in table 1 is at least a 4-bit binary code. Generally, if the counter 802 adopts binary plus method, the P0-P9 sequentially correspond to 4-bit binary codes 0000-1001, i.e. the ROM memory address range is 0000-1001, and the storage contents of the addresses 0000-1001 are the contents corresponding to P0-P9 in Table 1.

Burst allocation ROM memories require 2-bit data output. When the address input of the pulse distribution ROM is provided with R bits, and when the independent keyboard has N-bit keyboard state signal output, the selection of R needs to satisfy 2^R2 x (N +1) or more.

Oscillator 801 is a multivibrator. The period of the scan pulse CP1 is 20-100 ms. The CP1, CP2 may also be provided by circuitry or means other than the standalone keypad scan encoding circuitry.

The first shift register 100 latches data of status signals I1, I2, I3 and I4 output by the independent keyboard 400 under the control of the scan pulse CP1, and at this time, the output of the first shift register 100 is called as an on-state key value; the second shift register 200 shifts the output of the scan pulse CP1 latched to the first shift register 100 in the previous period to the output of the second shift register 200 under the control of 4 CP2 pulses in the previous period, so the output of the second shift register 200 at this time is called the previous state key value.

The scan pulse CP1 latches the current key value output by the first shift register 100 and the previous key value output by the second shift register 200 at the output terminal of the status code register 500, and the outputs of the status code register 500 are the previous key value and the current key value.

Since the shift pulses of the first and

second shift registers

100 and 200 are edge-active, the CP2 may be a positive pulse or a negative pulse.

When the preset pulse of the first shift register 100 is edge-active and the scan pulse CP1 is positive pulse, it is required that the preset pulse of the first shift register 100 is rising edge-active and the received pulse of the status code register 500 is falling edge-active; when the preset pulse of the first shift register 100 is edge-active and the scan pulse CP1 is negative, it is required that the preset pulse of the first shift register 100 is falling-active and the received pulse of the status code register 500 is rising-active. When the preset pulse of the first shift register 100 is active at a high level, the scan pulse CP1 is required to be a positive pulse, and the received pulse of the status code register 500 is active at a falling edge; when the preset pulse of the first shift register 100 is active low, the scan pulse CP1 is required to be negative, and the received pulse of the status code register 500 is active rising. In the embodiment, the preset pulse of the first shift register 100 is active low, so the scan pulse CP1 is negative, and the received pulse of the status code register 500 is active on the rising edge.

In the embodiment, the 4-bit present key value and the 4-bit previous key value output by the data output terminal of the status code register 500 together form an 8-bit status code. The 8-bit state code is used for identifying the current state and the operation state of the independent keyboard. For example, in the present embodiment, the status code of no key depression is 11111111; the status code of the single key press operation of the S1 key is 11111110; the state code of S1 key single key press and maintenance is 11101110; the state code of the S1 key single-key release operation is 11101111; the state code of the single key press operation of the S2 key is 11111101; the state code of the single key press operation of the S4 key is 11110111; the S1 pressing operation of the S2+ S1 combination operation indicates an operation of pressing S1 after pressing S2 first, and the status code of this operation is 11011100 while maintaining the pressed state at S2.

The encoder 300 is used to convert the status code into a key number. In an embodiment, there are 7 valid keyboard operations and states, including:

operation 0: a single key press operation of the key S1, the key number being 0000;

operation 1: a single key of the key S2 is pressed, and the key number is 0001;

operation 2: a single key of the key S3 is pressed, with the key number 0010;

operation 3: the key S3 is in a maintenance state after the single key is pressed, and the key number is 0011;

and operation 4: after the single key of the key S4 is pressed, the combined key of the key S1 is pressed for operation, and the key number is 0100;

operation 5: after the single key of the key S4 is pressed, the combined key of the key S2 is pressed for operation, and the key number is 0101;

operation 6: the single key release operation of the key S1 has a key number of 0110.

The state code and key number obtained according to the above specification are shown in code table 2:

TABLE 2 coding table

Keyboard operation	Status code (Address)	Key number (storage data)
			S1 Single Key Pushing	11111110	0000
S2 Single Key Pushing	11111101	0001
			S3 Single Key Pushing	11111011	0010
S3 Single Key Press Retention	10111011	0011
			Combined operation of S4+ S1	01110110	0100
Combined operation of S4+ S2	01110101	0101
			S1 Single bond Release	11101111	0110
Other operations or states	********	1111

The encoder 300 is a combinational logic circuit, and the designed circuit satisfies the logical relationship of table 2.

The encoder 300 of an embodiment is preferably comprised of read only memory. The selected ROM has 8-bit address, 2⁸4 bit binary memory cells. 7 effective keyboard operation and states have 7 effective state codes corresponding to 7 effective key numbers; the state codes are written as the addresses a7 to a0 of the read only memory, and the corresponding key numbers are written as the storage data in the storage cells corresponding to the 7 valid state codes. The status codes generated for the 7 valid keyboard operations and states are invalid status codes, i.e. the status codes generated for the other operations or states in table 2 are invalid status codes; in the other memory cells, an invalid key number, which is a value other than 7 valid key numbers, is written all over, and in the embodiment, the invalid key number is 1111.

The read-only memory is always operated in a data output state. When the read-only memory has chip selection control and data output buffer control functions, the chip selection control and the data output buffer control are in an effective state.

The key number in the embodiment is a 4-bit binary code. The binary digit number of the key number can be increased or decreased according to the requirement, and at the moment, only the matched read-only memory is needed to be selected. Assuming that the number of binary digits of the key number is M, the value of M should be selected to satisfy 2^MGreater than or equal to the sum of the number of valid and invalid key numbers. When the independent keyboard has N-bit keyboard state signal output, the read-only memory needs 2 XN-bit address input and M-bit data output.

If the key operation function needs to be increased or decreased or adjusted, the table 2 is modified as needed, and the modified content is rewritten into the storage content of the read-only memory.

An edge of the scan pulse CP1 at the time when the state code register 500 latches data is referred to as a state latch edge, in the embodiment, a rising edge of the CP 1. In the embodiment, when the single key of the independent keyboard S1 is pressed, the encoder 300 outputs the key number 0000 from the state latch edge of CP1 to the state latch edge of the next CP1 after the single key of S1 is pressed and the CP1 is preset and latched; when the independent keyboard S2 single key is pressed, the encoder 300 outputs the key number 0001 after the single key is pressed at S2, preset and latched by CP1, starting from the state latching edge of CP1 to the state latching edge of the next CP 1; when the independent keyboard firstly presses S4 and then presses S1, the encoder 300 outputs a key number 0100 from the state latch edge of CP1 to the state latch edge of the next CP1 after the combined key is pressed at S1 and preset and latched by CP 1; when the independent keyboard firstly presses S4 and then presses S2, the encoder 300 outputs a key number 0101 from the state latch edge of CP1 to the state latch edge of the next CP1 after the combined key is pressed at S2 and preset and latched by CP 1; when the independent keyboard S1 is released by a single key, the encoder 300 releases the single key at S1, after presetting and latching by CP1, the key number 0110 is output from the state latching edge of CP1 to the state latching edge of the next CP 1; it can be seen that when a valid key operation of the stand-alone keyboard is recognized, the encoder 300 outputs a valid key number having a duration of one CP1 cycle width starting at the state latch edge of CP1 after the valid key operation until the state latch edge of the next CP 1.

In the embodiment, when the single key of the independent keyboard is pressed by the S3, the encoder 300 outputs a key number 0010 after the single key is pressed by the S3, preset and latched by the CP1, and from the state latching edge of the CP1 to the state latching edge of the next CP 1; after the CP1 presets and latches after the state latch edge of the next CP1 starts, the state latch edge of the next CP1 ends until the holding state of the single key press of S3 ends, and the encoder 300 outputs a key number 0011 from the state latch edge of the CP1 to the state latch edge of the next CP 1; it can thus be seen that when a sustained state of the stand-alone keyboard is identified, the duration of the encoder 300 outputting a valid key number is adapted to the duration of the sustained state.

When the state or operation of the keyboard is outside the 7 valid keyboard operations and states described in table 2, the encoder 300 outputs an invalid key number 1111. Whether a valid key number is output or an invalid key number is output, the timing at which the encoder 300 changes the output content is the state latch edge of CP 1; in an embodiment, the moment when the encoder 300 changes the output content is the rising edge of CP 1.

The period of CP1 is the scan period of the free standing keyboard. When the scanning period of the keyboard is more than 20ms, the influence of keyboard key jitter can be effectively avoided; when the keyboard scanning period is below 100ms, keyboard operation is not missed; therefore, the period of the CP1 should be controlled to be 20-100 ms.

Fig. 7 is a circuit diagram of a keyboard state change pulse generating unit according to an embodiment of the present invention. When a valid key operation of the independent keyboard is recognized, the encoder 300 outputs a valid key number having a duration of one CP1 cycle width from the state latch edge of CP1 to the state latch edge of the next CP1 after the valid key operation. And the device for receiving the output of the independent keyboard inquires the output of the independent keyboard at any time to acquire the key number. The periodic interval of the query must be less than the period of CP 1.

The circuit shown in fig. 7 is used for judging whether the key number output by the independent keyboard is changed or not, outputting a keyboard state change pulse when the key number output by the independent keyboard is changed, and assisting the receiving device of the independent keyboard to receive the key number output by the independent keyboard, for example, using the keyboard state change pulse as an interrupt request signal of the receiving device.

The circuit shown in fig. 7 is composed of a delay buffer 601, an xor gate 602, an xor gate 603, an xor gate 604, an xor gate 605, and an or gate 606. The delay buffer 601 is composed of 4 edge flip-flops only having a trigger function, and trigger input ends of the 4 edge flip-flops are receiving pulse input ends of the delay buffer 601 and are all connected to the CP 1; the delay buffer 601 performs data latching at the state latching edge of CP 1.

The delay buffer 601 delays the 4-bit data C3 to C0 at the encoding output terminal of the encoder 300. 4 data input ends D63-D60 of the delay buffer 601 are connected to encoding output ends C3-C0 of the encoder 300, and data correspondingly output by 4 data output ends Q63-Q60 of the delay buffer 601 are C31-C01; after the signals of C31-C01 are buffered by the first stage of the delay buffer 601, the signals are delayed by one CP1 pulse period compared with the signals of C3-C0, and FIG. 8 is a waveform diagram related to the effective operation of the keyboard according to the embodiment of the present invention. Setting the interval T1 of CP1 pulse, the independent keyboard has one effective operation, the effective operation of the embodiment includes: an S1 single key press, an S2 single key press, an S3 single key press, an S1 press for the combined S4+ S1 operation, an S2 press for the combined S4+ S2 operation, and an S1 single key release. At the next state latch edge of an active operation, i.e., the rising edge after the interval of the CP1 pulse T1 in FIG. 8, the encodings C3-C0 output by the encoder 300 change; in the interval T2, the encoder 300 outputs effective codes C3-C0 with a CP1 pulse period; during the intervals T3, T4, and thereafter, the codes C3-C0 output by the encoder 300 change again and enter a hold state, which may be, for example, the S1 single key pressing the following hold state, outputting an invalid key number, or the S3 single key pressing the following hold state, outputting a valid key number, until the next valid operation.

The D6 pulse in fig. 8 schematically shows whether the codes C3 to C0 outputted from the encoder 300 are in the hold state, unchanged, or changed, and the D6 pulse does not exist in the actual circuit. As shown in fig. 8, the D6 pulse is low, which schematically shows that the codes C3 to C0 outputted from the encoder 300 are in a hold state and do not change; the D6 pulse is high, which schematically indicates that the encoder 300 outputs one cycle of valid codes C3-C0. Q6 in FIG. 8 reflects the change from C31 to C01, and it is clear that Q6 is delayed by one CP1 pulse period from D6. Also, the Q6 pulse is not present in an actual circuit.

In fig. 8, the codes C3 to C0 outputted from the encoder 300 are in a hold state, are unchanged, or are changed, and are actually completed by a logic circuit including a 4-bit delay buffer 601, an exclusive or gate 602, an exclusive or gate 603, an exclusive or gate 604, an exclusive or gate 605, and an or gate 606. The 4 exclusive or gates correspond to 1 bit of the encoding output terminals C3 to C0 of the encoder 300, and input signals of the 4-bit delay buffer 601 are input and output signals of the 4-bit delay buffer. For example, the two input signals of the xor gate 602 are C0 and C01, respectively, and C01 is delayed from C0 by one CP1 pulse period, so that when C0 changes, the xor gate 602 outputs a positive pulse of 1 CP1 pulse period width; when C0 is a CP1 pulse period width change signal, xor-gate 602 outputs a positive pulse of 2 CP1 pulse period widths. The xor gate 603, the xor gate 604, and the xor gate 605 respectively determine whether or not C1 to C3 have changed, and the principle is the same as that of determining whether or not C0 has changed. The output ends of the exclusive-or gate 602, the exclusive-or gate 603, the exclusive-or gate 604 and the exclusive-or gate 605 are respectively connected to the input end of the or gate 606, and the or gate 606 is used for comprehensively judging whether the C0-C3 change or not, so long as the C0-C3 change, the or gate 606 outputs a keyboard state change pulse F, and the pulse is a positive pulse.

In an embodiment, the delay buffer 601 selects the rising edge triggered 8D flip-flop 74HC 273.

Other schemes can be adopted for the delay buffer 601, for example, an RC circuit is adopted, and 4 RC circuits are used for respectively delaying C0-C3; if the delay time of the RC circuit is less than a CP1 pulse period, when the encoder 300 outputs effective codes C3-C0 of one period, a keyboard state change pulse is generated at the beginning of outputting the effective codes C3-C0 and at the end of outputting the effective codes C3-C0, and the width of the keyboard state change pulse is equal to the delay time of the RC circuit; if the delay time of the RC circuit is more than or equal to one CP1 pulse period, when the encoder 300 outputs the effective codes C3-C0 of one period, a keyboard state change pulse is generated at the beginning of outputting the effective codes C3-C0, and the pulse width is more than or equal to 2 CP1 pulse periods. The delay time of the RC circuit is required to not exceed 2 CP1 pulse periods in order to avoid false negatives.

In the circuit, the positioning of single key operation, combined key operation and keyboard maintenance state operation is controlled and converted into a state code with the same binary length by 2 pulses meeting specific time sequence requirements, and the state code is processed in a uniform coding mode, wherein the single key operation, the combined key operation and the keyboard maintenance state operation are only reflected on the difference of the state code; if the key operation function needs to be increased or decreased or the key operation function needs to be adjusted, the structure of the keyboard scanning circuit does not need to be modified, and the encoder 300 only needs to be updated according to the increased or decreased state code table, namely, the storage content of the read-only memory is rewritten and updated. The circuit of the invention does not use microcontrollers such as a singlechip and an ARM, does not need running programs, and has reliable work.

Claims

1. A free-standing keyboard scanning coding method is characterized in that: comprises thatNIndependent keyboard output of individual keysNA keyboard status signal; according to the scanning pulse pairNThe state signal of the bit keyboard is subjected to data latch to obtain the present state key value, and the scanning pulse is subjected to state latch on the present state key value and the previous state key value to obtain 2NThe status code of the bit or bits is,Nshifting the current-state key value by the shift pulses to obtain the sequence of the previous-state key value, and repeating the steps; encoding the status code and outputting a key number; the bits are binary bits;

the time sequence of the scanning pulse and the shifting pulse meets the following requirements: in one period, the scan pulse has 1 pulse, and the shift pulse hasNA pulse; the scanning pulse and the shift pulse are in accordance with 1 scanning pulse,NThe sequence of the shift pulses is repeated;

the state code is coded and the key number is output by the coder;

the scanning pulse pairNThe bit keyboard status signal is latched to obtain the present key value, anNThe shifting pulse shifts the current-state key value to obtain a previous-state key value, and the previous-state key value is realized by a first shift register and a second shift register;

the first shift register hasNBit parallel input,NBit parallel output and serial output functions; the second shift register has a serial input,NA bit parallel output function;

of said first shift registerNBit parallel input terminal connected toNA keyboard status signal output terminal; the serial input end of the second shift register is connected to the serial output end of the first shift register; shift pulses of first shift register and second shift registerThe pulse input ends are connected to the shift pulses, and the preset pulse input end of the first shift register is connected to the scanning pulse;

the scanning pulse carries out state latch on the present state key value and the previous state key value to obtain 2NThe status code of the bit is implemented by a status code register; the status code register is 2NA bit binary register; in status code registersNWith bit data input connected to first shift registerNBit-parallel output, otherwiseNWith bit data input connected to second shift registerNA bit parallel output; and the receiving pulse input end of the state code register is connected to the scanning pulse.

2. A method of encoding for scanning of a free standing keyboard as claimed in claim 1, wherein: the scanning pulse and the shifting pulse are generated by a circuit consisting of an oscillator, a counter and a pulse distributor; the clock pulse output by the oscillator is sent to a counter for counting, the output of the counter is sent to the input of a pulse distributor, and the pulse distributor outputs a scanning pulse and a shifting pulse.

3. A method of encoding for scanning of a free standing keyboard as claimed in claim 1, wherein: the state code consists of an effective state code and an ineffective state code and is used for identifying the current state and the operation state of the independent keyboard; the key number is composed of a valid key number and an invalid key number; the effective state code is generated by the operation or the state of an effective keyboard, and a corresponding effective key number is correspondingly output; the invalid state code is generated by invalid keyboard operation or state and correspondingly outputs an invalid key number.

4. A method of scanning encoding of a stand-alone keyboard according to claim 3, wherein: the effective keyboard operation comprises single-key pressing operation, single-key releasing operation, single-key pressing maintaining operation and combined key operation; the combined key operation refers to the operation that after a single key is pressed down, other keys are pressed down; the invalid keyboard operation is an operation other than the valid keyboard operation.

5. A method of scanning encoding of a stand-alone keyboard according to claim 3, wherein: the key number isMThe number of bits is,Mthe value should be selected to satisfy 2^MGreater than or equal to the sum of the number of valid and invalid key numbers.