GB718696A - Improvements in and relating to electric computers - Google Patents

Improvements in and relating to electric computers

Info

Publication number
GB718696A
GB718696A GB5635/51A GB563551A GB718696A GB 718696 A GB718696 A GB 718696A GB 5635/51 A GB5635/51 A GB 5635/51A GB 563551 A GB563551 A GB 563551A GB 718696 A GB718696 A GB 718696A
Authority
GB
United Kingdom
Prior art keywords
lead
circuit
counter
reset
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5635/51A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
British Thomson Houston Co Ltd
Original Assignee
British Thomson Houston Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Thomson Houston Co Ltd filed Critical British Thomson Houston Co Ltd
Publication of GB718696A publication Critical patent/GB718696A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/82Pulse counters comprising counting chains; Frequency dividers comprising counting chains using gas-filled tubes

Landscapes

  • Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
  • Photometry And Measurement Of Optical Pulse Characteristics (AREA)

Abstract

718,696. Electronic counting-apparatus. BRITISH THOMSON-HOUSTON CO., Ltd. March 8. 1951 [March 18, 1950], No. 5635/51. Class 106 (1) An electric counter comprises a chain of binary counting units, a matrix circuit for decoding a count registered therein, a switch for selecting one of a plurality of radices, means whereby a pulse derived from a potential in the matrix circuit is operable to reset the counting units after each count to the value of the selected radix and means for indicating the state of the count. Positive input pulses are supplied via a lead 35 to pentode coincidence gates 32, 33, of which the gate 32 is normally primed (as described below) to produce corresponding negative pulses at its anode which is coupled to a lead 21 forming the input to a binary counter 3 comprising four seriesconnected hard-valve trigger pairs. Each trigger circuit. inc'udes diodes 59, 60 so as to be responsive to negative pu'ses only and may be reset to represent zero by a negative pulse on a reset lead 22 connected to one grid of each trigger pair through a diode 65. The two anodes of each trigger pair are connected via leads 10, 11 to a matrix circuit of resistors 20, having sixteen output leads, corresponding, with the numbers 0-15 respectively to which indicating neon lamps N are connected. At any time, the output lead corresponding with the number registered in the counter is at a higher potential than any other lead and the corresponding neon lamp is alight. A switch 23 is set in accordance with the selected radix, the switch arm contacting the output lead of the matrix corresponding with the number which is one less than the radix chosen. When the counter registers this number, a unidirectional buffer circuit 34 (not described) produces a positive pulse over a condenser 92 at the grid of a triode 81 associated with a second triode 82 to form a flip-flop circuit 27 which produces an inverted and delayed pulse on a lead 78. This negative pulse switches a trigger pair 29 having two stable states from its normal condition to the condition in which the output leads 30, 31 are respectively at low and high potentials. These leads are connected to the control grids of the gates 32, 33 respectively, the suppressor grids of which are supplied with the positive pulses to be counted. The gate 32 is thus closed and the gate 33 is opened to produce, in response to the next input pulse, a negative pulse at its anode which is connected to the reset lead 22. All the triggers of the counter are thus reset to represent zero. The zero output lead of the matrix circuit then produces; over a buffer circuit 26 and the condenser 92, a positive pu'se at the flip-flop circuit 27: which resets the trigger 29 to close the gate 33 and re-open the gate 32 to the next input pulse. The counter may be manually zeorized by momentary depression of a switch button 38. which removes the negative bias from the left-hand grid of each of the counter triggers and of the trigger 29. The reset lead 22 may be connected directly to the input lead 21 of a second denominational circuit having a binary counter and matrix circuit with indicating lamps only. If more than two denominations are required, additional circuits like the circuit shown are used, the reset lead 22 of each being coupled through an inverting circuit to the input lead 35 of the next higher denomination. In a modification, diode coincidence gates, Fig. 5 (not shown), replace the pentode gates 32, 33 and are so arranged as to respond to negative input pu'ses on the lead 35. Thus, inverting circuits are unnecessary when several denominational circuits are couped together. The apparatus may be used to determine the remainder of a division operation. A number of denominational units are used depending on the size of the divisor' and the several radices are selected so that their product is equal to the divisor. A number of input pulses equal to the dividend are then applied after which the numbers indicated in the different denominational circuits may be multiplied by factors appropriate to the radices chosen and added to determine the remainder.
GB5635/51A 1950-03-18 1951-03-08 Improvements in and relating to electric computers Expired GB718696A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US718696XA 1950-03-18 1950-03-18

Publications (1)

Publication Number Publication Date
GB718696A true GB718696A (en) 1954-11-17

Family

ID=22104123

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5635/51A Expired GB718696A (en) 1950-03-18 1951-03-08 Improvements in and relating to electric computers

Country Status (1)

Country Link
GB (1) GB718696A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108919974A (en) * 2016-01-05 2018-11-30 湖南工业大学 A kind of matrix keyboard state recognition and coding method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108919974A (en) * 2016-01-05 2018-11-30 湖南工业大学 A kind of matrix keyboard state recognition and coding method
CN108919974B (en) * 2016-01-05 2023-01-10 湖南工业大学 Matrix type keyboard state identification and coding method

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