CN108807279B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN108807279B CN108807279B CN201810664793.5A CN201810664793A CN108807279B CN 108807279 B CN108807279 B CN 108807279B CN 201810664793 A CN201810664793 A CN 201810664793A CN 108807279 B CN108807279 B CN 108807279B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
Abstract
The application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the following steps: step S1, forming a base with a groove, wherein the base comprises a substrate and a dielectric layer; step S2, arranging semiconductor material in the groove to form a nanowire; step S3, a structure layer is arranged on the exposed surface of the nanowire and the exposed surface of the dielectric layer, the material of the nanowire is the same as that of the structure layer, a groove is formed in the substrate, then semiconductor material is filled in the groove to form the nanowire, the material of the nanowire is the same as that of the structure layer, and therefore the nanowire is actually used as a seed layer of the structure layer, the defect of the structure layer obtained by subsequent growth is less, the quality is better, and the good performance of the semiconductor structure is further guaranteed.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
InP, as a high mobility material, can be used in the channel region of CMOS, and like its III-V compounds, for the fabrication of large scale photonic devices, InP lacks a large area substrate, and InP and Si materials do not have a cost advantage. The manufacturing process of the large-area silicon substrate is mature, and the maximum area of the silicon substrate reaches 450 mm. In the prior art, a number of articles have reported the growth of InP layers on Si substrates using a number of different methods based on lateral growth of silicon dioxide layers.
However, these methods cannot produce an InP substrate having high quality, a large area, and a low cost.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a semiconductor structure and a method for fabricating the same, so as to solve the problem that an InP substrate with good quality and a large area cannot be fabricated in the prior art.
In order to achieve the above object, according to one aspect of the present application, there is provided a method of fabricating a semiconductor structure, the method comprising: step S1, forming a base with a recess, the base including a substrate and a dielectric layer; step S2, arranging semiconductor material in the groove to form a nanowire; step S3, a structure layer is disposed on the exposed surface of the nanowire and the exposed surface of the dielectric layer, and the material of the nanowire is the same as the material of the structure layer.
Furthermore, the depth-to-width ratio of the groove is 2: 1-6: 1.
Further, the step S1 includes: providing the substrate; providing the dielectric layer on a surface of the substrate; and forming the groove in at least the dielectric layer of the substrate.
Further, before the disposing the dielectric layer, the step S1 further includes: a first buffer layer is provided on a surface of the substrate, and a maximum value of a lattice constant of a material of the first buffer layer is a1The lattice constant of the material of the substrate is a2The lattice constant of the material of the structural layer is a3And a is a2<a1<a3The dielectric layer is arranged on the surface of the first buffer layer far away from the substrate.
Further, the step S2 includes: a second buffer layer is arranged in the groove, and the maximum value of the lattice constant of the material of the second buffer layer is a4The lattice constant of the material of the substrate is a2The lattice constant of the material of the structural layer is a3，a2<a4<a3(ii) a And arranging the nanowire on the surface of the second buffer layer far away from the substrate.
Further, the first buffer layer includes a plurality of first buffer sub-layers, and the maximum lattice constant of the material of the plurality of first buffer sub-layers increases or decreases in sequence in a direction away from the substrate.
Further, the first buffer layer includes two first buffer sub-layers, which are a first buffer sub-layer and a second first buffer sub-layer sequentially stacked along a direction away from the substrate.
Further, the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structure layer is an InP layer, and the first buffer sublayer is Si(1-X)GeXAnd the second first buffer sublayer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0.
Further, the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structure layer is an InP layer, the first buffer sublayer is a relaxed Ge layer, and the second first buffer sublayer is a relaxed GeSnSi layer.
Further, the second buffer layer includes a plurality of second buffer sub-layers, and the maximum lattice constants of materials of the plurality of second buffer sub-layers sequentially increase or decrease in a direction away from the substrate.
Further, the second buffer layer includes two second buffer sub-layers, which are a first second buffer sub-layer and a second buffer sub-layer sequentially stacked along a direction away from the substrate.
Further, the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structure layer is an InP layer, and the first and second buffer sub-layers are Si layers(1-X)GeXAnd the second buffer sublayer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0.
Further, the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structure layer is an InP layer, the first and second buffer sublayers are relaxed Ge layers, and the second and second buffer sublayers are relaxed GeSnSi layers.
Further, in the step S2, the nanowire does not fill the groove, and after the nanowire is disposed, the step S2 further includes: removing part of the dielectric layer to make the nanowire protrude out of the dielectric layer.
According to another aspect of the present application, a semiconductor structure is provided, which is fabricated by any one of the above-mentioned fabrication methods.
According to yet another aspect of the present application, there is provided a semiconductor structure comprising: a base having a recess, the base comprising a substrate and a dielectric layer; the nano wire is arranged in the groove; and the structural layer is arranged on the surface of the nanowire far away from the substrate and the surface of the dielectric layer far away from the substrate, and the material of the structural layer is the same as that of the nanowire.
Further, the semiconductor structure may further include a first buffer layer and/or a second buffer layer, the first buffer layer may be disposed between the dielectric layer and the substrate, the second buffer layer may be disposed in the recess, and the nanowire may be disposed on a surface of the second buffer layer in the recess, the surface being away from the dielectric layer, a maximum value of a lattice constant of a material of the first buffer layer may be a1The maximum value of the lattice constant of the material of the second buffer layer is a4The lattice constant of the material of the substrate is a2The lattice constant of the material of the structural layer is a3，a2<a1<a3，a2<a4<a3。
Further, the first buffer layer includes a plurality of first buffer sub-layers, and/or the second buffer layer includes a plurality of second buffer sub-layers; preferably, the first buffer layer includes two first buffer sublayers, namely a first buffer sublayer and a second first buffer sublayer that are sequentially stacked along a direction away from the substrate, the second buffer layer includes a plurality of second buffer sublayers, and the second buffer layer includes two second buffer sublayers, namely a first second buffer sublayer and a second buffer sublayer that are sequentially stacked along a direction away from the substrate.
Further, the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structure layer is an InP layer, and the first buffer sublayer is Si(1-X)GeXLayer of the second one aboveOne buffer sublayer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0, or the first buffer sublayer is a relaxed Ge layer and the second first buffer sublayer is a relaxed GeSnSi layer; the first and second buffer sublayers are Si(1-X)GeXAnd the second buffer sub-layer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0, or the first second buffer sub-layer is a relaxed Ge layer and the second buffer sub-layer is a relaxed GeSnSi layer.
Furthermore, the depth-to-width ratio of the groove is 2: 1-6: 1.
By applying the technical scheme of the application, in the manufacturing method, the groove is formed in the substrate, then the semiconductor material is filled in the groove to form the nanowire, the material of the nanowire is the same as that of the structural layer, so that the nanowire is actually used as a seed layer of the structural layer, the structural layer obtained by subsequent growth has fewer defects and better quality, and the semiconductor structure is further ensured to have good performance.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 to 5 are schematic structural diagrams illustrating a process of fabricating a semiconductor structure in an embodiment of the present application; and
fig. 6 to 11 are schematic structural diagrams illustrating a manufacturing process of a semiconductor structure in another embodiment of the present application.
Wherein the figures include the following reference numerals:
10. a substrate; 11. a substrate; 12. a first buffer layer; 121. a first buffer sublayer; 122. a second first buffer sublayer; 13. a dielectric layer; 14. a groove; 20. a second buffer layer; 21. a first second buffer sublayer; 22. a second, second buffer sublayer; 30. a nanowire; 40. and (5) a structural layer.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, InP substrates with good quality and large area cannot be fabricated in the prior art, and the present application provides a semiconductor structure and a fabrication method thereof to solve the above technical problems.
In an exemplary embodiment of the present application, a method for fabricating a semiconductor structure is provided, the method comprising: step S1, forming a base with a recess, wherein the base comprises a substrate and a dielectric layer, as shown in fig. 2; step S2, disposing a semiconductor material different from the substrate material in the groove to form a nanowire, as shown in fig. 3; step S3, a structure layer is disposed on the exposed surface of the nanowire and the exposed surface of the dielectric layer, as shown in fig. 5, the material of the nanowire is the same as the material of the structure layer.
In the manufacturing method, the groove is formed in the substrate, and then the semiconductor material is selectively filled in the groove, particularly, the dielectric layer defect limiting technology is adopted during the epitaxial growth of the heterostructure, so that the defects are effectively reduced, and the quality of the material is improved. The nanowire is formed by the method, the material of the nanowire is the same as the material of the designed structural layer, and the nanowire is actually used as a seed layer of the structural layer, so that the lattice mismatch is minimum during subsequent re-epitaxial growth, the obtained structural layer has fewer defects and better quality, and the semiconductor structure is further ensured to have good performance.
It should be noted that the dielectric layer in the present application is formed of a dielectric material, which serves as an insulating spacer, and those skilled in the art can select an appropriate dielectric material to form the dielectric layer in the present application according to actual situations, for example, silicon dioxide, silicon nitride, and silicon oxynitride compounds can be selected. In particular, it may be grown in any feasible manner, more commonly by PECVD or LPCVD.
Moreover, the manufacturing method can be applied to the growth process of other semiconductor materials except silicon, and further a large-area substrate with good quality, such as an InP substrate, can be formed.
The larger the aspect ratio of the groove is, the more the generation of defects can be limited, but such a groove makes it difficult for the semiconductor material to completely fill in, so in order to make the semiconductor material in step S2 more easily disposed in the groove and at the same time further limit the growth of defects, ensuring that the number of defects in the formed seed layer is small, in one embodiment of the present application, the aspect ratio of the groove is between 2:1 and 6: 1.
Of course, the aspect ratio of the groove in the present application is not limited to the above ratio range, and a person skilled in the art can set a groove with a suitable aspect ratio according to the actual situation according to the actual process situation.
In an embodiment of the present application, the step S1 includes: providing the substrate; providing the dielectric layer on a surface of the substrate; and forming the groove in at least the dielectric layer of the substrate. The manufacturing process in the process can adopt the common process in the prior art, for example, a thermal oxidation method or a PECVD method and the like can be adopted for growing the dielectric layer on the substrate, and wet etching or dry etching can be adopted for forming the groove. The skilled person can select suitable process methods to implement the above process according to practical situations.
In order to further reduce the defects in the final grown structure layer, and to achieve better quality, in an embodiment of the present application, before disposing the dielectric layer, the step S1 further includes: a first buffer layer is provided on a surface of the substrate, and a maximum value of a lattice constant of a material of the first buffer layer is a1The lattice constant of the material of the substrate is a2The lattice constant of the material of the structural layer is a3And a is a2<a1<a3The dielectric layer is arranged on the surface of the first buffer layer far away from the substrate. The lattice constant of the buffer layer is between the lattice constant of the structural layer and the lattice constant of the substrate, so that the lattice constant can be gradually changed, the problem that defects are more due to mutation of the lattice constant is solved, the number of the defects in the structural layer is further reduced, and the quality of the structural layer is further good.
Of course, the buffer layer of the present application may not be directly disposed on the substrate, but may also be disposed in the groove, and specifically, the above step S2 includes: a second buffer layer is arranged in the groove, and the maximum value of the lattice constant of the material of the second buffer layer is a4The lattice constant of the material of the substrate is a2The lattice constant of the material of the structural layer is a3And a is a2<a4<a3(ii) a And arranging the nanowire on the surface of the second buffer layer far away from the substrate. The second buffer layer has the same function as the first buffer layer, and the lattice constant of the second buffer layer is gradually changed, so that the number of defects in the structural layer is reduced.
It should be noted that the first buffer layer and the second buffer layer may be made of the same material or different materials, and those skilled in the art may select suitable materials to form the first buffer layer and the second buffer layer according to actual situations.
In addition, it should be noted that, in the present application, the first buffer layer and the second buffer layer may be disposed at the same time, or only one buffer layer may be disposed, that is, in a specific forming process, only the first buffer layer may be disposed, only the second buffer layer may be disposed, or both the first buffer layer and the second buffer layer may be disposed, specifically, the first buffer layer is disposed on the surface of the substrate, then the dielectric layer is disposed, then the groove is formed, and then the second buffer layer is filled in the groove.
The first buffer layer in this application may be formed by one or more first buffer sublayers, and one skilled in the art may select to dispose one or more first buffer sublayers to form the first buffer layer according to practical situations, and for a specific material of the first buffer layer, one skilled in the art may select an appropriate material to form the first buffer layer according to practical situations, as long as the first buffer layer satisfies the relationship of the lattice constants described above.
In order to further reduce the number of defects in the formed structural layer, in an embodiment of the present application, the first buffer layer includes a plurality of first buffer sub-layers, and the maximum lattice constants of materials of the plurality of first buffer sub-layers sequentially increase or decrease along a direction away from the substrate. This may allow a gradual change in the lattice constant between the nanowire and the substrate, thereby reducing the number of defects in the nanowire and further reducing the number of defects in the formed structural layer.
In a specific embodiment, as shown in fig. 3 to 5, the first buffer layer includes two first buffer sub-layers, namely a first buffer sub-layer and a second first buffer sub-layer, which are sequentially stacked in a direction away from the substrate. The first buffer layer can well reduce the number of defects in the structural layer, reduce the process procedures and improve the manufacturing efficiency.
In yet another specific embodiment of the present application, the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structure layer is an InP layer, and the first buffer sublayer is Si(1-X)GeXAnd the second first buffer sublayer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0. The structure of the first buffer layer can further ensure that the number of defects in the formed InP layer is small, so that an InP substrate with large area and good quality can be formed on the silicon.
Of course, when the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, and the structure layer is an InP layer, the specific structure of the first buffer layer is not limited to the two first buffer sub-layers, and may be a first buffer sub-layer formed of other materials, and a person skilled in the art may select a suitable material to form the first buffer sub-layer according to practical situations as long as it is a semiconductor material and the lattice constant satisfies the above requirements. For example, in another specific embodiment of the present application, when the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, and the structural layer is an InP layer, the first buffer sublayer is a relaxed Ge layer, and the second first buffer sublayer is a relaxed GeSnSi layer. The two first buffer sub-layers in this embodiment may also be good at reducing the number of defects in the formed structural layer.
In yet another embodiment of the present application, the second buffer layer includes a plurality of second buffer sub-layers, and the maximum lattice constant of the material of the plurality of second buffer sub-layers sequentially increases or decreases along a direction away from the substrate. The plurality of second buffer sublayers enable the lattice constant between the nanowire and the substrate to be gradually changed, so that the quality of the formed seed layer is better, and the defect number in the formed structural layer is further ensured to be less.
The maximum lattice constants of the materials of the plurality of first buffer sublayers may sequentially increase or sequentially decrease, specifically increase or decrease, along a direction away from the substrate, depending on the magnitude relationship of the lattice constants of the substrate and the structural layer, and if the lattice constant of the substrate is larger and the lattice constant of the structural layer is smaller, the maximum lattice constants of the materials of the plurality of first buffer sublayers sequentially decrease along the direction away from the substrate, and if the lattice constant of the substrate is smaller and the lattice constant of the structural layer is larger, the maximum lattice constants of the materials of the plurality of first buffer sublayers sequentially increase along the direction away from the substrate. Likewise, this arrangement principle also applies to the arrangement of the maximum lattice constant of the material of the plurality of second buffer sublayers mentioned above.
In order to reduce the number of defects in the formed InP layer and improve the efficiency of manufacturing the semiconductor structure, thereby efficiently forming an InP substrate with a large area and good quality on silicon, in an embodiment of the present invention, as shown in fig. 7 and 8, the second buffer layer includes two second buffer sub-layers, which are a first second buffer sub-layer and a second buffer sub-layer, respectively, sequentially stacked in a direction away from the substrate.
As in the specific case of the first buffer layer, when the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, and the structure layer is an InP layer, the first and second buffer sub-layers are Si layers(1-X)GeXThe second buffer sublayer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0; or the first second buffer sublayer is a relaxed Ge layer, and the second buffer sublayer is a relaxed GeSnSi layer. The two specific structures of the second buffer layer can further ensure that the seed layer is formed and the number of defects in the structural layer is small.
Of course, the specific material of the second buffer sublayer in the second buffer layer is not limited to the above two cases, and other suitable semiconductor materials may be used as long as the lattice constant relationship can be satisfied and the lattice constant buffering function is achieved.
In another embodiment of the present application, in the step S2, the nanowire does not fill the groove, and as shown in fig. 3 or 9, after the nanowire is disposed, the step S2 further includes: removing part of the dielectric layer to make the nanowires protrude from the dielectric layer, as shown in fig. 4 and 10, the protruding material is favorable for lateral growth, so that a large-area thin film is easily formed in the subsequent process of growing the structural layer.
It should be noted that the number of the grooves formed in the substrate in the present application may be one or more, and those skilled in the art can select and form an appropriate number of grooves according to actual situations. When a plurality of grooves are arranged, the grooves are arranged at intervals, the nanowires correspond to the grooves one by one, and when the grooves are arranged, the nanowires are also arranged at intervals.
The substrate in the present application may be any material that can be used as a substrate in the prior art, and those skilled in the art can select a suitable material to form the substrate in the present application according to practical situations, for example, Si, Ge, GaAs, or GeSnSi can be selected.
The structural layer in the present application is not limited to the InP layer described above, and may be other semiconductor materials, such as other group iii-v compounds, and those skilled in the art may set appropriate materials for the structural layer according to actual circumstances.
The semiconductor structure formed by the above manufacturing method in the present application may be a substrate of a device, or may be a functional structure in a device, and may be specifically applied according to actual situations.
In another exemplary embodiment of the present application, a semiconductor structure is provided, wherein the semiconductor structure is fabricated by any one of the above-mentioned fabrication methods.
The semiconductor structure is manufactured by the manufacturing method, so that the number of defects of the structure layer is small, the quality is good, and the good performance of the semiconductor structure is guaranteed.
In yet another exemplary embodiment of the present application, there is provided a semiconductor structure, as shown in fig. 5 and 11, including: the nanowire array comprises a substrate with a groove, a nanowire and a structural layer, wherein the substrate comprises a substrate and a dielectric layer; the nano wire is arranged in the groove; the structure layer is arranged on the surface of the nanowire far away from the substrate and the surface of the dielectric layer far away from the substrate.
In the semiconductor structure, the nanowire is formed at first before the structural layer is formed, and the nanowire is used as a seed layer, so that the structural layer obtained by subsequent growth has fewer defects and better quality, and the semiconductor structure is further ensured to have good performance.
In order to further reduce the number of defects in the formed seed layer and thus the number of defects in the formed structure layer, in an embodiment of the present application, the semiconductor structure further includes a first buffer layer and/or a second buffer layer, the first buffer layer is disposed between the dielectric layer and the substrate, the second buffer layer is disposed in the recess, and the nanowire is disposed on a surface of the second buffer layer away from the dielectric layer in the recess, a maximum value of a lattice constant of a material of the first buffer layer is a1The maximum value of the lattice constant of the material of the second buffer layer is a4The lattice constant of the material of the substrate is a2The lattice constant of the material of the structural layer is a3，a2<a1<a3，a2<a4<a3。
In another embodiment of the present application, the first buffer layer includes a plurality of first buffer sub-layers, and/or the second buffer layer includes a plurality of second buffer sub-layers, so that the number of defects in the formed structural layer can be further reduced.
In order to ensure that the number of defects in the formed InP layer is small, reduce the process, and improve the manufacturing efficiency of the semiconductor structure, so as to efficiently form an InP substrate with a large area and good quality on silicon, in an embodiment of the present invention, as shown in fig. 5, the first buffer layer includes two first buffer sublayers, which are a first buffer sublayer and a second first buffer sublayer sequentially stacked along a direction away from the substrate, respectively, as shown in fig. 11, the second buffer layer includes a plurality of second buffer sublayers, which include two second buffer sublayers, which are a first second buffer sublayer and a second buffer sublayer sequentially stacked along a direction away from the substrate, respectively.
In yet another embodiment of the present application, the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structure layer is an InP layer, and the first layer is a first dielectric layerThe buffer sublayer is Si(1-X)GeXThe second first buffer sublayer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0, or the first buffer sublayer is a relaxed Ge layer and the second first buffer sublayer is a relaxed GeSnSi layer; the structure of the first buffer layer can further ensure that the number of defects in the formed InP layer is small, so that an InP matrix with large area and good quality can be formed on the silicon.
The first and second buffer sublayers are Si(1-X)GeXAnd the second buffer sub-layer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0, or the first second buffer sub-layer is a relaxed Ge layer and the second buffer sub-layer is a relaxed GeSnSi layer. The structure of the second buffer layer can further ensure that the number of defects in the formed InP layer is small, so that an InP matrix with large area and good quality can be formed on the silicon.
The larger the aspect ratio of the groove in the substrate is, the more the generation of defects can be limited, but such a groove makes the semiconductor material not easy to fill in, so in order to make the semiconductor material in step S2 more easily disposed in the groove and at the same time further limit the growth of defects, and ensure that the number of defects in the formed seed layer is small, in an embodiment of the present application, the aspect ratio of the groove is between 2:1 and 6: 1.
In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the technical solutions and technical effects of the present application will be described below with reference to specific embodiments.
Example 1
The manufacturing process of the semiconductor structure comprises the following steps:
providing a substrate 11, and disposing a dielectric layer 13, specifically a silicon dioxide layer, on a surface of the substrate to form the structure shown in fig. 1; a plurality of spaced grooves 14 are formed in the silicon dioxide layer and a part of the substrate 11 to form the structure shown in FIG. 2, and the depth-to-width ratio of the grooves 14 is 2: 1-6: 1.
In each of the above-mentioned recesses 14 there is arranged in succession a first second buffer sub-layer 21 and a second buffer sub-layer 22,as shown in fig. 3, wherein the first and second buffer sublayers are Si(1-X)GeXAnd the second buffer sublayer is a GaAs layer, wherein X is increased from 0 to 1 in sequence.
InP is provided in each groove and does not fill the grooves 14, forming a plurality of nanowires 30, as shown in figure 3.
A portion of the silicon dioxide layer is removed so that the nanowires 30 protrude from the silicon dioxide layer, as shown in fig. 4.
InP is provided on the exposed surface of the nanowire 30 and the exposed surface of the silicon dioxide layer to form a structural layer 40, as shown in fig. 5.
Example 2
The manufacturing process of the semiconductor structure comprises the following steps:
providing the substrate 11, and sequentially disposing a first buffer sublayer 121 and a second first buffer sublayer 122 on a surface of the substrate, as shown in fig. 6, wherein the first buffer sublayer 121 is Si(1-X)GeXA second first buffer sublayer 122, which is a GaAs layer, wherein X is sequentially increased from 0 to 1
A dielectric layer 13, specifically a silicon dioxide layer, is disposed on a surface of the second first buffer sublayer 122 away from the first buffer sublayer 121, resulting in the structure shown in fig. 7.
A plurality of spaced grooves 14 are formed in the silicon dioxide layer and a portion of the second first buffer sublayer 122 to form the structure shown in FIG. 8, wherein the aspect ratio of the grooves is 2:1 to 6: 1.
InP is provided in each groove 14 and does not fill the groove 14, forming a plurality of nanowires 30, as shown in fig. 9.
A portion of the silicon dioxide layer is removed so that the nanowires 30 protrude from the silicon dioxide layer, as shown in fig. 10.
InP is provided on the exposed surface of the nanowire 30 and the exposed surface of the silicon dioxide layer to form a structural layer 40, as shown in fig. 11.
Example 3
The manufacturing process of the semiconductor structure comprises the following steps:
providing the substrate, and sequentially disposing a first buffer sub-layer and a second first buffer sub-layer on a surface of the substrate, as shown in fig. 6, where the first second buffer sub-layer is a relaxed Ge layer, and the second buffer sub-layer is a GeSnSi layer.
A silicon dioxide layer is provided on the surface of the second first buffer sub-layer remote from the first buffer sub-layer, resulting in the structure shown in fig. 7.
And forming a plurality of spaced grooves in the silicon dioxide layer and part of the second first buffer sublayer to form the structure shown in fig. 8, wherein the depth-to-width ratio of the grooves is 2: 1-6: 1.
InP is provided in each groove and does not fill the grooves 14, forming a plurality of nanowires 30, as shown in figure 9.
A portion of the silicon dioxide layer is removed so that the nanowires 30 protrude from the silicon dioxide layer, as shown in fig. 10.
InP is provided on the exposed surface of the nanowire 30 and the exposed surface of the silicon dioxide layer to form a structural layer 40, as shown in fig. 11.
In the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) in the manufacturing method, the groove is formed in the substrate, then the semiconductor material is filled in the groove to form the nanowire, the material of the nanowire is the same as that of the structural layer, and therefore the nanowire is actually used as a seed layer of the structural layer, so that the structural layer obtained by subsequent growth has fewer defects and better quality, and the semiconductor structure is further ensured to have good performance.
2) The semiconductor structure is manufactured by the manufacturing method, so that the number of defects of the structure layer is small, the quality is good, and the good performance of the semiconductor structure is guaranteed.
3) According to the semiconductor structure, the nanowire is formed at first before the structural layer is formed, and the nanowire is used as the seed layer, so that the structural layer obtained by subsequent growth has fewer defects and better quality, and the semiconductor structure is further ensured to have good performance.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (19)
1. A method for fabricating a semiconductor structure, the method comprising:
step S1, forming a base with a groove, wherein the base comprises a substrate and a dielectric layer;
step S2, arranging semiconductor material in the groove to form a nanowire; and
step S3, a structure layer is arranged on the exposed surface of the nanowire and the exposed surface of the dielectric layer, the material of the nanowire is the same as that of the structure layer,
before the disposing the dielectric layer, the step S1 further includes:
providing a first buffer layer on a surface of the substrate, the first buffer layer having a material with a maximum lattice constant of a1The lattice constant of the material of the substrate is a2The lattice constant of the material of the structural layer is a3And a is a2<a1<a3，
The dielectric layer is arranged on the surface of the first buffer layer far away from the substrate.
2. The manufacturing method of claim 1, wherein the depth-to-width ratio of the groove is between 2:1 and 6: 1.
3. The method of manufacturing according to claim 1, wherein the step S1 includes:
providing the substrate;
disposing the dielectric layer on a surface of the substrate; and
forming the recess in at least the dielectric layer of the substrate.
4. The method of manufacturing according to claim 1, wherein the step S2 includes:
a second buffer layer is arranged in the groove, and the maximum value of the lattice constant of the material of the second buffer layer is a4The lattice constant of the material of the substrate is a2The lattice constant of the material of the structural layer is a3，a2<a4<a3(ii) a And
the nanowires are arranged on the surface of the second buffer layer far away from the substrate.
5. The method of claim 1, wherein the first buffer layer comprises a plurality of first buffer sub-layers, and wherein a maximum lattice constant of materials of the plurality of first buffer sub-layers sequentially increases or decreases in a direction away from the substrate.
6. A method according to claim 1, wherein the first buffer layer comprises two first buffer sub-layers, namely a first buffer sub-layer and a second first buffer sub-layer, which are sequentially stacked in a direction away from the substrate.
7. The method as claimed in claim 6, wherein the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structure layer is an InP layer, and the first buffer sub-layer is Si(1-X)GeXAnd the second first buffer sublayer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0.
8. The method of claim 6, wherein the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structural layer is an InP layer, the first buffer sublayer is a relaxed Ge layer, and the second first buffer sublayer is a relaxed GeSnSi layer.
9. The method of claim 4, wherein the second buffer layer comprises a plurality of second buffer sub-layers, and the maximum lattice constant of the material of the plurality of second buffer sub-layers increases or decreases sequentially along a direction away from the substrate.
10. A manufacturing method according to claim 4, wherein the second buffer layer comprises two second buffer sub-layers, namely a first second buffer sub-layer and a second buffer sub-layer which are sequentially stacked in a direction away from the substrate.
11. The method of claim 10, wherein the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structural layer is an InP layer, and the first and second buffer sublayers are Si(1-X)GeXAnd the second buffer sublayer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0.
12. The method of claim 10, wherein the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structural layer is an InP layer, the first second buffer sublayer is a relaxed Ge layer, and the second buffer sublayer is a relaxed GeSnSi layer.
13. The method as claimed in claim 1, wherein the step S2 is performed by the nanowire not filling the groove, and after disposing the nanowire, the step S2 further comprises:
and removing part of the dielectric layer so that the nanowire protrudes out of the dielectric layer.
14. A semiconductor structure, wherein the semiconductor structure is manufactured by the manufacturing method of any one of claims 1 to 13.
15. A semiconductor structure, comprising:
a base with a recess, the base comprising a substrate and a dielectric layer;
a nanowire disposed in the groove; and
a structural layer disposed on a surface of the nanowire remote from the base and on a surface of the dielectric layer remote from the substrate, the structural layer being of a same material as the nanowire,
the semiconductor structure further comprises a first buffer layer and/or a second buffer layer, the first buffer layer is arranged between the dielectric layer and the substrate, the second buffer layer is arranged in the groove, the nanowire is arranged on the surface, far away from the dielectric layer, of the second buffer layer in the groove, and the maximum value of the lattice constant of the material of the first buffer layer is a1The maximum value of the lattice constant of the material of the second buffer layer is a4The lattice constant of the material of the substrate is a2The lattice constant of the material of the structural layer is a3，a2<a1<a3，a2<a4<a3。
16. The semiconductor structure of claim 15, wherein the first buffer layer comprises a plurality of first buffer sub-layers, and/or the second buffer layer comprises a plurality of second buffer sub-layers.
17. The semiconductor structure of claim 15, wherein the first buffer layer comprises two first buffer sub-layers, namely a first buffer sub-layer and a second first buffer sub-layer, which are sequentially stacked in a direction away from the substrate, and the second buffer layer comprises two second buffer sub-layers, namely a first second buffer sub-layer and a second buffer sub-layer, which are sequentially stacked in a direction away from the substrate.
18. The semiconductor structure of claim 16 or 17, wherein the substrate is a Si layer, the dielectric layer is a silicon dioxide layer, the structural layer is an InP layer,
the first buffer sublayer is Si(1-X)GeXThe second first buffer sublayer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0, or the first buffer sublayer is a relaxed Ge layer and the second first buffer sublayer is a relaxed GeSnSi layer;
the first and second buffer sublayers are Si(1-X)GeXAnd the second buffer sublayer is a GaAs layer, wherein X is more than or equal to 0 and less than or equal to 1.0, or the first second buffer sublayer is a relaxed Ge layer and the second buffer sublayer is a relaxed GeSnSi layer.
19. The semiconductor structure of claim 15, wherein an aspect ratio of the recess is between 2:1 and 6: 1.
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| CN1853260A (en) * | 2003-10-02 | 2006-10-25 | 飞思卡尔半导体公司 | Semiconductor structure with different lattice constant materials and method for forming the same |
| CN101685774A (en) * | 2008-09-24 | 2010-03-31 | 北京邮电大学 | Heteroepitaxial growth process based on interface nano-structure |
| CN103280425A (en) * | 2013-05-27 | 2013-09-04 | 中国科学院物理研究所 | Composite substrate with isolating layer and manufacturing method of composite substrate |
| CN104126228A (en) * | 2011-12-23 | 2014-10-29 | 英特尔公司 | Non-planar gate all-around device and method of fabrication thereof |
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| CN1853260A (en) * | 2003-10-02 | 2006-10-25 | 飞思卡尔半导体公司 | Semiconductor structure with different lattice constant materials and method for forming the same |
| CN101685774A (en) * | 2008-09-24 | 2010-03-31 | 北京邮电大学 | Heteroepitaxial growth process based on interface nano-structure |
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