CN213585703U - CMOS oscillator - Google Patents

Abstract

The utility model relates to an oscillator technical field discloses a lower and comparatively accurate CMOS oscillator of output reference signal of consumption, possesses: at least one inverter configured in the CMOS oscillator for receiving a control signal input by a peripheral circuit and inverting the phase of the control signal by 180 degrees; at least one nand gate, having an input end coupled to the output end of the inverter, for receiving the control signal after 180 degrees of phase reversal; and the input end of the at least one NOT gate is connected with the output end of the NAND gate, and the input control signal is processed by the NOT gate to obtain a quadrature clock signal at the output end of the NOT gate and output a differential signal.

Description

CMOS oscillator

Technical Field

The utility model relates to an oscillator technical field, more specifically say, relate to a CMOS oscillator.

Background

The crystal oscillator is a resonance device made by using the piezoelectric effect of quartz crystal, and is widely applied to various oscillation circuits of color TV, computers, remote controllers and the like, and is used for a frequency generator in a communication system, generating clock signals for data processing equipment and providing reference signals for a specific system. At present, when an integrated circuit works, the start-up time of an oscillator is expected to be short, and the oscillator can enter a stable oscillation state quickly, however, a traditional oscillator is provided with a large bias current for achieving quick oscillation starting, the power consumption of the oscillator is increased due to the large bias current, and the error of a reference signal output by the integrated circuit is large.

Therefore, how to reduce the power consumption of the oscillator becomes a technical problem that needs to be solved by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model lies in, set up great bias current to the above-mentioned traditional oscillator of prior art in order to reach quick start oscillation, great bias current can make the consumption grow of oscillator, leads to the great defect of reference signal's of integrated circuit output error, provides a lower and comparatively accurate CMOS oscillator of output reference signal of consumption.

The utility model provides a technical scheme that its technical problem adopted is: a CMOS oscillator is configured, and the CMOS oscillator includes:

at least one inverter configured in the CMOS oscillator for receiving a control signal input by a peripheral circuit and inverting the phase of the control signal by 180 degrees;

at least one nand gate, having an input end coupled to the output end of the inverter, for receiving the control signal after 180 degrees of phase reversal;

and the input end of the at least one NOT gate is connected with the output end of the NAND gate, and the input control signal is processed by the NOT gate to obtain a quadrature clock signal at the output end of the NOT gate and output a differential signal.

In some embodiments, the inverter comprises a first inverter and a second inverter,

the signal input end of the first inverter is connected with the output end of the peripheral circuit and is used for receiving a control signal input by the peripheral circuit and outputting the control signal to the NAND gate;

and the signal input end of the second inverter is connected with the output end of the peripheral circuit and is used for receiving another control signal input by the peripheral circuit and outputting the control signal to another NAND gate.

In some embodiments, the NAND gates include a first NAND gate and a second NAND gate,

a signal input end of the first nand gate is connected to a signal output end of the first inverter, and is configured to receive the control signal input by the first inverter and output the control signal to the nor gate;

a signal input end of the second nand gate is connected to the signal output end of the second inverter, and is configured to receive the control signal input by the second inverter and output the control signal to the other not gate; wherein the content of the first and second substances,

the other signal input end of the first NAND gate is connected with the signal output end of the second NAND gate,

and the other signal input end of the second NAND gate is connected with the signal output end of the first NAND gate.

In some embodiments, the NOT gates include a first NOT gate and a second NOT gate,

the signal input end of the first NOT gate is coupled to the signal output end of the first NAND gate;

the signal input end of the second not gate is coupled to the signal output end of the second not gate.

In some embodiments, the device further comprises a first capacitor and a second capacitor,

one end of the first capacitor is connected with the output end of the first phase inverter, and the other end of the first capacitor is connected with a common end;

one end of the second capacitor is connected with the output end of the second phase inverter, and the other end of the second capacitor is connected with the common end.

Among the CMOS oscillator, including at least one phase inverter, at least one NAND gate and at least one NOT gate, wherein, the phase inverter is used for receiving the control signal of peripheral circuit input to 180 degrees with this control signal's phase reversal, this control signal obtains a quadrature clock signal at the output of NOT gate after NOT gate handles, and output a difference signal. Compared with the prior art, the CMOS oscillator can conveniently obtain the quadrature clock by adopting the four-stage delay unit, and generates the differential signal by each stage of delay unit, thereby effectively reducing the static power consumption and having better anti-noise capability, and further solving the problem that the error of the reference signal output by the integrated circuit is larger because the power consumption of the oscillator is increased by larger bias current.

Drawings

The invention will be further explained with reference to the drawings and examples, wherein:

fig. 1 is a schematic circuit diagram of an embodiment of a CMOS oscillator according to the present invention.

Detailed Description

In order to clearly understand the technical features, objects, and effects of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in fig. 1, in a first embodiment of the CMOS oscillator of the present invention, the CMOS oscillator 100 includes at least one inverter (101, 102), at least one nand gate (IC1A, IC1C), and at least one not gate (IC1B, IC 1D).

The phase inversion circuit (101, 102) can invert the phase of an input signal by 180 degrees, the circuit is mainly applied to analog circuits (such as audio amplification and clock oscillators), and the phase inversion circuit (101, 102) is formed by connecting two enhancement type MOS field effect transistors.

Specifically, the inverters (101, 102) are disposed in the CMOS oscillator, and are configured to receive a control signal input from the peripheral circuit, invert the phase of the control signal by 180 degrees, and output the control signal to the nand gate (IC1A, IC 1C).

Nand gates (IC1A, IC1C) are a stack of and not gates, having multiple inputs and one output.

When the input is all high level (1), the output is low level (0);

when at least one of the inputs is low (0), the output is high (1).

Specifically, one input end of the nand gate (IC1A, IC1C) is correspondingly connected with the output end of the inverter (101, 102), and is used for receiving the control signal after 180 degrees of phase inversion and then outputting the control signal to the not gate (IC1B, IC 1D).

The not-gate (IC1B, IC1D) has an input and an output.

When the input end of the circuit is at high level (logic 1), the output end is at low level (logic 0);

when the input terminal is at low level, the output terminal is at high level.

Specifically, the inputs of the not gates (IC1B, IC1D) are coupled to the outputs of the nand gates (IC1A, IC1C), and the input control signals (IC1B, IC1D) are subjected to the not gate processing, so as to obtain a quadrature clock signal at the outputs of the not gates (IC1B, IC1D), and output a differential signal.

Particularly, the CMOS oscillator can conveniently obtain a quadrature clock by adopting four stages of delay units, and generates a differential signal through each stage of delay unit, so that static power consumption can be effectively reduced, better noise resistance is achieved, and the problem that the error of a reference signal output by an integrated circuit is larger due to the fact that the power consumption of the oscillator is increased by larger bias current is solved.

In some embodiments, in order to improve the accuracy of the output control signal, the first inverter 101 and the second inverter 102 may be disposed in an inverter.

Specifically, the signal input terminal of the first inverter 101 is connected to the output terminal of the peripheral circuit, and is configured to receive a control signal (corresponding to IN1) input by the peripheral circuit and output the control signal to a nand gate (corresponding to IC 1A);

the signal input terminal of the second inverter 102 is connected to the output terminal of the peripheral circuit, and is configured to receive another control signal (corresponding to IN2) input by the peripheral circuit and output the control signal to another nand gate (corresponding to IC 1C).

The first inverter 101 includes a first fet M101, a second fet M102, and a third fet M103.

The gates of the first fet M101 and the third fet M103 are connected to the input terminal of the peripheral circuit, and are configured to receive a control signal (corresponding to IN1) and reverse the phase of the control signal (corresponding to IN1) by 180 degrees.

The second inverter 102 includes a fourth fet M104, a fifth fet M105, and a sixth fet M106.

The gates of the fourth fet M104 and the sixth fet M106 are connected to the input of the peripheral circuit, and are configured to receive another control signal (corresponding to IN2) and reverse the phase of the another control signal (corresponding to IN2) by 180 degrees.

In some embodiments, in order to improve the processing performance of the control signal, a first nand gate IC1A and a second nand gate IC1C may be disposed in the nand gate.

Specifically, a signal input terminal (corresponding to pin 2) of the first nand gate IC1A is connected to the signal output terminal of the first inverter 101, and is configured to receive the control signal (corresponding to IN1) input by the first inverter 101 and output the control signal (corresponding to IN1) to a not gate (corresponding to IC 1C);

a signal input terminal (corresponding to pin 8) of the second nand gate IC1C is connected to the signal output terminal of the second inverter 102, and is configured to receive the control signal (corresponding to IN2) input by the second inverter 102 and output the control signal (corresponding to IN2) to another not gate (corresponding to IC 1D).

The other signal input end (corresponding to pin 3) of the first nand gate IC1A is connected to the signal output end (corresponding to pin 10) of the second nand gate IC1C, and the other signal input end (corresponding to pin 7) of the second nand gate IC1C is connected to the signal output end (corresponding to pin 4) of the first nand gate IC 1A.

In some embodiments, in order to improve the accuracy of outputting the differential signal, the first not gate IC1B and the second not gate IC1D may be disposed in the not gate.

Specifically, a signal input terminal (corresponding to pin 5) of the first not gate IC1B is coupled to a signal output terminal (corresponding to pin 4) of the first nand gate IC 1A;

the signal input terminal (corresponding to pin 11) of the second not-gate IC1D is coupled to the signal output terminal (corresponding to pin 10) of the second nand-gate IC 1C.

In some embodiments, the inverter further includes a first capacitor C101 and a second capacitor C102, wherein one end of the first capacitor C101 is connected to the output end of the first inverter 101, and the other end of the first capacitor C101 is connected to the common end; one end of the second capacitor C102 is connected to the output end of the second inverter 102, and the other end of the second capacitor C102 is connected to the common terminal.

The specific working principle is as follows: the first fet M101 and the fourth fet M104 supply currents when the first capacitor C101 and the second capacitor C102 are charged, respectively.

The second field effect transistor M102 and the fifth field effect transistor M105 are used as current sources to provide current when the capacitor discharges, and the current magnitude changes along with the control voltage Vg, so that the discharge speed of the capacitor is adjusted. In addition, the MOS gate oxide capacitors made of the NMOS tubes with grounded source-drain ends by the first capacitor C101 and the second capacitor C102 have high capacitance per unit area and good precision.

In order to avoid that the control tube enters the linear region during the capacitive discharge process with the increase of the control current, which leads to the reduction of the linear coverage frequency range of the CMOS oscillator, the value of Venable should be as large as possible. However, if the turning point Venable is too high, the discharge time of the capacitor is shortened, and when Venable is close to Vdd, the delay time of the three-input NAND gate and the inverter is not negligible any more, and the frequency adjustment range of the CMOS oscillator is greatly reduced.

While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many modifications may be made by one skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims (5)

1. A CMOS oscillator is characterized by comprising:

at least one inverter configured in the CMOS oscillator for receiving a control signal input by a peripheral circuit and inverting the phase of the control signal by 180 degrees;

at least one nand gate, having an input end coupled to the output end of the inverter, for receiving the control signal after 180 degrees of phase reversal;

and the input end of the at least one NOT gate is connected with the output end of the NAND gate, and the input control signal is processed by the NOT gate to obtain a quadrature clock signal at the output end of the NOT gate and output a differential signal.

2. The CMOS oscillator of claim 1,

the inverter includes a first inverter and a second inverter,

the signal input end of the first inverter is connected with the output end of the peripheral circuit and is used for receiving a control signal input by the peripheral circuit and outputting the control signal to the NAND gate;

and the signal input end of the second inverter is connected with the output end of the peripheral circuit and is used for receiving another control signal input by the peripheral circuit and outputting the control signal to another NAND gate.

3. The CMOS oscillator of claim 2,

the nand gates include a first nand gate and a second nand gate,

a signal input end of the first nand gate is connected to a signal output end of the first inverter, and is configured to receive the control signal input by the first inverter and output the control signal to the nor gate;

a signal input end of the second nand gate is connected to the signal output end of the second inverter, and is configured to receive the control signal input by the second inverter and output the control signal to the other not gate; wherein the content of the first and second substances,

the other signal input end of the first NAND gate is connected with the signal output end of the second NAND gate,

and the other signal input end of the second NAND gate is connected with the signal output end of the first NAND gate.

4. The CMOS oscillator of claim 3,

the NOT gates include a first NOT gate and a second NOT gate,

the signal input end of the first NOT gate is coupled to the signal output end of the first NAND gate;

the signal input end of the second not gate is coupled to the signal output end of the second not gate.

5. The CMOS oscillator of any one of claims 2 to 4,

also includes a first capacitor and a second capacitor,

one end of the first capacitor is connected with the output end of the first phase inverter, and the other end of the first capacitor is connected with a common end;

one end of the second capacitor is connected with the output end of the second phase inverter, and the other end of the second capacitor is connected with the common end.

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