CN108768351B - Low-offset low-power-consumption high-speed dynamic comparator under low power supply voltage - Google Patents

Low-offset low-power-consumption high-speed dynamic comparator under low power supply voltage Download PDF

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CN108768351B
CN108768351B CN201810541865.7A CN201810541865A CN108768351B CN 108768351 B CN108768351 B CN 108768351B CN 201810541865 A CN201810541865 A CN 201810541865A CN 108768351 B CN108768351 B CN 108768351B
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nmos transistor
transistor
pmos transistor
electrode
output signal
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CN108768351A (en
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张春茗
曹源
杜慧敏
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Xian University of Posts and Telecommunications
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Xian University of Posts and Telecommunications
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage

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  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses a high-speed dynamic comparator with low offset and low power consumption under low power supply voltage, which comprises: the first-stage pre-amplifying circuit receives the in-phase input signal, the reverse-phase input signal, the first voltage bias signal and the second voltage bias signal and outputs a first in-phase output signal and a first reverse-phase output signal; the second-stage pre-amplifying circuit receives the first in-phase output signal, the first anti-phase output signal and the clock control signal and outputs a second in-phase output signal and a second anti-phase output signal; the CMOS latch circuit receives the second in-phase output signal, the second reverse-phase output signal and the clock control signal and outputs a third in-phase output signal and a third reverse-phase output signal; and the SR trigger circuit receives the third in-phase output signal and the third reverse-phase output signal and outputs the in-phase output signal and the reverse-phase output signal. The invention relates to a high-speed dynamic comparator realized under 1.05V, which improves the speed of a clock control signal, so that the comparator still has the advantages of good low offset voltage and low power consumption at high frequency.

Description

Low-offset low-power-consumption high-speed dynamic comparator under low power supply voltage
Technical Field
The invention belongs to the technical field of comparators in analog-to-digital converters, and particularly relates to a dynamic comparator under low power supply voltage.
Background
Due to the rapid development of semiconductor industry and integrated circuit technology, analog-to-digital converters have become the key to the development of electronic technology. The comparator is used as a core part in the analog-to-digital converter circuit, and various performance characteristics of the comparator have important influence on the performance of the whole analog-to-digital converter. At present, with the development of integrated circuit technology, the power supply voltage provided for the circuit is gradually reduced, which brings certain difficulty to the design of the traditional dynamic comparator; moreover, how to ensure various performance indexes of the comparator circuit under low power supply voltage, such as offset voltage, transmission delay, power consumption, etc., becomes a problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a high-speed dynamic comparator under low power supply voltage, which can still improve various performance indexes of a comparator circuit under higher working frequency, thereby realizing high-speed application of an analog-digital converter circuit.
In order to achieve the purpose, the invention adopts the following technical scheme:
a high-speed dynamic comparator with low offset and low power consumption under low power supply voltage comprises a bias circuit, a first-stage pre-amplification circuit, a second-stage pre-amplification circuit, a CMOS latch circuit and an SR trigger circuit which are connected in sequence;
the bias circuit receives the current source signal and outputs a first voltage bias signal and a second voltage bias signal;
the first-stage pre-amplification circuit receives the in-phase input signal, the reverse-phase input signal, the first voltage bias signal and the second voltage bias signal and outputs a first in-phase output signal and a first reverse-phase output signal;
the second-stage pre-amplifying circuit receives the first in-phase output signal, the first anti-phase output signal and the clock control signal and outputs a second in-phase output signal and a second anti-phase output signal;
the CMOS latch circuit receives the second in-phase output signal, the second reverse-phase output signal and the clock control signal and outputs a third in-phase output signal and a third reverse-phase output signal;
and the SR flip-flop circuit receives the third in-phase output signal and the third reverse-phase output signal and outputs the in-phase output signal and the reverse-phase output signal.
Further, the bias circuit includes a first NMOS transistor and a second NMOS transistor, wherein,
the source electrode of the first NMOS transistor is grounded;
the grid electrode of the first NMOS transistor is connected with the drain electrode of the first NMOS transistor and is connected with the source electrode of the second NMOS transistor;
the grid electrode of the second NMOS transistor is connected with the drain electrode and is connected with a current source signal;
the grid electrode of the first NMOS transistor outputs a first voltage bias signal;
the gate of the second NMOS transistor outputs a second voltage bias signal.
Further, the first stage of pre-amplifying circuit includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, wherein,
a gate of the third NMOS transistor receives a first bias voltage signal;
the source of the third NMOS transistor is grounded;
the drain electrode of the third NMOS transistor, the source electrode of the fourth NMOS transistor and the source electrode of the fifth NMOS transistor are connected;
a gate of the fourth NMOS transistor receives an in-phase input signal;
a grid electrode of the fifth NMOS transistor receives an inverted input signal;
the drain electrode of the fourth NMOS transistor is connected with the source electrode of the sixth NMOS transistor;
the drain electrode of the fifth NMOS transistor and the source electrode of the seventh NMOS transistor are connected;
the grid electrode of the sixth NMOS transistor and the grid electrode of the seventh NMOS transistor are connected with a second voltage bias signal;
the drain electrode of the sixth NMOS transistor, the drain electrode of the first PMOS transistor and the drain electrode of the third PMOS transistor are connected;
the drain electrode of the seventh NMOS transistor, the drain electrode of the second PMOS transistor and the drain electrode of the fourth PMOS transistor are connected;
the drain electrode of the first PMOS transistor, the grid electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor are connected;
the grid electrode of the third PMOS transistor, the drain electrode of the fourth PMOS transistor and the grid electrode of the fourth PMOS transistor are connected;
the source electrode of the first PMOS transistor, the source electrode of the second PMOS transistor, the source electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected with a power supply voltage;
the drain electrode of the sixth NMOS transistor outputs a first in-phase output signal;
a drain of the seventh NMOS transistor outputs a first inverted output signal.
Further, the second stage pre-amplifying circuit includes: an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor, wherein,
a gate of the eighth NMOS transistor, a gate of the eleventh NMOS transistor, and a gate of the twelfth NMOS transistor receive a clock control signal;
the drain electrode of the eighth NMOS transistor, the source electrode of the ninth NMOS transistor and the source electrode of the tenth NMOS transistor are connected;
a gate of the ninth NMOS transistor receives a first inverted output signal;
a gate of the tenth NMOS transistor receives a first non-inverting output signal;
the drain electrode of the ninth NMOS transistor and the source electrode of the eleventh NMOS transistor are connected;
the drain electrode of the tenth NMOS transistor is connected with the source electrode of the twelfth NMOS transistor;
the source electrode of the eighth NMOS transistor is connected with the ground;
a drain of the eleventh NMOS transistor outputs a second inverted output signal;
the drain of the twelfth NMOS transistor outputs a second in-phase output signal.
Further, the CMOS latch circuit includes: a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor, wherein,
the nineteenth NMOS transistor and the tenth PMOS transistor form a first inverter, and the output of the inverter is connected with a third in-phase output signal;
the eighteenth NMOS transistor and the ninth PMOS transistor form a second inverter, and the output of the inverter is connected with a third inverted output signal;
the source electrode of the thirteenth NMOS transistor, the source electrode of the fourteenth NMOS transistor, the source electrode of the fifteenth NMOS transistor and the source electrode of the sixteenth NMOS transistor are connected with the ground;
the grid electrode of the thirteenth NMOS transistor, the grid electrode of the sixteenth NMOS transistor, the grid electrode of the fifteenth NMOS transistor, the grid electrode of the sixth PMOS transistor and the grid electrode of the seventeenth NMOS transistor are connected with a clock control signal;
the drain electrode of the thirteenth NMOS transistor, the drain electrode of the fourteenth NMOS transistor, the gate electrode of the fifteenth NMOS transistor, the drain electrode of the fifth PMOS transistor and the input of the second inverter are connected;
a drain of the sixteenth NMOS transistor, a drain of the fifteenth NMOS transistor, a gate of the fourteenth NMOS transistor, a drain of the sixth PMOS transistor, and an input of the first inverter are connected;
a source electrode of the fifth PMOS transistor, a source electrode of the seventeenth NMOS transistor, a drain electrode of the seventh PMOS transistor, and a gate electrode of the eighth PMOS transistor receive a second inverted output signal;
a source of the sixth PMOS transistor, a drain of the seventeenth NMOS transistor, a gate of the seventh PMOS transistor, and a drain of the eighth PMOS transistor receive a second in-phase output signal;
a source of the seventh PMOS transistor and a source of the eighth PMOS transistor are connected to a supply voltage.
Further, the SR flip-flop circuit includes: a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, and a fourteenth PMOS transistor, wherein,
the source electrode of the twentieth NMOS transistor and the source electrode of the twenty-first NMOS transistor are connected with the ground;
a gate of the twentieth NMOS transistor and a gate of the eleventh PMOS transistor receive a third in-phase output signal;
the grid electrode of the twenty-first NMOS transistor and the grid electrode of the fourteenth PMOS transistor receive a third inverted output signal;
the drain electrode of the twenty-second NMOS transistor is connected with the source electrode of the twenty-second NMOS transistor;
the drain electrode of the twenty-first NMOS transistor is connected with the source electrode of the twenty-third NMOS transistor;
the drain electrode of the twenty-third NMOS transistor, the drain electrode of the thirteenth PMOS transistor, the drain electrode of the fourteenth PMOS transistor, the gate electrode of the twelfth PMOS transistor and the gate electrode of the twenty-second NMOS transistor are connected and output in-phase output signals;
the drain electrode of the twenty-second NMOS transistor, the drain electrode of the eleventh PMOS transistor, the drain electrode of the twelfth PMOS transistor, the gate electrode of the thirteenth PMOS transistor and the gate electrode of the twenty-third NMOS transistor are connected and output an inverted output signal;
a source of the eleventh PMOS transistor, a source of the twelfth PMOS transistor, a source of the thirteenth PMOS transistor, and a source of the fourteenth PMOS transistor are connected to a supply voltage.
Further, the body of all NMOS transistors in the circuit are connected to ground, and the body of all PMOS transistors in the circuit are connected to the supply voltage.
Further, the high-speed dynamic comparator respectively passes through a reset stage of the comparator and a regeneration stage of the comparator under the control of a clock control signal clk, so as to complete one-time data comparison; controlling a tail current tube in the second-stage pre-amplifying circuit by a clock control signal; when the comparator is in a regeneration stage, the tail current tube is cut off, so that one path of current bias is reduced, and the static power consumption of the circuit is reduced.
Further, the comparator circuit undergoes two phases of reset and regeneration under the control of the clock control signal; when the circuit is in the reset phase:
firstly, a seventeenth NMOS transistor enters a conducting state, so that an input signal of the CMOS latch circuit is adjusted to be in a balanced state;
secondly, the fifth PMOS transistor and the sixth PMOS transistor enter a turn-off state, so that no direct current path exists between the input end and the ground wire of the CMOS latch circuit in the reset stage;
third, the thirteenth NMOS transistor and the sixteenth NMOS transistor are brought into a conducting state, thereby forcibly pulling the voltages at the drain a of the fifth PMOS transistor and the drain b of the sixth PMOS transistor to a low level.
Further, the low power voltage means a voltage of 1.05V.
Compared with the prior art, the invention has the following beneficial effects:
in the invention, under the condition of constant tail current and threshold voltage, a larger voltage margin is obtained by adjusting the width-to-length ratio of the tube, thereby solving the design difficulty of the traditional pre-amplifying circuit under low power supply voltage.
The tail current transistor in the second-stage pre-amplifying circuit is controlled by a clock control signal, so that the complexity of circuit design can be reduced, and the static power consumption of the circuit can be reduced.
In the invention, the pre-discharge transistor controlled by a clock signal and the transistor playing a switching role are added in the CMOS latch circuit, so that the static power consumption of the circuit can be reduced, the offset voltage performance of the comparator circuit can be improved, and the transmission delay of the circuit can be reduced.
The invention enables the comparator to work under higher frequency under low power voltage (1.05V), reduces offset voltage, improves transmission delay of the circuit, reduces power consumption of the circuit and the like, and realizes high-speed application of the analog-to-digital converter. FIG. 7 is a simulated waveform diagram of a circuit when the clock control signal is 5GHz, and FIG. 8 is a simulated waveform diagram of a circuit when the clock control signal is 10 GHz; wherein the first line is a same-direction and reverse-direction input signal, the second line is a clock control signal, and the third and fourth lines are respectively an in-phase and reverse-phase output signal. As can be seen from fig. 7, the offset voltage of the circuit is 0.2mV when the clock signal is 5GHz, and it can be known through calculation that the transmission delay is 63ps and the power consumption of the circuit is 0.37 mW; as can be seen from fig. 8, the offset voltage of the circuit is 0.8mV when the clock signal is 10GHz, and it can be found by calculation that the transmission delay is 44ps and the power consumption of the circuit is 0.44 mW.
Drawings
FIG. 1 is a schematic diagram of a bias circuit according to the present invention;
FIG. 2 is a schematic diagram of a first stage pre-amplifier circuit according to the present invention;
FIG. 3 is a schematic diagram of a second stage pre-amplifier circuit according to the present invention;
FIG. 4 is a schematic diagram of a CMOS latch circuit according to the present invention;
FIG. 5 is a schematic diagram of an SR flip-flop circuit according to the present invention;
FIG. 6 is a schematic diagram of a low offset low power consumption high speed dynamic comparator with low supply voltage;
FIG. 7 is a simulated waveform diagram of the circuit when the clock control signal is 5 GHz;
FIG. 8 is a waveform diagram of a simulation of the circuit when the clock control signal is 10 GHz.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described with reference to the following embodiments, and with reference to the accompanying drawings.
Referring to fig. 6, the high-speed dynamic comparator with low offset and low power consumption under low power supply voltage according to the present invention includes a bias circuit, a first stage pre-amplifier circuit, a second stage pre-amplifier circuit, a CMOS latch circuit, and an SR flip-flop circuit, which are connected in sequence. Wherein:
a bias circuit which receives the current source signal and outputs a first voltage bias signal vbias1 and a second voltage bias signal vbias 2;
a first-stage pre-amplifying circuit, which receives the in-phase input signal vinn, the reverse-phase input signal vinp, the first voltage bias signal vbias1 and the second voltage bias signal vbias2, and outputs a first in-phase output signal and a first reverse-phase output signal;
the second-stage pre-amplification circuit receives the first in-phase output signal, the first inverted output signal and the clock control signal clk and outputs a second in-phase output signal and a second inverted output signal;
a CMOS latch circuit that receives the second in-phase output signal, the second inverted output signal, and the clock control signal, and outputs a third in-phase output signal and a third inverted output signal;
and the SR flip-flop circuit receives the third in-phase output signal and the third reverse-phase output signal and outputs the in-phase output signal and the reverse-phase output signal.
Fig. 1 is a schematic diagram of a bias circuit according to the present invention, and as shown in fig. 1, the bias circuit includes: a first NMOS transistor M1, a second NMOS transistor M2, wherein,
the source of the first NMOS transistor M1 is grounded; the grid electrode of the first NMOS transistor is connected with the drain electrode of the first NMOS transistor and is connected with the source electrode of the second NMOS transistor; the grid electrode of the second NMOS transistor is connected with the drain electrode and the current source signal; the gate of the first NMOS transistor outputs a first voltage bias signal vbias 1; the gate of the second NMOS transistor outputs a second voltage bias signal vbias 2.
The grid and the drain of the first NMOS transistor M1 are connected to form a current mirror type and output a first voltage bias signal vbias 1;
the grid and the drain of the second NMOS transistor M2 are connected to form a current mirror type and output a second voltage bias signal vbias 2; the drain of the second NMOS transistor is connected to the input current source signal.
Fig. 2 is a schematic diagram of a first stage pre-amplifier circuit according to the present invention, as shown in fig. 2, the first stage pre-amplifier circuit includes: a load layer circuit composed of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, and a fourth PMOS transistor P4; a tail current layer circuit composed of a third NMOS transistor M3; a differential pair signal input layer circuit composed of a fourth NMOS transistor M4 and a fifth NMOS transistor M5; and an isolation layer circuit composed of a sixth NMOS transistor M6 and a seventh NMOS transistor M7.
The gate of the third NMOS transistor receives the first bias voltage signal vbias 1; the source electrode of the third NMOS transistor is grounded; the drain electrode of the third NMOS transistor, the source electrode of the fourth NMOS transistor and the source electrode of the fifth NMOS transistor are connected;
the grid electrode of the fourth NMOS transistor receives the in-phase input signal vinn;
the gate of the fifth NMOS transistor receives the inverted input signal vinp;
the drain electrode of the fourth NMOS transistor is connected with the source electrode of the sixth NMOS transistor;
the drain electrode of the fifth NMOS transistor is connected with the source electrode of the seventh NMOS transistor;
the grid electrode of the sixth NMOS transistor and the grid electrode of the seventh NMOS transistor are connected with a second voltage bias signal vbias 2;
the drain electrode of the sixth NMOS transistor, the drain electrode of the first PMOS transistor and the drain electrode of the third PMOS transistor are connected;
the drain electrode of the seventh NMOS transistor, the drain electrode of the second PMOS transistor and the drain electrode of the fourth PMOS transistor are connected;
the drain electrode of the first PMOS transistor, the grid electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor are connected;
the grid electrode of the third PMOS transistor, the drain electrode of the fourth PMOS transistor and the grid electrode of the fourth PMOS transistor are connected;
the source electrode of the first PMOS transistor, the source electrode of the second PMOS transistor, the source electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected with a power supply voltage;
the drain of the sixth NMOS transistor outputs the first non-inverting output signal voutn 1;
the drain of the seventh NMOS transistor outputs the first inverted output signal voutp 1.
Under the original power supply voltage, the four-layer circuit is relatively easy to design, because the higher power supply voltage can provide enough voltage margin for the circuit, but the power supply voltage used in the invention is only 1.05V, which not only causes the output voltage margin of the first-stage pre-amplification circuit to be very small, but also brings certain difficulty to the design of the circuit.
In order to fulfill the design requirements at low supply voltages, in the present invention,
firstly, determining the bias current of the current stage circuit by using a tail current layer circuit;
secondly, under the conditions of current determination and transistor threshold voltage determination, in order to increase the output voltage margin of the circuit of the stage, under the premise of ensuring that the transistor works in a saturation region, the sizes of the transistors in the differential pair signal input layer circuit and the isolation layer circuit are made larger as much as possible;
finally, correspondingly adjusting the load layer circuit according to the same principle;
the design according to the method can not only improve the output voltage margin of the circuit of the stage, but also reduce the mismatching degree of the differential signal and reduce the offset voltage of the comparator circuit.
Fig. 3 is a schematic diagram of a second stage pre-amplifying circuit according to the present invention, as shown in fig. 3, the second stage pre-amplifying circuit includes: an eighth NMOS transistor M8 controlled by the clock control signal; an input pair transistor consisting of a ninth NMOSM9 and a tenth NMOS transistor M10; and an isolation layer power circuit composed of an eleventh NMOS transistor M11 and a twelfth NMOS transistor M12 controlled by a clock control signal.
The grid electrode of the eighth NMOS transistor, the grid electrode of the eleventh NMOS transistor and the grid electrode of the twelfth NMOS transistor receive a clock control signal clk;
the drain electrode of the eighth NMOS transistor, the source electrode of the ninth NMOS transistor and the source electrode of the tenth NMOS transistor are connected;
the gate of the ninth NMOS transistor receives the first inverted output signal voutp 1;
a gate of the tenth NMOS transistor receives a first non-inverting output signal voutn 1;
the drain electrode of the ninth NMOS transistor is connected with the source electrode of the eleventh NMOS transistor;
the drain electrode of the tenth NMOS transistor is connected with the source electrode of the twelfth NMOS transistor;
the source electrode of the eighth NMOS transistor is connected with the ground;
a drain of the eleventh NMOS transistor outputs the second inverted output signal voutp 2;
the drain of the twelfth NMOS transistor outputs the second in-phase output signal voutn 2.
In the invention, the comparator circuit respectively passes through the reset stage (CLK is high level) of the comparator and the regeneration stage (CLK is low level) of the comparator under the control of a clock control signal (CLK), thereby completing one-time data comparison.
Therefore, the tail current tube in the second-stage pre-amplifying circuit is controlled by the clock control signal. Therefore, when the comparator is in a regeneration stage, the tail current tube is cut off, so that one path of current bias is reduced, and the aim of reducing the static power consumption of the circuit is fulfilled.
Fig. 4 is a schematic diagram of a CMOS latch circuit according to the present invention, as shown in fig. 4, the CMOS latch circuit adds a switching transistor controlled by a clock control signal, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventeenth NMOS transistor M17, and a pre-discharge transistor controlled by a clock control signal, a thirteenth NMOS transistor M13, a sixteenth NMOS transistor M16, and adds two inverters at the output of the present stage to reduce the metastable state effect of the comparator, based on the conventional latch.
A CMOS latch circuit comprising: a thirteenth NMOS transistor M13, a fourteenth NMOS transistor M14, a fifteenth NMOS transistor M15, a sixteenth NMOS transistor M16, a seventeenth NMOS transistor M17, an eighteenth NMOS transistor M18, a nineteenth NMOS transistor M19, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a ninth PMOS transistor P9, a tenth PMOS transistor P10, wherein,
the nineteenth NMOS transistor and the tenth PMOS transistor form a first inverter, and the output of the inverter is connected with the third in-phase output signal voutn 3;
the eighteenth NMOS transistor and the ninth PMOS transistor form a second inverter, and the output of the inverter is connected with a third inverted output signal voutp 3;
the source electrode of the thirteenth NMOS transistor, the source electrode of the fourteenth NMOS transistor, the source electrode of the fifteenth NMOS transistor and the source electrode of the sixteenth NMOS transistor are connected with the ground;
the grid electrode of the thirteenth NMOS transistor, the grid electrode of the sixteenth NMOS transistor, the grid electrode of the fifteenth NMOS transistor, the grid electrode of the sixth PMOS transistor and the grid electrode of the seventeenth NMOS transistor are connected with a clock control signal clk;
the drain electrode of the thirteenth NMOS transistor, the drain electrode of the fourteenth NMOS transistor, the grid electrode of the fifteenth NMOS transistor, the drain electrode of the fifth PMOS transistor and the input of the second inverter are connected;
the drain electrode of the sixteenth NMOS transistor, the drain electrode of the fifteenth NMOS transistor, the grid electrode of the fourteenth NMOS transistor, the drain electrode of the sixth PMOS transistor and the input of the first inverter are connected;
the source of the fifth PMOS transistor, the source of the seventeenth NMOS transistor, the drain of the seventh PMOS transistor, and the gate of the eighth PMOS transistor receive the second inverted output signal voutp 2;
the source of the sixth PMOS transistor, the drain of the seventeenth NMOS transistor, the gate of the seventh PMOS transistor, and the drain of the eighth PMOS transistor receive the second in-phase output signal voutn 2;
a source of the seventh PMOS transistor and a source of the eighth PMOS transistor are connected to the supply voltage.
In the present invention, the comparator circuit undergoes two phases of reset and regeneration under the control of the clock control signal. When the circuit is in the reset phase,
first, the seventeenth NMOS transistor M17 enters a conducting state, thereby adjusting the input signal of the CMOS latch circuit to an equilibrium state;
secondly, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 enter an off state, which results in that the CMOS latch circuit has no dc path between its input terminal and the ground during the reset phase;
third, the thirteenth NMOS transistor M13 and the sixteenth NMOS transistor M16 enter a conducting state, thereby forcibly pulling the voltage at both a and b low.
As can be seen from the above-described embodiments,
firstly, the current path from the power supply voltage to the ground wire is not arranged in the stage of reset, so that the static power consumption of the circuit can be reduced;
in the second place, the logic levels at the two places a and b are equal, so that the logic level of the signal transmitted from the CMOS latch circuit to the SR flip-flop circuit at the next stage is equal in the reset stage. The storage effect of the CMOS latch circuit is reduced, the hysteresis is reduced, and the offset voltage performance of the comparator circuit is improved;
thirdly, the above embodiment can reduce the recovery time of the overdrive voltage, thereby reducing the transmission delay of the signal.
Fig. 5 is a schematic diagram of an SR flip-flop circuit according to the present invention, and as shown in fig. 5, the structure of the SR flip-flop is similar to that of a conventional flip-flop, and only signal strength enhancement and protection of the whole circuit are added in the present invention.
An SR flip-flop circuit comprising: a twentieth NMOS transistor N20, a twenty-first NMOS transistor N21, a twenty-second NMOS transistor N22, a twenty-third NMOS transistor N23, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a fourteenth PMOS transistor P14, wherein,
the source electrode of the twentieth NMOS transistor and the source electrode of the twenty-first NMOS transistor are connected with the ground;
the gate of the twentieth NMOS transistor and the gate of the eleventh PMOS transistor receive the third in-phase output signal voutn 3;
the gate of the twenty-first NMOS transistor and the gate of the fourteenth PMOS transistor receive the third inverted output signal voutp 3;
the drain electrode of the twentieth NMOS transistor is connected with the source electrode of the twenty-second NMOS transistor;
the drain electrode of the twenty-first NMOS transistor is connected with the source electrode of the twenty-third NMOS transistor;
the drain electrode of the twenty-third NMOS transistor, the drain electrode of the thirteenth PMOS transistor, the drain electrode of the fourteenth PMOS transistor, the grid electrode of the twelfth PMOS transistor and the grid electrode of the twenty-second NMOS transistor are connected and output the in-phase output signal voutn;
the drain electrode of the twenty-second NMOS transistor, the drain electrode of the eleventh PMOS transistor, the drain electrode of the twelfth PMOS transistor, the grid electrode of the thirteenth PMOS transistor and the grid electrode of the twenty-third NMOS transistor are connected and output an inverted output signal voutp;
a source of the eleventh PMOS transistor, a source of the twelfth PMOS transistor, a source of the thirteenth PMOS transistor, and a source of the fourteenth PMOS transistor are connected to the power supply voltage.
Finally, it should be noted that: the above examples are only for illustrating the technical solutions of the present invention and are not to be construed as limiting the present invention, and although the present invention is described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: modifications of the technical solutions described in the embodiments or equivalent replacements of some technical features may still be made. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A high-speed dynamic comparator with low offset and low power consumption under low power supply voltage is characterized by comprising a bias circuit, a first-stage pre-amplification circuit, a second-stage pre-amplification circuit, a CMOS latch circuit and an SR trigger circuit which are sequentially connected;
the bias circuit receives the current source signal and outputs a first voltage bias signal and a second voltage bias signal;
the first-stage pre-amplification circuit receives the in-phase input signal, the reverse-phase input signal, the first voltage bias signal and the second voltage bias signal and outputs a first in-phase output signal and a first reverse-phase output signal;
the second-stage pre-amplifying circuit receives the first in-phase output signal, the first anti-phase output signal and the clock control signal and outputs a second in-phase output signal and a second anti-phase output signal;
the CMOS latch circuit receives the second in-phase output signal, the second reverse-phase output signal and the clock control signal and outputs a third in-phase output signal and a third reverse-phase output signal;
the SR flip-flop circuit receives a third in-phase output signal and a third reverse-phase output signal and outputs an in-phase output signal and a reverse-phase output signal;
the CMOS latch circuit comprises: a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor, wherein,
the nineteenth NMOS transistor and the tenth PMOS transistor form a first inverter, and the output of the inverter is connected with a third in-phase output signal;
the eighteenth NMOS transistor and the ninth PMOS transistor form a second inverter, and the output of the inverter is connected with a third inverted output signal;
the source electrode of the thirteenth NMOS transistor, the source electrode of the fourteenth NMOS transistor, the source electrode of the fifteenth NMOS transistor and the source electrode of the sixteenth NMOS transistor are connected with the ground;
the grid electrode of the thirteenth NMOS transistor, the grid electrode of the sixteenth NMOS transistor, the grid electrode of the fifteenth NMOS transistor, the grid electrode of the sixth PMOS transistor and the grid electrode of the seventeenth NMOS transistor are connected with a clock control signal;
the drain electrode of the thirteenth NMOS transistor, the drain electrode of the fourteenth NMOS transistor, the gate electrode of the fifteenth NMOS transistor, the drain electrode of the fifth PMOS transistor and the input of the second inverter are connected;
a drain of the sixteenth NMOS transistor, a drain of the fifteenth NMOS transistor, a gate of the fourteenth NMOS transistor, a drain of the sixth PMOS transistor, and an input of the first inverter are connected;
a source electrode of the fifth PMOS transistor, a source electrode of the seventeenth NMOS transistor, a drain electrode of the seventh PMOS transistor, and a gate electrode of the eighth PMOS transistor receive a second inverted output signal;
a source of the sixth PMOS transistor, a drain of the seventeenth NMOS transistor, a gate of the seventh PMOS transistor, and a drain of the eighth PMOS transistor receive a second in-phase output signal;
a source of the seventh PMOS transistor and a source of the eighth PMOS transistor are connected to a supply voltage.
2. The high speed dynamic comparator with low offset and low power consumption under low power supply voltage of claim 1, wherein the bias circuit comprises a first NMOS transistor and a second NMOS transistor, wherein,
the source electrode of the first NMOS transistor is grounded;
the grid electrode of the first NMOS transistor is connected with the drain electrode of the first NMOS transistor and is connected with the source electrode of the second NMOS transistor;
the grid electrode of the second NMOS transistor is connected with the drain electrode and is connected with a current source signal;
the grid electrode of the first NMOS transistor outputs a first voltage bias signal;
the gate of the second NMOS transistor outputs a second voltage bias signal.
3. The low offset low power consumption high speed dynamic comparator according to claim 1, wherein the first stage pre-amplifier circuit comprises: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, wherein,
a gate of the third NMOS transistor receives a first bias voltage signal;
the source of the third NMOS transistor is grounded;
the drain electrode of the third NMOS transistor, the source electrode of the fourth NMOS transistor and the source electrode of the fifth NMOS transistor are connected;
a gate of the fourth NMOS transistor receives an in-phase input signal;
a grid electrode of the fifth NMOS transistor receives an inverted input signal;
the drain electrode of the fourth NMOS transistor is connected with the source electrode of the sixth NMOS transistor;
the drain electrode of the fifth NMOS transistor and the source electrode of the seventh NMOS transistor are connected;
the grid electrode of the sixth NMOS transistor and the grid electrode of the seventh NMOS transistor are connected with a second voltage bias signal;
the drain electrode of the sixth NMOS transistor, the drain electrode of the first PMOS transistor and the drain electrode of the third PMOS transistor are connected;
the drain electrode of the seventh NMOS transistor, the drain electrode of the second PMOS transistor and the drain electrode of the fourth PMOS transistor are connected;
the drain electrode of the first PMOS transistor, the grid electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor are connected;
the grid electrode of the third PMOS transistor, the drain electrode of the fourth PMOS transistor and the grid electrode of the fourth PMOS transistor are connected;
the source electrode of the first PMOS transistor, the source electrode of the second PMOS transistor, the source electrode of the third PMOS transistor and the source electrode of the fourth PMOS transistor are connected with a power supply voltage;
the drain electrode of the sixth NMOS transistor outputs a first in-phase output signal;
a drain of the seventh NMOS transistor outputs a first inverted output signal.
4. The low offset low power consumption high speed dynamic comparator according to claim 1, wherein the second stage of the pre-amplifying circuit comprises: an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor, wherein,
a gate of the eighth NMOS transistor, a gate of the eleventh NMOS transistor, and a gate of the twelfth NMOS transistor receive a clock control signal;
the drain electrode of the eighth NMOS transistor, the source electrode of the ninth NMOS transistor and the source electrode of the tenth NMOS transistor are connected;
a gate of the ninth NMOS transistor receives a first inverted output signal;
a gate of the tenth NMOS transistor receives a first non-inverting output signal;
the drain electrode of the ninth NMOS transistor and the source electrode of the eleventh NMOS transistor are connected;
the drain electrode of the tenth NMOS transistor is connected with the source electrode of the twelfth NMOS transistor;
the source electrode of the eighth NMOS transistor is connected with the ground;
a drain of the eleventh NMOS transistor outputs a second inverted output signal;
the drain of the twelfth NMOS transistor outputs a second in-phase output signal.
5. The low offset low power consumption high speed dynamic comparator according to claim 1, wherein said SR flip-flop circuit comprises: a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second NMOS transistor, a twenty-third NMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, and a fourteenth PMOS transistor, wherein,
the source electrode of the twentieth NMOS transistor and the source electrode of the twenty-first NMOS transistor are connected with the ground;
a gate of the twentieth NMOS transistor and a gate of the eleventh PMOS transistor receive a third in-phase output signal;
the grid electrode of the twenty-first NMOS transistor and the grid electrode of the fourteenth PMOS transistor receive a third inverted output signal;
the drain electrode of the twenty-second NMOS transistor is connected with the source electrode of the twenty-second NMOS transistor;
the drain electrode of the twenty-first NMOS transistor is connected with the source electrode of the twenty-third NMOS transistor;
the drain electrode of the twenty-third NMOS transistor, the drain electrode of the thirteenth PMOS transistor, the drain electrode of the fourteenth PMOS transistor, the gate electrode of the twelfth PMOS transistor and the gate electrode of the twenty-second NMOS transistor are connected and output in-phase output signals;
the drain electrode of the twenty-second NMOS transistor, the drain electrode of the eleventh PMOS transistor, the drain electrode of the twelfth PMOS transistor, the gate electrode of the thirteenth PMOS transistor and the gate electrode of the twenty-third NMOS transistor are connected and output an inverted output signal;
a source of the eleventh PMOS transistor, a source of the twelfth PMOS transistor, a source of the thirteenth PMOS transistor, and a source of the fourteenth PMOS transistor are connected to a supply voltage.
6. A low offset low power consumption high speed dynamic comparator according to any of claims 1 to 5 wherein all NMOS transistors in the circuit have their bulk connected to ground and all PMOS transistors in the circuit have their bulk connected to the supply voltage.
7. The high-speed dynamic comparator with low offset and low power consumption under the low power supply voltage of claim 1, wherein the high-speed dynamic comparator respectively passes through the reset phase of the comparator and the regeneration phase of the comparator under the control of a clock control signal clk, thereby completing one data comparison; controlling a tail current tube in the second-stage pre-amplifying circuit by a clock control signal; when the comparator is in a regeneration stage, the tail current tube is cut off, so that one path of current bias is reduced, and the static power consumption of the circuit is reduced.
8. A low offset low power consumption high speed dynamic comparator with low supply voltage as claimed in claim 1 wherein the comparator circuit undergoes two phases of reset and regeneration under the control of the clock control signal; when the circuit is in the reset phase:
firstly, a seventeenth NMOS transistor enters a conducting state, so that an input signal of the CMOS latch circuit is adjusted to be in a balanced state;
secondly, the fifth PMOS transistor and the sixth PMOS transistor enter a turn-off state, so that no direct current path exists between the input end and the ground wire of the CMOS latch circuit in the reset stage;
third, the thirteenth NMOS transistor and the sixteenth NMOS transistor are brought into a conducting state, thereby forcibly pulling the voltages at the drain a of the fifth PMOS transistor and the drain b of the sixth PMOS transistor to a low level.
9. The low offset low power consumption high speed dynamic comparator according to claim 5, wherein the low supply voltage is 1.05V.
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