CN108666368A - 一种超结mosfet渐变终端结构及其制作方法 - Google Patents
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Abstract
本发明涉及半导体器件技术领域,尤其是一种超结MOSFET渐变终端结构及其制作方法,包括N型衬底和形成于N型衬底上的N型外延层,N型外延层包括元胞区及包围元胞区的终端区,其中元胞区中形成有至少一个晶体管单元,晶体管单元包括形成于N型外延层中的两个元胞区P柱。本发明终端区中形成有至少一个终端区P柱,终端区P柱顶端连接有至少三个P‑型体区,每两个相邻的P‑型体区之间的间距沿着远离元胞区P柱的方向依次增大,多个P‑型体区排布成一系列渐变的P‑型体区结构,该渐变的P‑型体区结构的存在有利于器件的电场向右横向延展,从而有利于提高终端耐压。
Description
技术领域
本发明涉及半导体器件技术领域,尤其是一种超结MOSFET渐变终端结构。
背景技术
VDMOSFET(高压功率MOSFET)可以通过减薄漏端漂移区的厚度来减小导通电阻,然而,减薄漏端漂移区的厚度就会降低器件的击穿电压,因此在VDMOSFET中,提高器件的击穿电压和减小器件的导通电阻是一对矛盾,超结MOSFET采用新的耐压层结构,利用一系列的交替排列的P型和N型半导体薄层,在较低反向电压下将P型N型区耗尽,实现电荷相互补偿,从而使N型区在高掺杂浓度下实现高的击穿电压,从而同时获得低导通电阻和高击穿电压,打破传统功率MOSFET导通电阻的理论极限。
超结MOSFET具有导通损耗低,栅极电荷低,开关速度快,器件发热小,能效高的优点,产品可广泛用于个人电脑、笔记本电脑、上网本或手机、照明(高压气体放电灯)产品以及电视机(液晶或等离子电视机)和游戏机等高端消费电子产品的电源或适配器。
如图1所示,现有的超结MOSFET结构括N型重掺杂衬底201”及形成于N型重掺杂衬底201’上的N型轻掺杂外延层202’;N型轻掺杂外延层202’包括元胞区I及包围元胞区I的终端区II;元胞区I中形成有至少一个晶体管单元,晶体管单元包括形成于N型轻掺杂外延层202’中的一对元胞区P柱203’;该一对元胞区P柱203’顶端分别连接有一P型体区204’,且P型体区204’位于N型轻掺杂外延层202’内;N型轻掺杂外延层202’表面形成有栅极结构;且栅极结构位于一对元胞区P柱203’之间;终端区II中形成有至少一个终端区P柱207’;终端区P柱207’的深度大于元胞区P柱203的深度。现有的超结MOSFET结构及制作工艺存在以下问题:1、终端区中形成有至少一个终端区P柱207’,终端结构的电场横向延展困难,相应地终端结构耐压性低;2、制作工艺中在元胞区沟槽及终端区沟槽中填充P型半导体层,得到元胞区P柱203’及终端区P柱207’,终端区P柱207’延伸至N型轻掺杂外延层202’表面,耐压性低。
发明内容
本发明的目的是克服现有技术存在的缺陷,提供一种超结MOSFET渐变终端结构及其制作方法,解决现有的超结MOSFET终端结构耐压低的问题。
为了实现本发明的目的,所采用的技术方案是:
本发明的超结MOSFET渐变终端结构包括N型衬底和形成于所述N型衬底上的N型外延层,所述N型外延层包括元胞区及包围所述元胞区的终端区,其中所述元胞区中形成有至少一个晶体管单元,所述晶体管单元包括形成于所述N型外延层中的两个元胞区P柱,两个所述元胞区P柱顶端分别连接有P型体区和N+型体区,且所述P型体区和N+型体区位于所述N型外延层内,所述终端区中形成有至少一个终端区P柱,所述终端区P柱顶端连接有至少三个P-型体区,每两个相邻的P-型体区之间的间距沿着远离所述元胞区P柱的方向依次增大。
本发明所述N型外延层表面形成有栅极结构且所述栅极结构位于两个所述元胞区P柱之间,所述栅极结构包括形成于所述N型外延层表面的栅氧化层及形成于所述栅氧化层表面的多晶硅栅极,所述栅极结构两端分别与两个相邻的P型体区接触,且所述栅极结构两端分别与两个相邻的N+型体区接触。
本发明所述元胞区P柱和终端区P柱均为P型单晶硅。
本发明所述N型衬底为N型重掺杂衬底,所述N型外延层为N型轻掺杂外延层。
本发明还提供一种超结MOSFET终端结构的制作方法,用于制作上述的超结MOSFET渐变终端结构,包括以下步骤:
S1:提供一N型衬底,在所述N型衬底上形成N型外延层,对所述N型外延层进行刻蚀,形成若干元胞区沟槽及若干终端区沟槽;
S2:在所述元胞区沟槽及所述终端区沟槽中填充P型半导体,得到元胞区P柱及终端区P柱,然后在所述N型外延层表面再外延一层N型外延层覆盖元胞区沟槽和终端区沟槽;
S3:在位于终端区的N型外延层上部进行B注入和扩散,形成P-型体区,其中,所述终端区P柱顶端连接有至少三个P-型体区,每两个相邻的P-型体区之间的间距沿着远离所述元胞区P柱的方向依次增大;
S4:在位于元胞区的N型轻掺杂外延层上部进行B注入和扩散形成P型体区,每个所述元胞区P柱顶端连接一个P型体区;
S5:在所述N型外延层上表面生成栅氧化层,然后在所述栅氧化层上表面制作多晶硅栅极;
S6:在位于元胞区的栅氧化层上表面进行As注入和扩散,形成N+型体区,N+型体区位于P型体区内;
S7:在所述栅氧化层和多晶硅栅极上生成绝缘层,然后挖接触孔,然后进行金属AL沉积和钝化处理。
本发明在多晶硅栅极的两侧挖接触孔,挖接触孔时将绝缘层和栅氧化层一起刻掉,所述多晶硅栅极及其底部的栅氧化层构成栅极结构,所述栅极结构的两端分别与两个相邻的P型体区接触,且所述栅极结构的两端分别与两个相邻的N+型体区接触。
本发明所述终端区P柱的深度范围为30~60um,所述N型外延层表面再外延一层N型外延层的厚度为3~5um。
本发明所述N型衬底为N型重掺杂衬底,所述N型外延层为N型轻掺杂外延层,掺杂元素为磷。
本发明所述栅氧化层的厚度为1000A,所述绝缘层的厚度为10000A。
本发明的超结MOSFET渐变终端结构及其制作方法的有益效果是:
1、本发明终端区中形成有至少一个终端区P柱,终端区P柱顶端连接有至少三个P-型体区,每两个相邻的P-型体区之间的间距沿着远离元胞区P柱的方向依次增大,多个P-型体区排布成一系列渐变的P-型体区结构,该渐变的P-型体区结构的存在有利于器件的电场向右横向延展,从而有利于提高终端耐压;
2、本发明在所述元胞区沟槽及所述终端区沟槽中填充P型半导体,得到元胞区P柱及终端区P柱,然后在所述N型外延层表面再外延一层3~5um的N型外延层,覆盖元胞区沟槽和终端区沟槽,然后再在该3~5um厚的N型外延层上部进行B注入和扩散,可以提高终端耐压。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明。
图1为现有技术中的超结MOSFET的结构示意图。
图2为本发明的超结MOSFET渐变终端结构的示意图。
图3为本发明的超结MOSFET渐变终端结构的制作方法中的步骤S1的工艺流程图。
图4为本发明的超结MOSFET渐变终端结构的制作方法中的步骤S2的工艺流程图。
图5为本发明的超结MOSFET渐变终端结构的制作方法中的步骤S3的工艺流程图。
图6为本发明的超结MOSFET渐变终端结构的制作方法中的步骤S4的工艺流程图。
图7为本发明的超结MOSFET渐变终端结构的制作方法中的步骤S5的工艺流程图。
图8为本发明的超结MOSFET渐变终端结构的制作方法中的步骤S6的工艺流程图。
图9为本发明的超结MOSFET渐变终端结构的制作方法中的步骤S7的工艺流程图。
其中:201 N型衬底
202 N型外延层
203 元胞区P柱
204 终端区P柱
205 P-型体区
206 P型体区
207 栅氧化层
208 多晶硅栅极
209 N+型体区
210 绝缘层
I 元胞区
II 终端区。
具体实施方式
在本发明的描述中,需要理解的是,术语“径向”、“轴向”、“上”、“下”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。在本发明的描述中,除非另有说明,“多个”的含义是两个或两个以上。
在本发明的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“设置”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体连接;可以是直接相连,也可以通过中间媒介间接相连。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本发明中的具体含义。
如图2所示,本实施例的超结MOSFET渐变终端结构包括N型衬底201和形成于N型衬底201上的N型外延层202,N型外延层202包括元胞区及包围元胞区的终端区,其中元胞区中形成有至少一个晶体管单元,晶体管单元包括形成于N型外延层202中的两个元胞区P柱203,两个元胞区P柱203顶端分别连接有P型体区206和N+型体区209,且P型体区206和N+型体区209位于N型外延层202内,终端区中形成有至少一个终端区P柱204,终端区P柱204顶端连接有至少三个P-型体区205,每两个相邻的P-型体区205之间的间距沿着远离元胞区P柱203的方向依次增大,多个P-型体区205排布成一系列渐变的P-型体区结构,该渐变的P-型体区结构的存在有利于器件的电场向右横向延展,从而有利于提高终端耐压。
本实施例的N型外延层202表面形成有栅极结构且栅极结构位于两个元胞区P柱203之间,栅极结构包括形成于N型外延层202表面的栅氧化层207及形成于栅氧化层207表面的多晶硅栅极208,栅极结构两端分别与两个相邻的P型体区206接触,且栅极结构两端分别与两个相邻的N+型体区209接触。
进一步地,元胞区P柱203和终端区P柱204均为P型单晶硅,N型衬底201为N型重掺杂衬底,N型外延层202为N型轻掺杂外延层。
优选的,终端区P柱204的深度范围为30~60um,栅氧化层207的厚度为1000A。
如图3-9所示,本实施例还提供一种超结MOSFET终端结构的制作方法,用于制作上述的超结MOSFET渐变终端结构,包括以下步骤:
S1:提供一N型衬底201,在N型衬底201上形成N型外延层202,对N型外延层202进行刻蚀,形成若干元胞区沟槽及若干终端区沟槽;
S2:在元胞区沟槽及终端区沟槽中填充P型半导体,得到元胞区P柱203及终端区P柱204,然后在N型外延层202表面再外延一层N型外延层202覆盖元胞区沟槽和终端区沟槽;
S3:在位于终端区的N型外延层202上部进行B注入和扩散,形成P-型体区205,其中,终端区P柱204顶端连接有至少三个P-型体区205,每两个相邻的P-型体区205之间的间距沿着远离元胞区P柱203的方向依次增大;
S4:在位于元胞区的N型轻掺杂外延层上部进行B注入和扩散形成P型体区206,每个元胞区P柱203顶端连接一个P型体区206;
S5:在N型外延层202上表面生成栅氧化层207,然后在栅氧化层207上表面制作多晶硅栅极208;
S6:在位于元胞区的栅氧化层207上表面进行As注入和扩散,形成N+型体区209,N+型体区209位于P型体区206内;
S7:在栅氧化层207和多晶硅栅极208上生成绝缘层210,然后挖接触孔,具体地,参见图9,在多晶硅栅极208的两侧挖接触孔,挖接触孔时将绝缘层210和栅氧化层207一起刻掉,多晶硅栅极208及其底部的栅氧化层207构成栅极结构,栅极结构的两端分别与两个相邻的P型体区206接触,且栅极结构的两端分别与两个相邻的N+型体区209接触,然后进行金属AL沉积和钝化处理。
参见图9,金属AL沉积后形成源极金属层,源极金属层填充进接触孔内并与N+型体区209及P型体区206接触,源极金属层与多晶硅栅极208之间通过绝缘层210隔离,至此制作得到本发明的超结MOSFET渐变终端结构,本发明的超结MOSFET渐变终端结构的制作工艺步骤简单易行,可以制作出性能优异的耐高压的超结MOSFET渐变终端结构。
优选的,终端区P柱204的深度范围为30~60um,N型外延层202表面再外延一层N型外延层202的厚度为3~5um,该外延出的N型外延层202可以提高终端耐压。
进一步地,栅氧化层207的厚度为1000A,绝缘层210的厚度为10000A。
进一步地,N型衬底201为N型重掺杂衬底,N型外延层202为N型轻掺杂外延层,掺杂元素为磷。
应当理解,以上所描述的具体实施例仅用于解释本发明,并不用于限定本发明。由本发明的精神所引伸出的显而易见的变化或变动仍处于本发明的保护范围之中。
Claims (9)
1.一种超结MOSFET渐变终端结构,包括N型衬底(201)和形成于所述N型衬底(201)上的N型外延层(202),所述N型外延层(202)包括元胞区及包围所述元胞区的终端区,其中所述元胞区中形成有至少一个晶体管单元,所述晶体管单元包括形成于所述N型外延层(202)中的两个元胞区P柱(203),两个所述元胞区P柱(203)顶端分别连接有P型体区(206)和N+型体区(209),且所述P型体区(206)和N+型体区(209)位于所述N型外延层(202)内,所述终端区中形成有至少一个终端区P柱(204),其特征在于:所述终端区P柱(204)顶端连接有至少三个P-型体区(205),每两个相邻的P-型体区(205)之间的间距沿着远离所述元胞区P柱(203)的方向依次增大。
2.根据权利要求1所述的超结MOSFET渐变终端结构,其特征在于:所述N型外延层(202)表面形成有栅极结构且所述栅极结构位于两个所述元胞区P柱(203)之间,所述栅极结构包括形成于所述N型外延层(202)表面的栅氧化层(207)及形成于所述栅氧化层(207)表面的多晶硅栅极(208),所述栅极结构两端分别与两个相邻的P型体区(206)接触,且所述栅极结构两端分别与两个相邻的N+型体区(209)接触。
3.根据权利要求1所述的超结MOSFET渐变终端结构,其特征在于:所述元胞区P柱(203)和终端区P柱(204)均为P型单晶硅。
4.根据权利要求1所述的超结MOSFET渐变终端结构,其特征在于:所述N型衬底(201)为N型重掺杂衬底,所述N型外延层(202)为N型轻掺杂外延层。
5.一种超结MOSFET渐变终端结构的制作方法,用于制作如权利要求1所述的超结MOSFET渐变终端结构,其特征在于:包括以下步骤:
S1:提供一N型衬底(201),在所述N型衬底(201)上形成N型外延层(202),对所述N型外延层(202)进行刻蚀,形成若干元胞区沟槽及若干终端区沟槽;
S2:在所述元胞区沟槽及所述终端区沟槽中填充P型半导体,得到元胞区P柱(203)及终端区P柱(204),然后在所述N型外延层(202)表面再外延一层N型外延层(202)覆盖元胞区沟槽和终端区沟槽;
S3:在位于终端区的N型外延层(202)上部进行B注入和扩散,形成P-型体区(205),其中,所述终端区P柱(204)顶端连接有至少三个P-型体区(205),每两个相邻的P-型体区(205)之间的间距沿着远离所述元胞区P柱(203)的方向依次增大;
S4:在位于元胞区的N型轻掺杂外延层上部进行B注入和扩散形成P型体区(206),每个所述元胞区P柱(203)顶端连接一个P型体区(206);
S5:在所述N型外延层(202)上表面生成栅氧化层(207),然后在所述栅氧化层(207)上表面制作多晶硅栅极(208);
S6:在位于元胞区的栅氧化层(207)上表面进行As注入和扩散,形成N+型体区(209),N+型体区(209)位于P型体区(206)内;
S7:在所述栅氧化层(207)和多晶硅栅极(208)上生成绝缘层(210),然后挖接触孔,然后进行金属沉积。
6.根据权利要求5所述的超结MOSFET渐变终端结构的制作方法,其特征在于:在多晶硅栅极(208)的两侧挖接触孔,挖接触孔时将绝缘层(210)和栅氧化层(207)一起刻掉,所述多晶硅栅极(208)及其底部的栅氧化层(207)构成栅极结构,所述栅极结构的两端分别与两个相邻的P型体区(206)接触,且所述栅极结构的两端分别与两个相邻的N+型体区(209)接触。
7.根据权利要求5所述的超结MOSFET渐变终端结构的制作方法,其特征在于:所述终端区P柱(204)的深度范围为30~60um,所述N型外延层(202)表面再外延一层N型外延层(202)的厚度为3~5um。
8.根据权利要求5所述的超结MOSFET渐变终端结构的制作方法,其特征在于:所述N型衬底(201)为N型重掺杂衬底,所述N型外延层(202)为N型轻掺杂外延层,掺杂元素为磷。
9.根据权利要求5所述的超结MOSFET渐变终端结构的制作方法,其特征在于:所述栅氧化层(207)的厚度为1000A,所述绝缘层(210)的厚度为10000A。
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