CN101931005B - 半导体装置及其制造方法和使用它的电源装置 - Google Patents
半导体装置及其制造方法和使用它的电源装置 Download PDFInfo
- Publication number
- CN101931005B CN101931005B CN2010101855348A CN201010185534A CN101931005B CN 101931005 B CN101931005 B CN 101931005B CN 2010101855348 A CN2010101855348 A CN 2010101855348A CN 201010185534 A CN201010185534 A CN 201010185534A CN 101931005 B CN101931005 B CN 101931005B
- Authority
- CN
- China
- Prior art keywords
- mentioned
- resistance
- conduction type
- semiconductor region
- interarea
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 144
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000004020 conductor Substances 0.000 claims description 37
- 239000012212 insulator Substances 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 238000005304 joining Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 87
- 229910052710 silicon Inorganic materials 0.000 abstract description 86
- 239000010703 silicon Substances 0.000 abstract description 86
- 239000000126 substance Substances 0.000 abstract 3
- 230000015556 catabolic process Effects 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 13
- 230000000694 effects Effects 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000003139 buffering effect Effects 0.000 description 8
- 238000005755 formation reaction Methods 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 238000000059 patterning Methods 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000009467 reduction Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- UXUFTKZYJYGMGO-CMCWBKRRSA-N (2s,3s,4r,5r)-5-[6-amino-2-[2-[4-[3-(2-aminoethylamino)-3-oxopropyl]phenyl]ethylamino]purin-9-yl]-n-ethyl-3,4-dihydroxyoxolane-2-carboxamide Chemical compound O[C@@H]1[C@H](O)[C@@H](C(=O)NCC)O[C@H]1N1C2=NC(NCCC=3C=CC(CCC(=O)NCCN)=CC=3)=NC(N)=C2N=C1 UXUFTKZYJYGMGO-CMCWBKRRSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
提供一种半导体装置及其制造方法和使用它的电源装置。在横型功率MOSFET中,不仅抑制了单元间距的增大,还提高了耐压,降低了反馈电容和接通电阻。相对于n+型硅衬底(1)的主面(72)垂直地设置作为耐压保持区域的高电阻的n-型硅区(3),使高电阻的n-型硅区(3)与n+型硅衬底(1)连接。另外,与高电阻的n-型硅区(3)相接地在从n+型硅衬底(1)的主面(72)到达n+型硅衬底(1)的沟槽(61)内隔着绝缘体(4)填充有导电体(5),把上述导电体(5)与源电极(13)电连接。
Description
技术领域
本发明涉及半导体装置及其制造方法和使用它的电源装置,尤其涉及适用于功率MOSFET和使用它的电力变换用的电源装置的有效技术。
背景技术
现在,在向个人计算机或服务商的CPU(中央处理单元)供给电力的开关电源(以下称VR,即Voltage Regulator)中使用沟槽MOSFET(金属氧化物半导体场效应晶体管)(例如专利文献1、专利文献2)。沟槽MOSFET与平面MOSFET(例如非专利文献1)相比,由于单元间距小,所以具有每单位面积的沟槽宽度大、可以降低接通电阻的优点,但由于沟槽栅与漏区的对置面积大,所以具有反馈电容大的缺点。
近年来,由于CPU的大电流化和低电压化,所以抑制CPU的消耗电流变化时的CPU电压的变化的输出电容器增多,导致VR的尺寸和成本增加。已知,为了削减输出电容器,提高VR的开关频率是有效的(例如非专利文献2或非专利文献3)。
提高开关频率时的瓶颈是,因伴随着开关产生的损失,MOSFET超过使用温度的上限(例如150℃)。作为开关时产生的损失,针对VR的高侧MOSFET有接通损失、截止损失和驱动损失,针对低侧MOSFET有内置二极管的导通损失、复原损失和驱动损失,但其中高侧MOSFET的接通损失和截止损失占的比率相对较大。下面,把接通损失和截止损失统称为开关损失。
为了降低开关损失,降低MOSFET的反馈电容是有效的。因为,如果反馈电容减小,则开关速度加快,开关损失降低。沟槽MOSFET本质上存在反馈电容大的问题,难以进一步提高开关频率。
虽然作为可以降低反馈电容的结构有横型MOSFET,但有接通电阻大的缺点。作为横型MOSFET的接通电阻大的理由,可以举出以下两点。
第一,由于保持耐压的区域相对于半导体衬底的表面为水平方向,所以在提高耐压时必须增大水平方向的距离,单元间距增大,接通电阻增大。
第二,由于从衬底表面获取漏和源的电极,所以漏电流相对于衬底表面在水平方向上流动时的电极的电阻即所谓扩展电阻增大。
作为解决上述第二问题的手段,提出了在半导体衬底的背面上设置源电极或漏电极,经由扩散层或金属、多晶硅等的导电体在衬底背面上流过电流的结构(例如专利文献3、专利文献4)。由于通过在背面上设置源电极或漏电极可以增大源电极和漏电极的面积,所以可以降低电极的扩展电阻。
<专利文献1>日本特开2008-218711号公报
<专利文献2>日本特开2005-57050号公报
<专利文献3>日本特开2002-368121号公报
<专利文献4>日本特开平6-232396号公报
<非专利文献1>J.Ng等,″A Novel Planar Power MOSFET withLaterally Uniform Body and Ion-Implanted JFET Region″,IEEEElectron Device Letter,2008,Vol.29,No.4,pp.375-377,April 2008。
<非专利文献2>Y.Ren等,″Analysis of the power delivery pathfrom the 12-V VR to the microprocessor″,Proc.IEEE APEC′04,2004,Vol.1,pp.285-291。
<非专利文献3>M.Xu等,″Small signal modeling of a highbandwidth voltage regulator using coupled inductor″,IEEE Trans.Power Electron,Vol.22,No.2,pp.399-406,Mar.2007。
发明内容
(发明要解决的问题)
虽然利用专利文献3和专利文献4可以解决上述第二问题,但上述第一问题,即由于保持耐压的区域相对于半导体衬底的表面为水平方向,所以在提高耐压时必须增大水平方向的距离、单元间距增大、接通电阻增大的问题未被改善。
本发明的目的在于,在横型功率MOSFET中提供不仅防止了元件面积的扩大、还可以降低反馈电容和接通电阻的技术。
本发明的上述和其它的目的和新颖特征,从本说明书的描述和附图可以清楚地看出。
(用来解决问题的手段)
如果简要地说明本申请中公开的发明中的代表性方案的概要,则如下所述。
根据本申请的一个发明的半导体装置,具有在具有第一电阻的第一导电类型的半导体衬底的主面上形成的功率MOSFET,上述功率MOSFET具有:
在上述具有第一电阻的第一导电类型的半导体衬底的主面上形成的、具有比上述第一电阻高的第二电阻的半导体区;
在上述具有第二电阻的半导体区的表面的一部分上形成的、具有比上述第一电阻高的第三电阻的第一导电类型的半导体区;
在上述具有第二电阻的半导体区的表面的一部分上形成的第二导电类型的半导体区;
在上述第二导电类型的半导体区的表面的一部分上形成的、具有比上述第三电阻低的第四电阻的第一导电类型的半导体区;
在上述具有第二电阻的半导体区的主面上,隔着栅绝缘膜形成的栅电极;
在上述具有第二电阻的半导体区的主面上,与上述栅电极隔着绝缘膜形成,且与上述具有第四电阻的第一导电类型的半导体区电连接的源电极;以及
在上述具有第一电阻的第一导电类型的半导体衬底的背面上形成的漏电极;且
上述具有第三电阻的第一导电类型的半导体区从上述具有第二电阻的半导体区的主面一直设置到上述具有第一电阻的第一导电类型的半导体衬底,
与上述具有第三电阻的第一导电类型的半导体区相接地形成从上述具有第二电阻的半导体区的主面一直设置到上述具有第一电阻的第一导电类型的半导体衬底的沟槽,在上述沟槽内隔着绝缘体填充有导电体,上述导电体与上述源电极电连接。
(发明的效果)
如果简要地说明由本申请中公开的发明中的代表性方案分别得到的效果,则如下所述。
在横型MOSFET中,提供不仅防止了元件面积的扩大、还可以降低反馈电容和接通电阻的技术。
附图说明
图1是示出本发明的实施方式1的半导体装置的概要剖面图。
图2是示出本发明的实施方式1的半导体装置的制造方法的概要剖面图。
图3是示出接着图2的半导体装置的制造方法的概要剖面图。
图4是示出接着图3的半导体装置的制造方法的概要剖面图。
图5是示出接着图4的半导体装置的制造方法的概要剖面图。
图6是示出接着图5的半导体装置的制造方法的概要剖面图。
图7是示出接着图6的半导体装置的制造方法的概要剖面图。
图8是示出接着图7的半导体装置的制造方法的概要剖面图。
图9是示出接着图8的半导体装置的制造方法的概要剖面图。
图10是示出接着图9的半导体装置的制造方法的概要剖面图。
图11是示出接着图10的半导体装置的制造方法的概要剖面图。
图12是示出接着图11的半导体装置的制造方法的概要剖面图。
图13是示出本发明的实施方式2的半导体装置的概要剖面图。
图14是附加了缓冲电阻和缓冲电容的功率MOSFET的电路图。
图15是非绝缘型降压变换器的电路图。
图16(a)是有缓冲电阻和缓冲电容的电源装置的开关时的电压波形,(b)是没有缓冲电阻和缓冲电容的电源装置的开关时的电压波形。
图17(a)是本发明的实施方式3的半导体装置的平面图,(b)是本发明的实施方式3的半导体装置的概要剖面图。
图18是示出接通电阻和反馈电容的折衷关系的图。
(附图标记说明)
1:n+型硅衬底(半导体衬底);3:高电阻的n-型硅区(第二漂移区);4:绝缘体;5:导电体;6:p型硅区(阱区);7:p+型硅区(阱区·接触区);8:n+型硅区(源区);9:栅绝缘膜;10:栅电极;11:硅化物等的低电阻的导电膜;12:绝缘膜;13:源电极;14:漏电极;15、16:接触孔;17:绝缘膜;21:n-型硅区(第一漂移区);31:电源控制器;32:驱动器;33:处理器;34:高侧MOSFET;35:高侧内置二极管;36:低侧MOSFET;37:低侧内置二极管;41:功率MOSFET;42:内置二极管;43:缓冲电阻;44:缓冲电容;51、52:接触;61、62:沟槽;72:主面;73:背面;La:单元间距
具体实施方式
在以下实施方式中,为了方便,需要分成多个部分或实施方式进行说明,但除了特别明示的情形以外,它们相互间不是没有关系,而是具有如下关系:一方是另一方的一部分或全部变形例、细节、补充说明等。
另外,在以下实施方式中,在提到要素的数等(包括个数、数值、数量、范围等)时,除了特别明示的情形和从原理上看很显然限于特定的数的情形等以外,但并不限定于该特定的数,可以是特定的数以上,也可以是特定的数以下。
而且,在以下实施方式中,其构成要素(也包括要素步骤等),除了特别明示的情形和从原理上看认为很显然是必需的情形等以外,也不是必需的,这是不言而喻的。另外,在实施方式等中,关于构成要素等提到“由A构成”时,除了特别明示仅由该要素构成的情形等以外,不排除除此之外的要素,这是不言而喻的。
同样地,在以下实施方式中,在提到构成要素等的形状、位置关系等时,除了特别明示的情形和从原理上看很显然不是这样的情形等以外,包括基本上与该形状等近似或类似的情况等。这一点对于上述数值和范围也是一样。
另外,在提及材料等时,除了特别明示不是这样的情形或从原理上或根据情况看不是这样的情形时以外,特定的材料是主要材料,并不排除次要的要素、添加物、附加要素等。例如,硅部件除了特别明示的情形等以外,不仅包括纯硅的情形,也包括添加杂质、以硅为主要要素的二元、三元等的合金(例如SiGe)等。
另外,在用来说明以下的实施方式的全部附图中,原则上对具有相同功能的部件赋予相同的附图标记,省略其重复说明。
另外,在以下的实施方式使用的附图中,即使是平面图,为了容易观察,有时也部分地添加了阴影线。
(实施方式1)
图1示出实施了本发明的实施方式1的横型功率MOSFET的剖面图,图中附图标记1是n+型硅衬底(半导体衬底);21是n-型硅区(第一漂移区);3是高电阻的n-型硅区(第二漂移区);6是p型硅区(阱区);7是p+型硅区(阱区·接触区);8是n+型硅区(源区);9是栅绝缘膜;10是栅电极;11是硅化物等的低电阻的导电膜;12是绝缘膜;13是源电极;14是漏电极。与n-型硅区3邻接着设置有沟槽(沟)61,隔着绝缘体4用导电体5填充沟槽61内部,导电体5与源电极13电连接。
在此,把设置了源的n+型硅区8和阱的p型硅区6的半导体衬底面称为主面72(第一主表面)、把n+型硅衬底1的背面称为半导体衬底的背面73(第二主表面)。
在n+型硅衬底1的表面上预先用例如外延生长法等形成n-型硅区21,在该n-型硅区21的表面上通过离子注入和扩散工序形成n-型硅区3和p型硅区6。制造工序的细节在后面说明。
在本实施方式所示的横型功率MOSFET中,上述各要素中尤其是漏、源、栅这三个主要端子是如下那样的构成。n-型硅区21和n-型硅区3构成漏,隔着邻接的n+型硅衬底1与漏电极14连接。n+型硅区8构成源,与源电极13连接。在p型硅区6的表面上被栅绝缘膜9隔开的栅电极10构成栅。p型硅区6构成阱区。
如果向栅电极10施加正的电压,则在p型硅区6上经由栅绝缘膜9产生电场,在p型硅区6中的与栅绝缘膜9接合的接合面处电场强度特别强,反转成n型,生成载流子。此时,如果在源电极13与漏电极14之间施加有电压,则通过源的n+型硅区8和漏的n-型硅区3引起载流子的漂移。
另外,以与p型硅区6电接触的方式从衬底表面到p型硅区6设置沟槽(沟)62,成为与源的n+型硅区8一体地导通了的结构。此时,为了欧姆连接而在源电极13和p型硅区6的接触面上形成有p+型硅区7。
在本实施方式中,漏电极14与背面73相接地设置,但由于一般情况下横型MOSFET的漏电极和源电极都设置在半导体衬底的主面上,所以统称为“横型”。另一方面,由于专利文献1和专利文献2的沟槽MOSFET的漏电极设置在半导体衬底的背面上,所以称为纵型MOSFET。
在本实施方式所示的横型功率MOSFET中,图1所示的功率MOSFET是基本单位,称为单位单元(unit cell)。实际中是多个单位单元成为反复的基本单位而排列的结构。把单位单元的横方向的尺寸称为单元间距La,单元间距La小时在单位面积上敷设的单位单元的数目多,可以降低接通电阻。
另外,通过使n-型硅区3隔着绝缘体4与导电体5相接,可以提高n-型硅区3的杂质浓度,降低n-型硅区3的电阻。通过使与源电极电连接的导电体隔着绝缘物与n-型硅区邻接来降低n-型硅区的电阻,作为“RESURF效果”是已知的(例如,P.Goarin等,″Split-gateRESURF stepped oxide(RSO)MOSFET for 25V applications withrecord low gate-to-drain charge″,Proc.IEEE ISPSD′07,May 2007,pp.61-64)。
下面,用图2~图12描述本发明的实施方式1的半导体装置的制造方法。
首先,像图2所示那样,在n+型硅衬底1上用外延生长法形成n-型硅区21。
然后,像图3所示那样,用光掩模构图后,用干法蚀刻形成沟槽(沟)61。
然后,像图4所示那样,用光掩模构图后,通过离子注入形成n-型硅区3。此时,通过使离子注入的角度从与衬底表面垂直的方向偏离,在沟槽61侧面上形成n-型硅区3。
然后,像图5所示那样,通过热扩散在沟槽61内形成由二氧化硅构成的绝缘体4。另外,作为绝缘体4的材料,也可以使用BST((Ba,Sr)TiO3)。
然后,像图6所示那样,用CVD(化学气相沉积)法沉积多晶硅,通过回蚀(etch back)除去在沟槽61的内侧以外沉积的多晶硅,形成导电体5。另外,作为导电体5的材料,除多晶硅以外也可以使用钨等的高熔点金属。
然后,像图7所示那样,用光掩模构图后,通过离子注入形成p型硅区6。
然后,像图8所示那样,通过热氧化形成作为栅绝缘膜9的二氧化硅后,用CVD法沉积作为栅电极10的多晶硅和作为导电膜11的硅化物,用光掩模构图后,用干法蚀刻形成栅绝缘膜9、栅电极10和导电膜11。
然后,像图9所示那样,用光掩模构图后,通过离子注入形成作为源的n+型硅区8。
然后,像图10所示那样,用CVD法沉积作为绝缘膜12的二氧化硅,用光掩模构图后,为了获得源电极的接触,在绝缘膜12上形成接触孔15。
然后,像图11所示那样,用干法蚀刻在p型硅区6上形成沟槽62后,为了获得p型硅区6与源电极的欧姆接触,通过离子注入在沟槽62的底部形成p+型硅区7。
然后,像图12所示那样,用光掩模构图后,用干法蚀刻形成用来连接导电体5的多晶硅和源电极的接触孔16,最后用CVD法在n+型硅衬底1的主面上和背面上分别沉积源电极13和漏电极14,完成本实施方式的半导体装置。在此,作为源电极13和漏电极14的材料,主要使用Al(铝)。
本实施方式与现有例(专利文献3、专利文献4)的不同之处在于,与半导体衬底的主面72垂直地设置称为漂移区的保持耐压的区域(n-型硅区3)。在现有例(专利文献3、专利文献4)中,虽然也是漏电极与背面73相接地设置,但由于从主面72向背面73沿垂直方向流动的电流路径是多晶硅或金属等的导电体,所以在垂直方向上不能保持耐压,MOSFET的耐压由n-型硅区3的横方向(相对于主面72为水平方向)的尺寸确定。因此,为了提高耐压必须增大横方向的尺寸,所以存在单元间距La增宽、接通电阻增加的问题。
与此不同,在本实施方式中,由于作为漂移区的n-型硅区3与主面72垂直地形成,所以在提高耐压时,只要增大纵方向(相对于主面72为垂直方向)的尺寸即可,所以即使提高耐压也不会增大单元间距La,可以抑制接通电阻的增加。
下面,对本实施方式中提高雪崩耐量的设计方针进行描述。雪崩耐量指向MOSFET施加了超过耐压的电压时MOSFET不会物理破坏的电流值,该电流值被称为雪崩峰值电流(Iap)。已知一般情况下,横型MOSFET在主面72附近发生击穿,所以雪崩耐量低。在本实施方式中,通过设计成p型硅区6与n-型硅区21的接合耐压比p型硅区6与高电阻的n-型硅区3的接合耐压低,在p型硅区6与n-型硅区21的接合面附近即半导体衬底内部发生击穿,可以提高雪崩耐量。
另外,在本实施方式中,虽然与n-型硅区21邻接地形成有绝缘体4和导电体5,但也可以没有该绝缘体4、导电体5以及接触孔16。但此时,由于不能提高n-型硅区3的杂质浓度,所以不能降低n-型硅区3的电阻,不能得到RESURF效果。作为制造方法,有取代绝缘体4和导电体5而向沟槽61内填充由二氧化硅等的绝缘体构成的绝缘物的方法、或者不形成沟槽61而通过以光刻胶为掩模的离子注入形成n-型硅区21的方法等。
(实施方式2)
图13示出实施本发明的实施方式2的横型功率MOSFET的剖面图,与实施方式1的不同之处在于,取代n-型硅区21而使用p-型硅区2。通过使p-型硅区2与n-型硅区3邻接地配置可以提高n-型硅区3的杂质浓度、降低电阻。作为“超结”,一般已知:像上述那样,使p型区与n型区邻接地配置而降低电阻,(例如,G.Deboy等,″A newgeneration of high voltage MOSFETs breaks the limit line of silicon″,Technical digest IEEE IEDM′98,December 1998,pp.683-685)。
另外,在本实施方式中也是,也可以没有绝缘体4、导电体5以及接触孔16。但此时不能得到RESURF(降低表面电场)效果。
(实施方式3)
下面,用图14~图18说明本发明的实施方式3。图14是在功率MOSFET 41与内置二极管42上追加了缓冲电阻43和缓冲电容44的电路图。缓冲电阻43和缓冲电容44的串联电路连接在功率MOSFET41的漏和源之间,具有抑制MOSFET开关时的电压变化的效果。
图15示出向处理器等供给电力的电源中使用的电路构成,称为非绝缘型降压(Buck)变换器。降压变换器由输入电源Vin、输入电容器Cin、高侧MOSFET 34、高侧MOSFET 34的内置二极管35、低侧MOSFET 36、低侧MOSFET 36的内置二极管37、驱动高侧MOSFET 34和低侧MOSFET 36的驱动器32、驱动器32的电源Vdrive、向驱动器32供给PWM信号的电源控制器31、构成输出滤波器的输出电感器L、输出电容器Cout和作为负载的处理器33构成。高侧MOSFET 34接通时,低侧MOSFET 36的漏电压Vsw上升到电源电压Vin。此时,受从输入电容器Cin到高侧MOSFET 34和低侧MOSFET 36的环路中存在的寄生电感的影响,低侧MOSFET 36的漏电压Vsw上升到电源电压Vin以上,发生电压振动。近年来,为了降低降压变换器的损失,提高驱动电路的驱动力,使MOSFET高速地开关,因此,具有伴随着电压振动而产生的噪声对电子设备施加影响的问题。
图16(a)、(b)示出接通高侧MOSFET时的低侧MOSFET的漏电Vsw的电压波形。测定点是图15中的Vsw点。
可以看出,在有缓冲电阻和缓冲电容时(图16(a)),与没有缓冲电阻和缓冲电容时(图16(b))相比,电压振动被抑制。这是因为,通过用缓冲电容缓和开关时的电压跳升,抑制了峰值电压,缓冲电阻阻滞了电压振动。这样,缓冲电容和缓冲电阻具有抑制开关时的峰值电压和电压振动的效果,但在追加了外带电容和电阻时,存在增加降压变换器的成本和安装面积的问题。
在本实施方式中,提供不追加外带电容和电阻而在半导体衬底上制作缓冲电容和缓冲电阻的方法。图17是说明本实施方式中的半导体装置的图,图17(a)示出图17(b)的B-B线处的剖面的平面图,图17(b)示出图17(a)的A-A线处的剖面图。图17(a)中,51表示源电极13与导电体5的接触,52表示源电极13与n+型硅区8和p+型硅区7的接触,17表示图17(b)中的由栅绝缘膜9和绝缘膜12构成的绝缘膜。本实施方式与实施方式2的不同之处在于,导电体5与源电极13的接触51是在衬底表面的水平方向上断断续续地设置的。
在图17(a)中,虽然源电极13与n+型硅区8和p+型硅区7的接触52是连续地设置的,但导电体5与源电极13的接触51是断断续续地设置的。在本实施方式中,缓冲电容44由以绝缘体4为介电体、以导电体5、n-型硅区3和n+型硅衬底1为电极的电容器构成,缓冲电阻43由导电体5构成。为了将导电体5用作缓冲电阻43,需要使导电体5成为所期望的电阻值,但可以通过改变导电体5的电阻率或导电体5与源电极13的接触51的间隔来调整导电体5的电阻值。关于接触51的间隔变更,可以通过扩大接触51的间隔来增大电阻值,通过缩窄接触51的间隔来减小电阻值。
下面,图18通过比较沟槽MOSFET和横型MOSFET来示出本发明的效果。图18是以接通电阻Ron为横轴、以反馈电容Crss为纵轴的图,A表示本实施方式的半导体装置,B表示现有的横型MOSFET,C表示现有的沟槽MOSFET。圆圈是沟槽MOSFET、横型MOSFET以及本实施方式的半导体装置在同一芯片面积下的比较。
关于沟槽MOSFET,虽然接通电阻小但反馈电容大,可以通过改变MOSFET的芯片面积来实现接通电阻和反馈电容的折衷曲线的任意特性。即,如果增大芯片面积则是图中左上的特性(接通电阻小、反馈电容大),如果减小芯片面积则是图中右下的特性(接通电阻大、反馈电容小)。横型MOSFET在相同芯片面积下与沟槽MOSFET比较时,虽然接通电阻增大,但反馈电容减小,就折衷性而言有所改善。但是,在横型MOSFET中,为了实现与沟槽MOSFET同等的接通电阻,需要将芯片面积增大3倍左右,导致芯片成本增加。
根据本发明,除了实施方式1的效果以外,还能够使接通电阻与沟槽MOSFET相比的增加停留在30%左右,且折衷性比横型MOSFET更加改善。由此,可以实现反馈电容和接通电阻小的功率MOSFET,所以对于使用它的电源装置的损失降低和成本降低有效果。
以上,基于实施方式具体说明了由本发明人完成的发明,但本发明不限于上述实施方式,在不脱离本发明的主要发明构思的范围内可以进行种种变更。
产业上的可利用性
本发明的半导体装置的制造方法广泛应用于向计算机供给电力的变换中使用的电源装置。
Claims (20)
1.一种半导体装置,具有在具有第一电阻的第一导电类型的半导体衬底的主面上形成的功率MOSFET,其特征在于:
上述功率MOSFET具有:
在上述具有第一电阻的第一导电类型的半导体衬底的主面上形成的、具有比上述第一电阻高的第二电阻的半导体区;
在上述具有第二电阻的半导体区的表面的一部分上形成的、具有比上述第一电阻高的第三电阻的第一导电类型的半导体区;
在上述具有第二电阻的半导体区的表面的一部分上形成的第二导电类型的半导体区;
在上述第二导电类型的半导体区的表面的一部分上形成的、具有比上述第三电阻低的第四电阻的第一导电类型的半导体区;
在上述具有第二电阻的半导体区的主面上,隔着栅绝缘膜形成的栅电极;
在上述具有第二电阻的半导体区的主面上,与上述栅电极隔着绝缘膜形成,且与上述具有第四电阻的第一导电类型的半导体区电连接的源电极;以及
在上述具有第一电阻的第一导电类型的半导体衬底的背面上形成的漏电极,
上述具有第二电阻的半导体区包含第一导电类型的杂质或第二导电类型的杂质,且
上述具有第三电阻的第一导电类型的半导体区从上述具有第二电阻的半导体区的主面一直设置到上述具有第一电阻的第一导电类型的半导体衬底。
2.如权利要求1所述的半导体装置,其特征在于:
上述具有第二电阻的半导体区包含第一导电类型的杂质。
3.如权利要求1所述的半导体装置,其特征在于:
上述具有第二电阻的半导体区包含第二导电类型的杂质。
4.如权利要求1所述的半导体装置,其特征在于:
与上述具有第三电阻的第一导电类型的半导体区相接地形成有从上述具有第二电阻的半导体区的主面一直设置到上述具有第一电阻的第一导电类型的半导体衬底的沟槽,在上述沟槽内隔着绝缘体填充有导电体,上述导电体与上述源电极电连接。
5.如权利要求4所述的半导体装置,其特征在于:
上述导电体包含多晶硅或钨。
6.如权利要求4所述的半导体装置,其特征在于:
上述沟槽内的上述绝缘体包含二氧化硅或BST即(Ba,Sr)TiO3。
7.如权利要求4所述的半导体装置,其特征在于:
在沿着上述具有第一电阻的第一导电类型的半导体衬底的主面的方向上,断断续续地设置有把上述沟槽内的上述导电体与上述源电极电连接的接触孔。
8.一种半导体装置的制造方法,该半导体装置具有在具有第一电阻的第一导电类型的半导体衬底上形成的功率MOSFET,该制造方法包括:
(a)、准备上述具有第一电阻的第一导电类型的半导体衬底的工序;
(b)、在上述(a)工序之后,在上述具有第一电阻的第一导电类型的半导体衬底上形成具有比上述第一电阻高的第二电阻的半导体区的工序;
(c)、在上述(b)工序之后,通过各向异性蚀刻形成从上述具有第二电阻的半导体区的主面到达上述具有第一电阻的第一导电类型的半导体衬底的第一沟槽的工序;
(d)、在上述(c)工序之后,通过从相对于上述具有第二电阻的半导体区的主面垂直的方向倾斜的方向注入离子,在上述第一沟槽的侧壁上形成具有比上述第一电阻高的第三电阻的第一导电类型的半导体区的工序;
(e)、在上述(d)工序之后,在上述第一沟槽的表面上形成绝缘体的工序;
(f)、在上述(e)工序之后,用导电体填充上述第一沟槽内的工序;
(g)、在上述(b)工序之后,通过离子注入在上述具有第二电阻的半导体区的表面的一部分上形成具有第四电阻的第二导电类型的半导体区的工序;
(h)、在上述(g)工序之后,在上述具有第二电阻的半导体区的主面上隔着栅绝缘膜形成栅电极的工序;
(i)、在上述(h)工序之后,通过离子注入在上述具有第二电阻的半导体区的表面的一部分上形成具有比上述第三电阻低的第五电阻的第一导电类型的半导体区的工序;
(j)、在上述(i)工序之后,在上述具有第一电阻的第一导电类型的半导体衬底的主面上沉积绝缘膜的工序;
(k)、在上述(j)工序之后,贯通上述绝缘膜形成到达上述具有第五电阻的第一导电类型的半导体区的第一接触孔的工序;
(l)、在上述(k)工序之后,将形成了上述第一接触孔的上述绝缘膜作为掩模而在上述具有第二电阻的半导体区的主面上形成到达上述具有第四电阻的第二导电类型的半导体区的第二沟槽的工序;
(m)、在上述(l)工序之后,在上述第二沟槽的底部形成上述具有比第四电阻低的第六电阻的第二导电类型的半导体区的工序;
(n)、在上述(j)工序之后,贯通上述绝缘膜地形成到达填充了上述第一沟槽的导电体的第二接触孔的工序;
(o)、在上述(m)工序和(n)工序之后,在第一主表面上形成源电极的工序;以及
(p)、在第二主表面上形成漏电极的工序,
上述具有第二电阻的半导体区包含第一导电类型的杂质或第二导电类型的杂质,且
在上述(d)工序中,上述具有第三电阻的第一导电类型的半导体区从上述具有第二电阻的半导体区的主面一直设置到上述具有第一电阻的第一导电类型的半导体衬底。
9.如权利要求8所述的半导体装置的制造方法,其特征在于:
在上述(b)工序中形成上述具有第二电阻的半导体区时,向上述具有第二电阻的半导体区混入第一导电类型的杂质。
10.如权利要求8所述的半导体装置的制造方法,其特征在于:
在上述(b)工序中形成上述具有第二电阻的半导体区时,向上述具有第二电阻的半导体区混入第二导电类型的杂质。
11.如权利要求8所述的半导体装置的制造方法,其特征在于:
在上述(f)工序中,上述导电体包含多晶硅或钨而形成。
12.如权利要求8所述的半导体装置的制造方法,其特征在于:
在上述(e)工序中,上述第一沟槽内的上述绝缘体包含二氧化硅或BST即(Ba,Sr)TiO3而形成。
13.如权利要求8所述的半导体装置的制造方法,其特征在于:
在上述(n)工序中,在沿着上述具有第一电阻的第一导电类型的半导体衬底的主面的方向上,断断续续地设置上述第二接触孔。
14.一种电源装置,是向半导体装置供给电力的同步整流方式的电源装置,上述电源装置具有第一功率MOSFET和第二功率MOSFET,上述第一功率MOSFET和上述第二功率MOSFET中的至少一个具有:
在具有第一电阻的第一导电类型的半导体衬底的主面上形成的、具有比上述第一电阻高的第二电阻的半导体区;
在上述具有第二电阻的半导体区的表面的一部分上形成的、具有比上述第一电阻高的第三电阻的第一导电类型的半导体区;
在上述具有第二电阻的半导体区的表面的一部分上形成的第二导电类型的半导体区;
在上述第二导电类型的半导体区的表面的一部分上形成的、具有比上述第三电阻低的第四电阻的第一导电类型的半导体区;
在上述具有第二电阻的半导体区的主面上,隔着栅绝缘膜形成的栅电极;
在上述具有第二电阻的半导体区的主面上,与上述栅电极隔着绝缘膜形成,且与上述具有第四电阻的第一导电类型的半导体区电连接的源电极;以及
在上述具有第一电阻的第一导电类型的半导体衬底的背面上形成的漏电极,
上述具有第二电阻的半导体区包含第一导电类型的杂质或第二导电类型的杂质,且
上述具有第三电阻的第一导电类型的半导体区从上述具有第二电阻的半导体区的主面一直设置到上述具有第一电阻的第一导电类型的半导体衬底。
15.如权利要求14所述的电源装置,其特征在于:
上述具有第二电阻的半导体区包含第一导电类型的杂质。
16.如权利要求14所述的电源装置,其特征在于:
上述具有第二电阻的半导体区包含第二导电类型的杂质。
17.如权利要求14所述的电源装置,其特征在于:
与上述具有第三电阻的第一导电类型的半导体区相接地形成从上述具有第二电阻的半导体区的主面一直设置到上述具有第一电阻的第一导电类型的半导体衬底的沟槽,在上述沟槽内隔着绝缘体填充有导电体,上述导电体与上述源电极电连接。
18.如权利要求17所述的电源装置,其特征在于:
上述导电体包含多晶硅或钨。
19.如权利要求17所述的电源装置,其特征在于:
上述沟槽内的上述绝缘体包含二氧化硅或BST即(Ba,Sr)TiO3。
20.如权利要求17所述的电源装置,其特征在于:
在沿着上述具有第一电阻的第一导电类型的半导体衬底的主面的方向上,断断续续地设置把上述沟槽内的上述导电体与上述源电极电连接的接触孔。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009-149783 | 2009-06-24 | ||
JP2009149783A JP2011009352A (ja) | 2009-06-24 | 2009-06-24 | 半導体装置およびその製造方法ならびにそれを用いた電源装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101931005A CN101931005A (zh) | 2010-12-29 |
CN101931005B true CN101931005B (zh) | 2012-11-28 |
Family
ID=43370062
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2010101855348A Expired - Fee Related CN101931005B (zh) | 2009-06-24 | 2010-05-19 | 半导体装置及其制造方法和使用它的电源装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8664716B2 (zh) |
JP (1) | JP2011009352A (zh) |
CN (1) | CN101931005B (zh) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5218541B2 (ja) * | 2010-12-14 | 2013-06-26 | 株式会社デンソー | スイッチングモジュール |
JP2012178389A (ja) * | 2011-02-25 | 2012-09-13 | Renesas Electronics Corp | 半導体装置 |
US8796745B2 (en) * | 2011-07-05 | 2014-08-05 | Texas Instruments Incorporated | Monolithically integrated active snubber |
US9324838B2 (en) | 2013-01-11 | 2016-04-26 | Stmicroelectronics S.R.L. | LDMOS power semiconductor device and manufacturing method of the same |
US9450076B2 (en) | 2014-01-21 | 2016-09-20 | Stmicroelectronics S.R.L. | Power LDMOS semiconductor device with reduced on-resistance and manufacturing method thereof |
JP2015176889A (ja) * | 2014-03-13 | 2015-10-05 | 株式会社東芝 | 半導体装置 |
CN103928522B (zh) * | 2014-04-10 | 2016-04-27 | 电子科技大学 | 一种槽型积累层mosfet器件 |
DE102015200809A1 (de) | 2015-01-20 | 2016-07-21 | Robert Bosch Gmbh | Halbleiterbauelement mit Grabenstruktur |
DE102015221375A1 (de) | 2015-11-02 | 2017-05-04 | Robert Bosch Gmbh | Halbleiterbauelement sowie Verfahren zur Herstellung eines Halbleiterbauelements und Steuergerät für ein Fahrzeug |
CN106533163A (zh) * | 2016-01-22 | 2017-03-22 | 东莞市清能光伏科技有限公司 | 光伏功率转换器 |
US10381274B2 (en) * | 2016-02-09 | 2019-08-13 | Fuji Electric Co., Ltd. | Assessment method, and semiconductor device manufacturing method |
KR102593272B1 (ko) * | 2018-05-24 | 2023-10-23 | 엘지디스플레이 주식회사 | 표시 장치 |
CN108565289A (zh) * | 2018-06-26 | 2018-09-21 | 南京方旭智芯微电子科技有限公司 | 超结场效应管及超结场效应管的制造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1669151A (zh) * | 2003-06-05 | 2005-09-14 | 三菱电机株式会社 | 半导体器件及其制造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3185441B2 (ja) * | 1993-02-04 | 2001-07-09 | 株式会社日立製作所 | 高周波高出力電界効果トランジスタ |
JP3291957B2 (ja) * | 1995-02-17 | 2002-06-17 | 富士電機株式会社 | 縦型トレンチmisfetおよびその製造方法 |
US5847428A (en) * | 1996-12-06 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit gate conductor which uses layered spacers to produce a graded junction |
US6545316B1 (en) * | 2000-06-23 | 2003-04-08 | Silicon Wireless Corporation | MOSFET devices having linear transfer characteristics when operating in velocity saturation mode and methods of forming and operating same |
JP4124981B2 (ja) * | 2001-06-04 | 2008-07-23 | 株式会社ルネサステクノロジ | 電力用半導体装置および電源回路 |
TW563244B (en) * | 2002-10-25 | 2003-11-21 | Vanguard Int Semiconduct Corp | Deep trench isolation structure of high voltage device and its manufacturing method |
JP4945055B2 (ja) * | 2003-08-04 | 2012-06-06 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2008218711A (ja) * | 2007-03-05 | 2008-09-18 | Renesas Technology Corp | 半導体装置およびその製造方法、ならびに電源装置 |
US7851314B2 (en) * | 2008-04-30 | 2010-12-14 | Alpha And Omega Semiconductor Incorporated | Short channel lateral MOSFET and method |
US7893488B2 (en) * | 2008-08-20 | 2011-02-22 | Alpha & Omega Semiconductor, Inc. | Charged balanced devices with shielded gate trench |
US8552535B2 (en) * | 2008-11-14 | 2013-10-08 | Semiconductor Components Industries, Llc | Trench shielding structure for semiconductor device and method |
US7829947B2 (en) * | 2009-03-17 | 2010-11-09 | Alpha & Omega Semiconductor Incorporated | Bottom-drain LDMOS power MOSFET structure having a top drain strap |
US8174070B2 (en) * | 2009-12-02 | 2012-05-08 | Alpha And Omega Semiconductor Incorporated | Dual channel trench LDMOS transistors and BCD process with deep trench isolation |
-
2009
- 2009-06-24 JP JP2009149783A patent/JP2011009352A/ja active Pending
-
2010
- 2010-05-19 CN CN2010101855348A patent/CN101931005B/zh not_active Expired - Fee Related
- 2010-06-18 US US12/818,485 patent/US8664716B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1669151A (zh) * | 2003-06-05 | 2005-09-14 | 三菱电机株式会社 | 半导体器件及其制造方法 |
Non-Patent Citations (3)
Title |
---|
JP特开2002-368121A 2002.12.20 |
JP特开2005-57050A 2005.03.03 |
JP特开平6-232396A 1994.08.19 |
Also Published As
Publication number | Publication date |
---|---|
CN101931005A (zh) | 2010-12-29 |
US20100327348A1 (en) | 2010-12-30 |
JP2011009352A (ja) | 2011-01-13 |
US8664716B2 (en) | 2014-03-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101931005B (zh) | 半导体装置及其制造方法和使用它的电源装置 | |
CN102779836B (zh) | 使用高介电常数槽结构的低比导通电阻的纵向功率器件 | |
US9571087B2 (en) | Method of operating a reverse conducting IGBT | |
CN108257953A (zh) | 具有igbt区和不可切换二极管区的半导体器件 | |
CN101950759A (zh) | 一种Super Junction VDMOS器件 | |
JP5872281B2 (ja) | ダイオードを含む半導体装置 | |
CN103733344A (zh) | 半导体装置 | |
CN102420251A (zh) | 一种具有非均匀浮岛结构的vdmos器件 | |
CN103441148A (zh) | 一种集成肖特基二极管的槽栅vdmos器件 | |
CN103579313A (zh) | 提高高压ldmos器件击穿电压的结构 | |
CN103035692A (zh) | 半导体装置 | |
CN108198857A (zh) | 一种集成凸块状肖特基二极管的碳化硅mosfet器件元胞结构 | |
CN103280457A (zh) | 一种超低比导通电阻的横向高压功率器件及制造方法 | |
CN107611179A (zh) | 降低栅源电容的屏蔽栅mosfet结构及其制备方法 | |
CN103579309A (zh) | 在沟槽中包括电介质结构的半导体器件 | |
CN110061057A (zh) | 一种具有集成隧穿二极管的超结功率mosfet | |
CN106158927A (zh) | 一种优化开关特性的超结半导体器件及制造方法 | |
CN103022123A (zh) | 超级结半导体器件及其制造方法 | |
CN108666368A (zh) | 一种超结mosfet渐变终端结构及其制作方法 | |
CN105977295A (zh) | 半导体装置 | |
CN205376537U (zh) | 改善反向恢复特性及雪崩能力的超结mos器件 | |
CN102867844A (zh) | 一种p型纵向高耐压的横向双扩散金属氧化物半导体晶体管 | |
CN112002751A (zh) | 碳化硅vdmosfet器件的元胞结构、其制备方法及碳化硅vdmosfet器件 | |
CN114667609A (zh) | 垂直场效应晶体管和用于构造其的方法 | |
CN113410299A (zh) | 一种高耐压的n沟道LDMOS器件及其制备方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121128 Termination date: 20140519 |