CN108573937B - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN108573937B
CN108573937B CN201810182489.7A CN201810182489A CN108573937B CN 108573937 B CN108573937 B CN 108573937B CN 201810182489 A CN201810182489 A CN 201810182489A CN 108573937 B CN108573937 B CN 108573937B
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solder
metal plate
heat sink
thickness
semiconductor element
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CN108573937A (zh
Inventor
高萩智
舟野祥
门口卓矢
花木裕治
岩崎真悟
川岛崇功
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Denso Corp
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Denso Corp
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Abstract

本说明书公开一种半导体装置，具备：第一及第二半导体元件，在两个面具备电极；第一及第二金属板，夹着第一半导体元件，通过第一焊料与第一半导体元件的各电极接合；及第三及第四金属板，夹着第二半导体元件，通过第二焊料与第二半导体元件的各电极接合。该半导体装置中，从第一金属板延伸出第一接头并且从第四金属板延伸出第二接头，这些接头由第三焊料接合，第一焊料的凝固点比第三焊料的凝固点高，且第二焊料的凝固点比第三焊料的凝固点高。

Description

半导体装置
技术领域
本说明书公开的技术涉及半导体装置。尤其是，涉及具备将两个半导体元件密封的树脂封装，并且半导体元件的电极通过焊料接合于在该树脂封装的两个面露出的金属板的半导体装置。
背景技术
已知有具备将两个半导体元件密封的树脂封装，并且作为散热板的金属板在该树脂封装的两个面露出的半导体装置。金属板与树脂封装的内部的半导体元件的电极导通。即，金属板兼作为散热板和电极。例如，在日本特开2015-170810号公报及日本特开2012-235081号公报中公开了这样的半导体装置。半导体元件在其两个面具备电极。一对金属板将半导体元件夹入，一对金属板分别通过焊料接合于各电极。此外，“电极与金属板由焊料接合”包括电极与分隔件由焊料接合，且在该分隔件的相反侧通过焊料接合有金属板的情况。两个半导体元件由树脂封装密封。一对金属板各自的一个面从树脂封装露出，起到散热板的作用。为了方便说明，将两个半导体元件分别称作第一半导体元件和第二半导体元件。将夹入第一半导体元件的一对金属板称作第一及第二金属板，将夹入第二半导体元件的一对金属板称作第三及第四金属板。第一金属板和第三金属板在树脂封装的一个面露出，第二金属板和第四金属板在相反侧的面露出。为了将两个半导体元件电连接，从第一金属板的缘部延伸出第一接头，从在与第一金属板相反的一侧从树脂封装露出的第四金属板的缘部延伸出第二接头，两个接头在树脂封装的内部由焊料接合。
发明内容
在上述的半导体装置中，在第一及第二金属板之间存在焊料，并且在第三及第四金属板之间也存在焊料。从在树脂封装的两个面分别露出的第一及第四金属板的缘部延伸出接头，它们由焊料接合。焊料在凝固时收缩。在第一及第二金属板之间焊料收缩，第三及第四金属板之间的焊料也收缩。若接头间的焊料先于金属板间的焊料而凝固，则会由于金属板的缘部受到束缚而导致在金属板间的焊料收缩时金属板倾斜。期望有一种抑制与焊料在凝固时的收缩相伴的金属板的倾斜的技术。
本说明书公开的半导体装置具备：第一半导体元件及第二半导体元件，在两个面具备电极；第一及第二金属板，夹着第一半导体元件，通过第一焊料与第一半导体元件的各电极接合；第三及第四金属板，夹着第二半导体元件，通过第二焊料与第二半导体元件的各电极接合；及树脂封装，将第一半导体元件和第二半导体元件密封，第一金属板和第三金属板在该树脂封装的一个面露出，并且第二金属板和第四金属板在该树脂封装的相反面露出。该半导体装置中，从第一金属板的缘部延伸出第一接头并且从第四金属板的缘部延伸出第二接头，第一接头与所述第二接头在从第一金属板与第一半导体元件的层叠方向观察时重叠，并且由第三焊料接合，第一焊料的凝固点比第三焊料的凝固点高，且第二焊料的凝固点比第三焊料的凝固点高。
根据上述的凝固点的关系，当将所有焊料加热之后冷却时，凝固点高的焊料(第一焊料和第二焊料)比凝固点低的焊料(第三焊料)先凝固。即，当满足上述的凝固点的关系时，在接头间的焊料(第三焊料)凝固之前，金属板间的焊料(第一焊料和第二焊料)凝固。由于在第一金属板和第四金属板的缘部自由的期间金属板与半导体元件接合，所以金属板不会倾斜。
若假设第三焊料的厚度相当薄，则由于金属板间的焊料(第一焊料或第二焊料)凝固时的收缩，第一接头与第二接头可能会干涉。若在金属板间的焊料收缩的中途第一、第二接头干涉，则金属板的接头侧的缘部会受到束缚，金属板仍有可能倾斜。
因此，优选，第一金属板与第二金属板之间的第一焊料的合计厚度在凝固时的推定收缩量为第三焊料的厚度以下，第三金属板与第四金属板之间的第二焊料的合计厚度在凝固时的推定收缩量为第三焊料的厚度以下。在此，推定收缩量是指在具有规定的合计厚度的第一焊料(第二焊料)凝固时设想的缩小量(厚度方向的缩小量)。若焊料的材料和初始厚度已知，则能够通过实验等确定推定收缩量。若第三焊料的厚度比第一焊料的推定收缩量大且比第二焊料的推定收缩量大，则即使在第一焊料和第二焊料的收缩时金属板间的间隔变窄，接头彼此也不会干涉。由此，能够防止金属板倾斜的情况。
为了更可靠地防止由接头的干涉引起的金属板的倾斜，优选，第一金属板与第二金属板之间的第一焊料的合计厚度为第三焊料的厚度以下，第三金属板与第四金属板之间的第二焊料的合计厚度为第三焊料的厚度以下。若满足上述的厚度的关系，则即使金属板间的焊料收缩，也能可靠地避免接头彼此的干涉。
本说明书公开的技术的详情及进一步的改良将在以下的“具体实施方式”中进行说明。
附图说明
图1是半导体装置的立体图。
图2是半导体装置的等效电路图。
图3是半导体装置的分解图(1)。
图4是半导体装置的分解图(2)。
图5是半导体元件和散热板的组件的立体图。
图6是沿着图1的VI-VI线的剖视图。
图7是图6中标号VII所示的范围的放大图。
图8是示出对散热板和半导体元件的组件进行加热/冷却的炉的温度曲线的一例的坐标图。
图9是变形例的半导体装置的局部剖视图。
具体实施方式
参照附图对实施例的半导体装置2进行说明。图1中示出半导体装置2的立体图。半导体装置2是在树脂制的封装(树脂封装9)中封固有四个半导体元件的器件。将半导体装置2的等效电路图示于图2。半导体装置2具有由两个晶体管103、105和两个二极管104、106构成的电路。两个晶体管103、105和两个二极管104、106都属于在电力变换中使用的功率半导体元件。具体地说，晶体管103、105和二极管104、106分别是容许电流为100安培以上且主要在电力变换中使用的元件。半导体装置2典型地在电动汽车、混合动力车、燃料电池车等中使用于产生向行驶用电动机供给的交流电力的变换器。
两个晶体管103、105串联连接。二极管104反并联地连接于晶体管103，二极管106反并联地连接于于晶体管105。为了便于说明，将串联连接的两端的端子中的连接于高电位侧的端子称作HIGH端子，将连接于低电位侧的端子称作LOW端子。另外，将串联连接的中点称作OUT端子。图1的P端子24相当于HIGH端子，图1的N端子34相当于LOW端子，图1的O端子14相当于OUT端子。另外，晶体管105的栅极端子GH相当于图1的控制端子81a中的一根。晶体管103的栅极端子GL相当于图1的控制端子81b中的一根。控制端子81a、81b的剩余的端子是用于监视半导体元件的状态的信号端子等。
如图1所示，在树脂封装9的一个侧面露出了散热板15、25。散热板15的一个面露出到树脂封装9的一个侧面，另一个面在树脂封装9的内部与后述的第一晶体管元件3及第一二极管元件4接合。散热板25的一个面露出到树脂封装9的一个侧面，另一个面在树脂封装9的内部与后述的第二晶体管元件5及第二二极管元件6接合。虽然在图1中被遮挡而看不到，但在树脂封装9的另一个侧面也露出了两个散热板12、22。散热板12、15、22、25由导电性的金属制成。更具体地说，散热板12、15、22、25由铜制成。以下，在对四张散热板进行区分的情况下，有时称作第一散热板12、第二散热板15、第三散热板22、第四散热板25。
图3是除去树脂封装9和散热板15、25的半导体装置2的分解图。图4是将散热板15、25分离后的立体图。图5是除去树脂封装9的半导体装置2(即，散热板和半导体元件的组件2a)的立体图。此外，在图3-图5中，N端子34、P端子24、O端子14和控制端子81a、81b由流道(runner)42a、42b连结，构成了一个部件(引线框架42)。当在图5的组件2a形成树脂封装9之后将流道42a、42b切除后，图1的半导体装置2完成。为了便于说明，将图中的坐标系的X轴正方向称作“上”，将X轴负方向称作“下”。在以后的图中有时也使用“上”、“下”的表述。
两张散热板(第一散热板12和第三散热板22)位于最下侧。从第一散热板12的一个缘部延伸出O端子14，从另外的缘部延伸出第一接头13。从第三散热板22的一个缘部延伸出P端子24。在O端子14与P端子24之间配置有N端子34。从N端子34的缘部延伸出接头32。如先前描述那样，N端子34、P端子24(第三散热板22)及O端子14(第一散热板12)在最初的阶段与控制端子81a、81b一起由流道42a、42b连结，相互的位置关系固定。
在第一散热板12上层叠第一晶体管元件3，并利用焊料(未图示)接合。另外，在第一散热板12上层叠第一二极管元件4，并利用焊料(未图示)接合。此外，第一晶体管元件3是平板型，在两个面分别具备电极。在第一晶体管元件3的下表面具备集电极3a(参照后述的图6)，在上表面具备发射极3b。另外，在第一晶体管元件3的上表面具备包括栅电极的信号端子3d。在第一二极管元件4的下表面具备阴电极，在上表面具备阳电极4b。第一散热板12将第一晶体管元件3的集电极3a与第一二极管元件4的阴电极连接。在第一晶体管元件3的上表面的发射极3b上经由焊料(未图示)而接合分隔件7a。在第一二极管元件4的上表面的阳电极4b上经由焊料(未图示)而接合分隔件7b。在分隔件7a和分隔件7b上(参照图4)经由焊料(未图示)而接合第二散热板15。第二散热板15将第一晶体管元件3的发射极3b与第一二极管元件4的阳电极4b连接。第一晶体管元件3的上表面的包括栅电极的信号端子3d与键合线82的一端接合(参照图4)。键合线82的另一端接合于控制端子81b。
在第三散热板22上层叠第二晶体管元件5，并利用焊料(未图示)接合。另外，在第三散热板22上层叠第二二极管元件6，并利用焊料(未图示)接合。第二晶体管元件5也是平板型，在两个面分别具备电极。在第二晶体管元件5的下表面具备集电极5a(参照后述的图6)，在上表面具备发射极5b。另外，在第二晶体管元件5的上表面具备包括栅电极的信号端子5d。在第二二极管元件6的下表面具备阴电极，在上表面具备阳电极6b。第三散热板22将第二晶体管元件5的集电极5a与第二二极管元件6的阴电极连接。在第二晶体管元件5的上表面的发射极5b上经由焊料(未图示)而接合分隔件7c。在第二二极管元件6的上表面的阳电极6b上经由焊料(未图示)而接合分隔件7d。在分隔件7c和分隔件7d上(参照图4)经由焊料(未图示)而接合第四散热板25。第四散热板25将第二晶体管元件5的发射极5b与第二二极管元件6的阳电极6b连接。第二晶体管元件5的上表面的包括栅电极的信号端子5d与键合线82的一端接合。键合线82的另一端接合于控制端子81a。
从第二散热板15的缘部延伸出接头16。从第四散热板25的缘部延伸出第二接头26。第二散热板15的接头16与N端子34的接头32对向，并利用焊料(未图示)接合。第四散热板25的第二接头26与第一散热板12的第一接头13对向，并利用焊料接合。此外，第一接头13与第二接头26在从第一散热板12、第一晶体管元件3及第二散热板15的层叠方向(图中的X方向)观察时重叠，焊料将它们相连。通过以上的连接，图2所示的电路完成。第一晶体管元件3对应于图2的晶体管103，第二晶体管元件5对应于图2的晶体管105。第一二极管元件4对应于图2的二极管104，第二二极管元件6对应于图2的二极管106。
在图5的组件2a的周围形成树脂封装9。树脂封装9通过将组件2a放入模具并向模具的内部注射熔融树脂而制成。即，树脂封装9通过树脂的注射成形而制成。树脂封装9将第一晶体管元件3、第二晶体管元件5、第一二极管元件4及第二二极管元件6封固。第一散热板12和第三散热板22在树脂封装9的一个面露出，第二散热板15和第四散热板25在相反侧的面露出。
如先前描述那样，第一晶体管元件3等半导体元件、散热板12、15、22、25及分隔件7a-7d由焊料接合。在图3-图5中，省略了焊料的图示。以下，参照图6，对第一晶体管元件3等半导体元件、散热板12、15、22、25、分隔件7a-7d及将它们接合的焊料进行说明。
图6是沿着图1的VI-VI线的剖视图。如先前描述那样，在第一晶体管元件3的下表面具备集电极3a，在上表面具备发射极3b。第一散热板12与第一晶体管元件3的集电极3a由焊料18a接合。第一晶体管元件3的发射极3b与分隔件7a由焊料18b接合。分隔件7a与第二散热板15由焊料18c接合。第二散热板15通过焊料18b、18c和分隔件7a而与第一晶体管元件3接合。第一散热板12与第二散热板15将第一晶体管元件3夹入，它们通过焊料18a、18b、18c和分隔件7a而与第一晶体管元件3的电极接合。以下，为了便于说明，将存在于对向的第一散热板12与第二散热板15之间的焊料18a、18b、18c统称作第一焊料18。
在第一散热板12与第二散热板15之间也夹着分隔件7b和第一二极管元件4(参照图3-图5)。第一二极管元件4与第一散热板12由与焊料18a相同材质且相同厚度的焊料接合。第一二极管元件4与分隔件7b由与焊料18b相同材质且相同厚度的焊料接合。分隔件7b与第二散热板15由与焊料18c相同材质且相同厚度的焊料接合。
在第二晶体管元件5的下表面具备集电极5a，在上表面具备发射极5b。第三散热板22与第二晶体管元件5的集电极5a由焊料28a接合。第二晶体管元件5的发射极5b与分隔件7c由焊料28b接合。分隔件7c与第四散热板25由焊料28c接合。第四散热板25通过焊料28b、28c和分隔件7c而与第二晶体管元件5的电极接合。第三散热板22与第四散热板25将第二晶体管元件5夹入，它们通过焊料28a、28b、28c和分隔件7c而与第二晶体管元件5的电极接合。以下，为了便于说明，将存在于对向的第三散热板22与第四散热板25之间的焊料28a、28b、28c统称作第二焊料28。
在第三散热板22与第四散热板25之间也夹着分隔件7d和第二二极管元件6(参照图3-图5)。第二二极管元件6与第三散热板22由与焊料28a相同材质且相同厚度的焊料接合。第二二极管元件6与分隔件7d由与焊料28b相同材质且相同厚度的焊料接合。分隔件7d与第四散热板25由与焊料28c相同材质且相同厚度的焊料接合。
从第一散热板12的缘部延伸出第一接头13，从第四散热板25的缘部延伸出第二接头26。第一接头13与第二接头26在从第一散热板12的法线方向(图中的X方向)观察时重叠，两者由焊料38接合。为了将焊料38与第一焊料18、第二焊料28进行区分，将其称作第三焊料38。
将图6中标号VII所示的范围的放大图示于图7。标号W1a、W1b、W1c分别表示焊料18a、18b、18c的厚度。第一散热板12与第二散热板15之间的第一焊料18的合计厚度W1为W1＝W1a+W1b+W1c。标号W2a、W2b、W2c分别表示焊料28a、28b、28c的厚度。第三散热板22与第四散热板25之间的第二焊料28的合计厚度W2为W2＝W2a+W2b+W2c。标号W3表示第三焊料38的厚度。第三焊料38的厚度W3比第一焊料18的合计厚度W1大，且比第二焊料28的合计厚度W2大。另外，第三焊料38使用了与第一焊料18及第二焊料28不同的材料。第一焊料18的凝固点T1比第三焊料38的凝固点T3高。第二焊料28的凝固点T2比第三焊料38的凝固点T3高。在图7中，利用密度比凝固点低的第三焊料38高的点状阴影来表示凝固点高的第一焊料18和第二焊料28。例如，第一焊料18、第二焊料28使用Sn-0.7Cu的焊料材料。其凝固点为227[℃]。另外，第三焊料38例如使用Sn-3.0Ag-0.5Cu的焊料材料。其凝固点为217[℃]。上述的厚度与凝固点的关系带来以下优点。
焊料在凝固时收缩。厚度越大，则厚度方向的收缩量越大。在图7的构造的情况下，第三焊料38的厚度W3比第一焊料18的厚度W1和第二焊料28的厚度W2大。若假设第一焊料18、第二焊料28、第三焊料38具有相同的凝固点，则焊料18、28、38在冷却时同时开始收缩。这样一来，由于厚度大的第三焊料38的收缩，第一接头13与第二接头26会接近，第一散热板12和第四散热板25会倾斜。但是，在实施例的半导体装置2中，厚度小的第一焊料18和第二焊料28比厚度大的第三焊料先凝固。即，在第一接头13因与第二接头26的接合而受到束缚之前，第一焊料18(即，对向的第一及第二散热板12、15之间的焊料)凝固。同样，在第二接头26因与第一接头13的接合而受到束缚之前，第二焊料28(即，对向的第三及第四散热板22、25之间的焊料)凝固。由此，对向的第一及第二散热板12、15在保持平行的状态下被接合。同样，对向的第三及第四散热板22、25在保持平行的状态下被接合。
半导体装置2中的焊料的厚度与凝固点的关系还带来以下优点。若假设厚度大的接头间的第三焊料38先发生收缩凝固，则对向的第一及第二散热板12、15的间隔及对向的第三及第四散热板22、25的间隔会变窄。这样一来，厚度本来就小的第一焊料18和第二焊料28会在伴随于接头间的接合而变薄之后开始收缩凝固。其结果，接合后的厚度会进一步变小。但是，在实施例的半导体装置2中，由于厚度小的第一焊料18、第二焊料28比厚度大的第三焊料38先发生收缩凝固，所以接合后的厚度不足的情况得以避免。
对能够从上述的焊料的厚度与凝固点的关系中获得的其他优点进行叙述。当第一焊料18和第二焊料28先于第三焊料38的凝固而发生收缩凝固时，第一及第二散热板12、15的间隔变窄。另外，第三及第四散热板22、25的间隔也变窄。若假设第三焊料38的厚度薄，则在散热板的间隔变窄时，第一接头13与第二接头26之间也会变窄，两接头可能会干涉。若两接头干涉，则第一散热板12的接头侧的缘部与第四散热板25的接头侧的缘部的间隔会受到束缚。若在该状态下第一焊料18、第二焊料28进一步收缩，则散热板可能会倾斜。通过使第三焊料38的厚度W3比第一焊料18的合计厚度W1大且比第二焊料28的合计厚度W2大，能够防止由接头彼此的干涉引起的金属板的倾斜。
如先前所叙述那样，二极管元件、散热板及分隔件之间的焊料不管是材料还是厚度都与晶体管元件、散热板及分隔件之间的对应的焊料相同，因此，上述的说明即使将接合二极管元件的焊料纳入考虑也是成立的。
在图6、图7中，为了帮助理解而将焊料的厚度描绘得比实际厚。焊料的厚度在50微米-500微米左右的范围内设定。
接着，对半导体装置2的制造方法进行说明。在此，从将图5的组件2a(即，使树脂封装9成形之前的半导体装置2的半成品)放入炉内而使焊料熔融/凝固的工序起进行说明。此外，在组件2a中，在散热板、半导体元件及分隔件之间配置有熔融前的焊料。
在图8中示出放入组件2a的炉的温度曲线。图8的横轴为时间，纵轴为炉内温度。温度T1为第一焊料18的凝固点(熔融温度)，温度T2为第二焊料28的凝固点(熔融温度)。温度T3为第三焊料38的凝固点(熔融温度)。在此，为了容易进行说明，假定凝固点与熔融温度相等。
首先，使炉内温度升温至比第一焊料18、第二焊料28的凝固点(熔融温度)T1、T2高的温度TH。通过在一定时间的期间将炉内温度维持为温度TH，所有焊料熔融。接着，逐渐降低炉内温度。在时刻t1，炉内温度降低至第一、第二焊料18、28的凝固点T1、T2，在时刻t2，炉内温度降低至第三焊料38的凝固点T3。在时刻t1至t2的期间，第一焊料18和第二焊料28凝固。此时，第三焊料38仍为熔融状态。
在到达时刻t2时，第一焊料18和第二焊料28处于凝固状态。第三焊料38在时刻t2以后凝固。这样，在厚度小的第一焊料18和第二焊料28凝固之后，第三焊料38凝固。如先前所叙述那样，通过使厚度小的第一焊料18和第二焊料28比厚度大的第三焊料38先凝固，第一散热板12与第二散热板15在维持平行的状态下被接合。从另外的观点来说明，由于在接头间的焊料(第三焊料38)凝固之前散热板间的焊料(第一焊料18、第二焊料28)凝固，所以在接头侧的缘部受到束缚之前第一散热板12与第二散热板15在维持平行的状态下被接合。第三散热板22与第四散热板25也同样在维持平行的状态下被接合。
在所有焊料凝固之后，将组件2a从炉移向注射成形的模具，使树脂封装9成形。接着，对第一散热板12和第三散热板22露出的面进行研磨，使第一散热板12、第三散热板22及树脂封装9的面共面。同样，对第二散热板15和第四散热板25露出的面进行研磨，使第二散热板15、第四散热板25及树脂封装9的相反侧的面共面。此时，由于散热板没有倾斜，所以能够以低成本完成直到树脂封装9的表面与散热板成为共面为止的研磨。
在如上述那样制造半导体装置2时，无需使对向的散热板之间的焊料(第一焊料18、第二焊料28)与接头之间的焊料(第三焊料38)分别加热/冷却。在制造半导体装置2的情况下，将第一-第四散热板12、15、22、25和半导体元件(晶体管元件3、5、二极管元件4、6)的组件放入炉并使组件升温至比所有焊料的融点高的温度之后，使组件的温度降低至比所有焊料的凝固点低的温度即可。这样，厚度薄的一方的焊料(凝固点高的焊料)比另一方的焊料(凝固点低的焊料)先凝固。
(变形例)
接着，参照图9对变形例的半导体装置302进行说明。图9是变形例的半导体装置302的局部剖视图。以下，为了使说明简单，将晶体管元件的电极与散热板接合表述成晶体管元件与散热板接合。另外，假设二极管元件与散热板之间的焊料是与对应的晶体管元件与散热板之间的焊料相同的材料和相同的厚度。因此，关于二极管元件与其两侧的散热板之间的焊料，省略说明。
在该变形例中，第一接头313与第二接头26的间隔比先前的实施例的情况窄。除此以外，与先前的实施例的构造相同。在图9中，对与图7所示的实施例的部件相同的部件标注了相同的标号。在该变形例中，第一焊料18和第二焊料28的凝固点也比第三焊料338的凝固点高。为了表示这一点，在图9中，也利用密度比凝固点低的第三焊料338高的点状阴影来表示凝固点高的第一焊料18和第二焊料28。
在该变形例中，第三焊料338的厚度W33比第一焊料18的合计厚度W1(＝W1a+W1b+W1c)小，且比第二焊料28的合计厚度W2(＝W2a+W2b+W2c)小。不过，第三焊料338的厚度比第一焊料18的合计厚度W1的推定收缩量大，且比第二焊料28的合计厚度W2的推定收缩量大。在此，推定收缩量是指在合计厚度W1的第一焊料18(合计厚度W2的第二焊料28)发生收缩凝固时设想的缩小量(厚度方向的缩小量)。若焊料的材料和初始厚度已知，则能够通过实验来对推定收缩量进行推定。若第三焊料338的厚度W33比第一焊料18的推定收缩量和第二焊料28的推定收缩量大，则即使在第一焊料18和第二焊料28的收缩凝固时金属板间的间隔变窄，接头彼此也不会干涉，金属板不会倾斜。
在该变形例中，例如，W1a＝W1b＝W1c＝W2a＝W2c＝W3c＝W33/2。并且，假设第一焊料18的合计厚度W1(＝W1a+W1b+W1c)的推定收缩量为厚度W1的10％。另外，假设第二焊料28的合计厚度W2(＝W2a+W2b+W2c)的推定收缩量为厚度W2的10％。此时，若第三焊料338的厚度W33为[W1a×2]，则即使第一焊料18和第二焊料收缩，第一接头313与第二接头26也不会干涉。因此，能够防止在焊料的收缩时散热板倾斜的情况。
对与实施例中说明的技术相关的留意点进行叙述。实施例的半导体装置2、302在一对散热板12、15(22、25)之间夹着晶体管元件和二极管元件。近年来，开发出了将晶体管和二极管的反并联电路单芯片化的半导体元件。这样的半导体元件的一例被称作RC-IGBT。在采用了晶体管元件和二极管被单芯片化的半导体元件的情况下，散热板与半导体元件的电极的接合面积与接头彼此的接合面积之差变小。若散热板与半导体元件的电极的接合面积与接头彼此的接合面积之差变小，则接头彼此的接合给散热板的倾斜带来的影响会变得显著。本说明书公开的技术在一对散热板之间夹着一个小型半导体元件的半导体装置中尤其有效。另外，如图3-图7中所示，通过使接头之间的焊料(第三焊料38)的厚度比散热板之间的焊料(第一焊料18和第二焊料28)的厚度大，能够对散热板的倾斜防止期待最高的效果。
实施例的第一晶体管元件3和第一二极管元件4相当于第一半导体元件的一例。实施例的第二晶体管元件5和第二二极管元件6相当于第二半导体元件的一例。第一散热板12、第二散热板15、第三散热板22及第四散热板25分别相当于第一金属板、第二金属板、第三金属板及第四金属板的一例。
以上，虽然对本发明的具体例进行了详细说明，但这些只不过是例示，不对权利要求书构成限定。在权利要求书中记载的技术中，包括将以上所例示的具体例进行各种变形、变更而得到的技术方案。本说明书或附图中所说明的技术要素以单独或各种组合的方式发挥技术有用性，不限定于申请时权利要求所记载的组合。另外，本说明书或附图中所例示的技术能够同时实现多个目的，实现其中一个目的本身就具有技术有用性。

Claims (1)

1.一种半导体装置，具备：
第一半导体元件及第二半导体元件，在两个面具备电极；
第一及第二金属板，夹着所述第一半导体元件，通过第一焊料与所述第一半导体元件的各所述电极接合；
第三及第四金属板，夹着所述第二半导体元件，通过第二焊料与所述第二半导体元件的各所述电极接合；及
树脂封装，将所述第一半导体元件和所述第二半导体元件密封，所述第一金属板和所述第三金属板在该树脂封装的一个面露出，并且所述第二金属板和所述第四金属板在该树脂封装的相反面露出，
从所述第一金属板的缘部延伸出第一接头并且从所述第四金属板的缘部延伸出第二接头，所述第一接头与所述第二接头在从所述第一金属板与所述第一半导体元件的层叠方向观察时重叠，并且由第三焊料接合，
所述第一焊料的凝固点比所述第三焊料的凝固点高，且所述第二焊料的凝固点比所述第三焊料的凝固点高，
在所述第一金属板与所述第二金属板之间的所述第一焊料的合计厚度为所述第三焊料的厚度以上，且所述第三金属板与所述第四金属板之间的所述第二焊料的合计厚度为所述第三焊料的厚度以上的情况下，
所述第一金属板与所述第二金属板之间的所述第一焊料的合计厚度在凝固时的推定收缩量为所述第三焊料的厚度以下，
所述第三金属板与所述第四金属板之间的所述第二焊料的合计厚度在凝固时的推定收缩量为所述第三焊料的厚度以下。
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Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
JP6512231B2 (ja) * 2017-01-27 2019-05-15 トヨタ自動車株式会社 半導体装置
JP7043225B2 (ja) * 2017-11-08 2022-03-29 株式会社東芝 半導体装置
JP7155990B2 (ja) * 2018-12-17 2022-10-19 株式会社デンソー 半導体モジュール
DE102020206464A1 (de) 2020-05-25 2021-11-25 Zf Friedrichshafen Ag Verfahren zur Herstellung eines Halbbrückenmoduls, eines Inverters, Halbbrückenmodul und Inverter

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102473655A (zh) * 2009-07-17 2012-05-23 住友电木株式会社 电子部件的制造方法及电子部件
CN105518857A (zh) * 2013-09-06 2016-04-20 丰田自动车株式会社 半导体装置、以及半导体装置的制造方法
CN105575937A (zh) * 2014-11-04 2016-05-11 丰田自动车株式会社 半导体装置和用于半导体装置的制造方法
CN108428685A (zh) * 2017-01-27 2018-08-21 丰田自动车株式会社 半导体装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3614079B2 (ja) * 2000-03-24 2005-01-26 株式会社デンソー 半導体装置及びその製造方法
JP4085563B2 (ja) * 2000-08-24 2008-05-14 富士電機ホールディングス株式会社 パワー半導体モジュールの製造方法
JP4302607B2 (ja) * 2004-01-30 2009-07-29 株式会社デンソー 半導体装置
JP2005286121A (ja) * 2004-03-30 2005-10-13 Toshiba Corp 半導体装置及びその製造方法
JP4730181B2 (ja) * 2006-04-10 2011-07-20 株式会社デンソー 半導体装置
JP5947537B2 (ja) 2011-04-19 2016-07-06 トヨタ自動車株式会社 半導体装置及びその製造方法
EP2824696B1 (en) * 2012-03-07 2021-05-05 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacture thereof
JP5966979B2 (ja) * 2013-03-14 2016-08-10 株式会社デンソー 半導体装置及びその製造方法
JP6114149B2 (ja) 2013-09-05 2017-04-12 トヨタ自動車株式会社 半導体装置
JP2015056641A (ja) * 2013-09-13 2015-03-23 株式会社東芝 半導体装置及びその製造方法
JP6221542B2 (ja) * 2013-09-16 2017-11-01 株式会社デンソー 半導体装置
JP6154342B2 (ja) * 2013-12-06 2017-06-28 トヨタ自動車株式会社 半導体装置
JP6125984B2 (ja) * 2013-12-11 2017-05-10 トヨタ自動車株式会社 半導体装置
JP6294110B2 (ja) 2014-03-10 2018-03-14 トヨタ自動車株式会社 半導体装置
JP6578900B2 (ja) * 2014-12-10 2019-09-25 株式会社デンソー 半導体装置及びその製造方法
JP6394489B2 (ja) * 2015-05-11 2018-09-26 株式会社デンソー 半導体装置
JP2017107907A (ja) 2015-12-07 2017-06-15 トヨタ自動車株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102473655A (zh) * 2009-07-17 2012-05-23 住友电木株式会社 电子部件的制造方法及电子部件
CN105518857A (zh) * 2013-09-06 2016-04-20 丰田自动车株式会社 半导体装置、以及半导体装置的制造方法
CN105575937A (zh) * 2014-11-04 2016-05-11 丰田自动车株式会社 半导体装置和用于半导体装置的制造方法
CN108428685A (zh) * 2017-01-27 2018-08-21 丰田自动车株式会社 半导体装置

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