CN108519857A - Multi-source unformatted wideband data high speed magnanimity formats storage and feature security method - Google Patents
Multi-source unformatted wideband data high speed magnanimity formats storage and feature security method Download PDFInfo
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- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/202—Non-volatile memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/21—Employing a record carrier using a specific recording technology
- G06F2212/214—Solid state disk
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Abstract
For aerospace field unmanned plane, the weapons such as stratospheric airship and civilian equipment are being developed, production, demand in experiment and maintenance process to universal data storage device, by using high-speed multiple channel SRIO optical fiber interface transmitting technologies, wideband data high speed great capacity data storage, complicated Clock management technology, multi-source nonformatted data formats recording technique, overall process signal characteristic saves technology from damage, record support and access technique simultaneously, miniaturization technology etc., effective Solving Multichannel high-speed serial data transmitting, the technical barriers such as multi-source data high speed magnanimity reliable memory, it has invented multi-source unformatted wideband data high speed magnanimity and has formatted storage and feature security method.It can be applied in development, production, experiment and the maintenance process of the equipments such as aerospace field unmanned plane, stratospheric airship, effectively realize the high speed mass memory of multi-source data, critical data support is provided for the performance evaluation of associated equipment, to realize the performance test and evaluation to equipment.
Description
Technical field
The present invention relates to Visible Light Camera in the weapons such as aerospace field unmanned plane, stratospheric airship and civilian equipment,
Wideband data acquisition, high speed transmitting and the magnanimity of the mission payloads such as thermal camera, infrared high spectrograph, laser radar
Memory technology, and in particular to a kind of wideband data high speed mass memory method based on embedded architecture efficiently solves multi-source
Data high-speed magnanimity reliable memory, overall process signal characteristic save from damage while record support and access, multi-source nonformatted data lattice
The technical barriers such as formulaization record, may be implemented generalization, the miniaturization and lightweight of wideband data high speed mass memory unit.
Background technology
With the development of aeronautical and space technology, the equipments such as various novel unmanned planes, stratospheric airship, fighter plane, transporter
It continues to introduce new, mission payload also constantly diversification.In order to obtain more effective informations, common visible light in equipment
The message transmission rate of the mission payloads such as camera, thermal camera, infrared high spectrograph, laser radar is higher and higher, and not
It is often not quite similar with the data-interface of mission payload, communication pattern, data encoding, volume frame format etc..And unmanned plane, advection
It is small, light-weight to often require that the data storage device of its configuration has in view of its own finite volume for the equipments such as layer dirigible
The features such as.These factors make existing data storage device cannot be satisfied practical application request.Therefore, there is an urgent need to a kind of energy
Enough support multi-channel high-speed data transmission, the miniaturization universal data storage device with massive storage space.
SRIO（Serial RapidIO）It is the highly reliable of embedded system exploitation proposition, high-performance, is handed over based on packet
The high-speed serial communication standard of new generation changed, can be as the data transmission and interconnection mode of internal system, and supports chip-scale
With the communication of plate grade.SRIO buses can meet Visible Light Camera, thermal camera, infrared high spectrograph, laser well
The data transportation requirements of the mission payloads such as radar are widely used to the fields such as Aeronautics and Astronautics, telecommunications, communication.In current skill
Under the conditions of art, broadband mass data storage device is typically the form realization by server carry disk array, although this
Kind implementation method is also advantageous, still, in view of index factors such as its volume, weight and power consumptions, it is difficult to be stored as conventional data
Equipment application is in the weaponrys such as unmanned plane and stratospheric airship.And embedded storage architecture is used to realize that mass data storage can
Effectively to solve the problems, such as this, and mSATA solid state disks have that capacity is big, speed is high, the advantages such as small, light-weight, are logical
With the ideal storage medium of data storage device.
Invention content
For the weapons such as aerospace field unmanned plane, stratospheric airship and civilian equipment in development, production, experiment and dimension
To the active demand of universal data storage device during shield, by using high-speed multiple channel SRIO optical fiber interface transmitting skills
Art, wideband data high speed great capacity data storage, complicated Clock management technology, multi-source nonformatted data format recording technique,
Overall process signal characteristic saves technology from damage while record support and access technique, miniaturization technology etc., can effectively solve the problem that more
The technical barriers such as channel high-speed serial data transmitting, multi-source data high speed magnanimity reliable memory, it is non-to have invented a kind of multi-source
It formats wideband data high speed magnanimity and formats storage and feature security method.
The present invention adopts the following technical scheme that realization：Multi-source unformatted wideband data high speed magnanimity formats storage
With feature security method, hardware system includes that input/output interface module, FPGA main control modules, DDR3 cache modules, solid-state are hard
Disk array module, power management module, high precision clock module；Input/output interface module includes 8 road SRIO optical fiber interfaces, 2
Road RS422 interfaces and 1 gigabit ethernet interface and 1 spare FMC expansion interface；FPGA main control modules are for realizing number
According to communication interface and its agreement, completes data receiver, caching, splicing, compiles frame and the work(such as transmission and relevant logic control
Can, and realize complicated Clock management function；DDR3 cache modules include DDR3 and 1 group of 32bit bit wide of 2 groups of 64bit bit wides
DDR3；Wherein, the DDR3 of 64bit bit wides is used for the read-write cache of high-speed data；The DDR3 of 32bit bit wides is as embedding inside FPGA
Enter the operation caching of microsever MicroBlaze；Solid state disk array module is hard by the SATA solid-states that 16 capacity are 1TB
Disk forms a solid state disk array, realizes that high speed reliably stores mass data under being uniformly controlled of FPGA；Power management
Module is converted for realizing voltage, and the burning voltage of various different range is provided for entire hardware circuit；High precision clock module
High precision clock is provided for FPGA and various data-interfaces.
The present invention is whole by structural module, function in the design using standardization, modularization and General design thought
Body, miniaturization and performance can the design measures such as survey, further increase institute's titration data recording equipment versatility, can
By property, testability, maintainability and safety.The present invention realizes mass data storage using embedded storage architecture.
Further, 8 road SRIO optical fiber interfaces of the hardware system support, selection MPO multicore watertights optical fiber connector,
HTA8530 optical-electric modules and the GTX high speed serialization transceivers joint built in FPGA constitute high speed fibre interface module；In view of high speed
The importance of clock circuit and the substantial connection of optical fiber link data rate and reference clock, pass through control in serial communication
Single channel SRIO optical fiber links data rate is steady to system to avoid optical fiber link complex electromagnetic environment caused by rate is excessively high
The influence of qualitative generation, and by designing high precision clock circuit, further increase the reliability of data transmission.
Further, the unitized of data format is realized using variable length frame head strategy, multi-source nonformatted data is pressed
It is stored according to the data format of setting；And data format Dynamic Configuration is used, it is each using control software setting configuration
The data format in channel realizes the dynamically configurable of data format, can be under the premise of not changing hardware platform according to difference
Mission requirements setting and modifying data memory format further improves the versatility and using flexible of institute's titration data recording equipment
Property.
Further, by using multistage front end buffering area, poll processing rear end buffering area mechanism, multi-stage pipeline technology
And high-speed high capacity data buffer storage realizes synchronization and the reliable memory between multi-channel data, it can be ensured that overall process data are remembered
The integrality of record realizes that overall process signal characteristic is saved from damage, can provide effective data for subsequent data analysis and processing and support.
Further, this method uses full-duplex data bussing technique, devises and reads while write operating process, embedded
Microprocessor is uniformly coordinated under control, using automatic adjusument input data buffer memory capacity and solid state disk digital independent quantity
The read-write hybrid manipulation of data is realized, can effectively realize under the premise of not influencing data reliable memory record support simultaneously
And access.
The effect income of the present invention：Present invention could apply to the weapons such as aerospace field unmanned plane, stratospheric airship
And in the development of civilian equipment, production, experiment and maintenance process, it can effectively realize the high speed mass memory of multi-source data, be
The performance evaluation of related weaponry provides critical data and supports, to realize the performance test and evaluation to equipment.In view of utilization
The data storage device of the method for the present invention development has that capacity is big, speed is high, the advantages such as small, light-weight, low in energy consumption, and has
There are higher environmental suitability and good versatility, is alternatively Airborne Data Recorder, spaceborne data logger, missile-borne number
The equipment such as data logger, vehicle-mounted data recorder, ships data recorder are carried according to recorder, arrow, technical support is provided, promote
It is applied to the processes such as development, production, experiment and the maintenance of the fields such as Aeronautics and Astronautics, vehicle, ship correlation weapon and civilian equipment
In, the test, experiment and daily maintenance safeguard level of my army's weaponry can be effectively improved.As can be seen that the present invention has extensively
Wealthy application prospect, one can effectively push the seriation, standardization and modular development of universal data storage device surely.
Description of the drawings
Fig. 1 is hardware composition frame chart in the specific embodiment of the invention one；
Fig. 2 is DDR3 cache modules structural schematic diagram in the specific embodiment of the invention one；
Fig. 3 is SRIO things conveying flow figure in the specific embodiment of the invention two；
Fig. 4 is data packet frame head form schematic diagram in the specific embodiment of the invention three；
Fig. 5 is two-stage data buffer zone schematic diagram in the specific embodiment of the invention four；
Fig. 6 is 8 channel polling schematic diagram of mechanism in the specific embodiment of the invention four；
Fig. 7 is multilevel pipelining schematic diagram in the specific embodiment of the invention four；
Fig. 8 is to read while write operational flowchart in the specific embodiment of the invention five.
Specific implementation mode
Specific implementation mode one illustrates the specific embodiment of the invention in conjunction with Fig. 1 and Fig. 2.The present invention uses in the design
Standardization, modularization and General design thought, can be surveyed by structural module, function integration, miniaturization and performance
The design measures such as change further increase versatility, reliability, testability, maintainability and the safety of the present invention.The present invention uses
Embedded storage architecture based on FPGA, hardware composition frame chart are as shown in Figure 1.The hardware system of the present invention includes mainly input
When output interface module, FPGA main control modules, DDR3 cache modules, solid state disk array module, power management module, high-precision
The component parts such as clock module.
Input/output interface module includes mainly 8 road SRIO optical fiber interfaces, 2 road RS422 interfaces and 1 gigabit Ethernet
Interface and 1 spare FMC expansion interface.High speed mission payload data are received by 8 road SRIO optical fiber interfaces, 2 road RS422 connect
It is used to receive control command all the way in mouthful, another way is for receiving low speed mission payload data, gigabit ethernet interface（RJ45）
It is mainly used for the configuration to the various programmable parameters of conventional data recording equipment, it is also possible to which data export when making special circumstances connects
Mouthful, for reading the test data stored in solid state disk array.The FMC that the present invention has also reserved a standard in design connects
Mouthful, the Camera Link interfaces of 1 standard, 4 GTX interfaces and 1 3G-SDI interface can be expanded.It can be according to reality
Using needs, it can realize the various interfaces of seamless switching by replacing corresponding extension subcard, effectively increase its versatility.
The V7 series high-performance FPGA of the quasi- selection Xilinx companies of FPGA main control modules, it is mainly real by FPGA main control modules
Existing data communication interface and its agreement complete data receiver, caching, splicing, compile frame and transmission and relevant logic control etc.
Function, and realize complicated Clock management function.Wherein, the data communication interface of realization includes 8 road SRIO interfaces, 16 tunnels
SATA3.0 interfaces, 3 groups of DDR3 interfaces, 2 road RS422 interfaces and 1 road Ethernet interface.In being uniformly controlled for FPGA main control modules
Under management, reliable reception, transmission and the high speed mass memory of multichannel data are realized.
Fig. 2 show the structural schematic diagram of the DDR3 cache modules of the present invention.It is made of 3 groups of DDR3, including 2 groups
The DDR3 of DDR3 and 1 group of 32bit bit wide of 64bit bit wides.Wherein, the DDR3 of 64bit bit wides is mainly used for the reading of high-speed data
Write buffer, by 4 bit wides be 16bit, the MT41K512M16 that capacity is 8Gbit is spliced, and data rate reaches 1600MT/S
× 64=96Gbps, memory capacity reach 512M × 16bit × 4=32Gbit.The DDR3 of 32bit bit wides is internally embedded formula as FPGA
The operation of microprocessor MicroBlaze caches, by 2 bit wides are 16bit, capacity is 8Gbit MT41K512M16 splicings
At data rate 24Gbps, memory capacity 16Gbit, the operation that can be very good to meet MicroBlaze use.
The present invention, as storage medium, is made of using SATA solid state disks the mSATA solid state disks that 16 capacity are 1TB
One solid state disk array realizes that high speed reliably stores mass data under being uniformly controlled of FPGA.If selecting 16 capacity
Form solid state disk array for the mSATA solid state disks of 2TB, then it can be by the expanding storage depth of whole equipment to 32TB.
Power management module is mainly used for realizing voltage conversion, and the stabilization of various different range is provided for entire hardware circuit
Voltage.High precision clock module is mainly that FPGA and various data-interfaces provide high precision clock.The clock of entire hardware system
It is made of 4 high-precision external crystal-controlled oscillations, passes through the novel mixed mode timer manager MMCM inside FPGA（Mixed-Mode
Clock Manager）Module generates the required clock of modules, and is effectively managed complicated clock, to ensure to count
According to reliable reception, transmission and storage.
Specific implementation mode two illustrates the specific embodiment of the invention in conjunction with Fig. 3.SRIO is embedded system exploitation
The highly reliable of proposition, high-performance, the high-speed serial communication standard of new generation based on packet switch.The present invention supports 8 road SRIO optical fiber
Interface selects the GTX high speeds built in MPO multicores watertight optical fiber connector of good performance, HTA8530 optical-electric modules and FPGA to go here and there
Row transceiver joint constitutes high speed fibre interface module.In view of the importance and optical fiber of clock circuit in high-speed serial communication
The substantial connection of link data rates and reference clock, this project are kept away by controlling single channel SRIO optical fiber links data rate
Exempt from the optical fiber link influence that complex electromagnetic environment generates system stability caused by rate is excessively high, and by designing high-precision
Clock circuit further increases the reliability of data transmission.
SRIO protocol specifications are made of packet (packet) and controlling symbols (control symbol), and packet is SRIO
Basic communication unit in system between endpoint device, the effect of controlling symbols are to manage the transaction flow of SRIO physical layers, are realized
Packet receives the functions such as confirmation, flow control and link maintenance, and provides handshake mechanism for physical layer, can be used for integrating, answering
Data packet is answered and retransmitted, and carries out the Fault recovery based on hardware components.SRIO operations are based on request and response transactions.
Packet is the medium of the interconnection between endpoint device in bus system, and request transaction is initiated by main equipment, the transaction types data frame quilt
It send to the purpose equipment of distal end.Purpose equipment makes corresponding response according to the transaction types of data frame, completes transaction operation.Its
Realize that the detailed process that affairs are transmitted is as shown in Figure 3.
Specific implementation mode three illustrates the specific embodiment of the invention in conjunction with Fig. 4.In order to which multi-source nonformatted data is pressed
It is stored according to the data format of setting, the present invention realizes the unitized of data format using variable length frame head strategy, further
Improve the versatility and using flexible of institute's titration data recording equipment.Its data frame format includes frame head and valid data two
Part.In order to realize that the unification of data format, the present invention set minimum data storage unit as 512 bytes, it is desirable that data frame
Size is necessary for the integral multiple of 512 bytes, minimum 512 byte.The frame head format of design is as shown in Figure 4.It is wrapped in frame head format
Include the reserved field of the tag field and a variable-length for having particular meaning of 36 bytes.Wherein, the particular meaning of 36 bytes
Label include the frame flag of 16 bytes, the channel labelled notation of 1 byte, 1 byte channel pattern mark, 2 bytes
The line number of frame frequency label, the frame number label of 2 bytes, the color depth label of 2 bytes, the columns label of 2 bytes, 2 bytes
It marks, the time of 5 bytes marks（When, minute, second account for 1 byte respectively, millisecond accounts for 2 bytes）, 3 bytes frame length scale
Note.Variable-length reserved field is used for according to real data length compensation data frame sign, when data frame is less than 512 byte,
512 bytes are supplied by increasing the length of reserved field in frame head so that all data frame lengths of record are 512 bytes
Integral multiple, the unitized of data format is realized with this.Therefore, minimum 36 byte of frame head length is up to 512 bytes, protects
The length for section of writeeing down characters is variable in 0~476 byte.It should be strongly noted that 36 byte particular meanings label physical meaning with
Byte number can be modified adjustment according to practical application, if exceeding 36 bytes, can also be supplemented by reserved field.
Specific implementation mode four illustrates the specific embodiment of the invention in conjunction with Fig. 4, Fig. 5 and Fig. 6.Realize overall process data
Complete documentation and feature to save from damage be necessary functions of the present invention, and the Data Input Interface arrived involved in the present invention have it is mostly logical
Therefore the features such as road, high-speed, during realization, will not only ensure that the reliable reception of each channel data is preserved with complete,
It is also to be ensured that the synchronization between multi-channel data.The present invention handles rear end buffering area by using multistage front end buffering area, poll
The effective measures such as mechanism, multi-stage pipeline technology and high-speed high capacity data buffer storage come realize the synchronization between multi-channel data with
Reliable memory, it can be ensured that the integrality of overall process data record.
Fig. 5 is shown caches the front end data buffering area formed by two-stage FIFO.The data in different channels are by phase in FPGA
The data collector answered is completed after receiving, and first order FIFO is first written, and is write and is enabled to be the data enable signal by input data
Determining.When needing the FIFO in synchronous multiple channels there are data, while reading the data in each FIFO.By the first order
The reading of FIFO is enabled enabled as writing for second level FIFO, to ensure that multi-channel data is synchronously written into second level FIFO, subsequently
Data transmission is operated only for second level FIFO.The problem of data synchronization is not only solved by the way that buffer area is arranged, it is also logical
Crossing first order FIFO effectively realizes clock domain conversion.
When executing multi-channel data storage operation, this project receives and stores multichannel number simultaneously using polling mechanism
According to.Fig. 6 show the polling mechanism designed for 8 channel datas.The juche idea of polling mechanism, which is exactly priority processing, data
Channel, be immediately switched in addition there is the channel of data to be handled when having handled a channel.It is ordered when receiving storage
When, whether ready, immediately reading out data if ready is stored if first checking for first channel data, if
It is offhand ready just to automatically switch to second channel and be polled.And so on, the data in all channels are polled
Processing.The reliable memory of multi-channel data is ensured with this.
The present invention passes through multi-stage pipeline technology and high-speed high capacity data buffer storage, it can be ensured that in the case that high bandwidth not
It can cause loss of data or entanglement because of congestion.Fig. 7 show the multilevel pipelining schematic diagram of this Project design.Its
In, a level production line and three class pipeline be by FPGA inside FIFO complete, be mainly used for realizing data buffer storage and
Clock-domain crossing data processing.Second level flowing water is realized by high-speed high capacity DDR3 data buffers plug-in FPGA,
It can effectively solve the problem that the problem of magnanimity data high-speed caches under high bandwidth, and further ensure the integrality of data.
Specific implementation mode five illustrates the specific embodiment of the invention in conjunction with Fig. 8.Realization is not influencing data reliable memory
Under the premise of the function of record support and access simultaneously be necessary functions of the present invention.The present invention uses full-duplex data bus skill
Art is controlled by the coordination of embedded microprocessor, can effectively be realized while the function of record support and access.
The GTX transceivers inside SRIO optical fiber data bus, SATA3.0 data/address bus and FPGA that the present invention uses,
Support full-duplex communication.This is independent of each other when data double-way circulation has been effectively ensured in system architecture, to realize while remembering
Record and access provide basic-level support.
Under the coordination control of embedded microprocessor, the function of record support and access simultaneously is effectively realized.To solid-state
The Read-write Catrol operation of hard disk array be by FPGA inside embedded microprocessor realize that and embedded microprocessor is
Read-write operation is initiated and terminates by receiving superior instructions.It is single thread work in view of the embedded microprocessor inside FPGA
Therefore operation mode will be realized and read while write operation, it is necessary to be realized using the nested mode of read-write.Fig. 8 show the present invention and sets
Read-write operation flow chart while meter.
After embedded microprocessor receives read write command, read-write operation is initiated.When executing read-write operation, first look at
Whether outer input data caching is ready.If ready, data write operation first is carried out to solid state disk, to ensure
Valid data will not be lost, otherwise, with regard to first carrying out data reading operation to solid state disk.
The data that can be written with valid cache by data cache module, while executing data cached, insertion declines
Processor can carry out data read-write operation to solid state disk, and the read-write nested operation under single thread is realized with this.
Meanwhile the present invention is also by using automatic adjusument input data buffer memory capacity and solid state disk digital independent quantity
To realize the read-write hybrid manipulation of data.When needing to carry out high band wide data storage, then by increasing data buffer storage capacity, subtracting
Small data reads the method for quantitative proportion to realize.It, then can be by reducing data buffer storage when front end data input tape is wide smaller
Capacity increases the method for digital independent quantitative proportion to realize.
The present invention use full-duplex data bussing technique, embedded microprocessor be uniformly coordinated control under, Ke Yi
Under the premise of not influencing data reliable memory, realize simultaneously record and access operation, effectively increase the flexibility of operation.
Multistage front end buffering area, poll processing rear end buffering area mechanism, multi-stage pipeline technology and high-speed high capacity
Data buffer storage is realized by corresponding program with the read-write mixing of data.Those skilled in the art are reading above-mentioned work
After flow, so that it may easily to write out corresponding program.
Specific implementation mode six.Realize that miniaturization, the lightweight of data storage device can further widen the present invention's
Application field.This using embedded storage architecture realizes mass data storage to the present invention, and hardware selects that integrated level is high, volume
Complicated sequence circuit and control system are fused in embedded controller chip and are realized, used by small, light-weight component
The data communication interface of high integration, and using mSATA solid-state memory of the weight less than 10g as storage medium, in hardware
On effectively reduce volume and weight.On the basis of meeting environmental requirement, it then follows solid, compact design principle, maximum journey
The volume of the reduction mechanical cover of degree, and select titanium alloy as mechanical hull material, while proof strength, effectively mitigate
Weight of equipment.
Certainly, above description is not limitation of the present invention, and the present invention is also not limited to the above, this technology neck
The variations, modifications, additions or substitutions that the technical staff in domain is made in the essential scope of the present invention should also belong to the present invention's
Protection domain.
Claims (9)
1. multi-source unformatted wideband data high speed magnanimity formats storage and feature security method, which is characterized in that hardware system
System includes input/output interface module, FPGA main control modules, DDR3 cache modules, solid state disk array module, power management mould
Block, high precision clock module；Input/output interface module includes 8 road SRIO optical fiber interfaces, 2 road RS422 interfaces and 1 gigabit
Ethernet interface and 1 spare FMC expansion interface；FPGA main control modules are complete for realizing data communication interface and its agreement
At data receiver, caching, splicing, frame and the functions such as transmission and relevant logic control are compiled, and realizes complicated Clock management work(
Energy；DDR3 cache modules include the DDR3 of DDR3 and 1 group of 32bit bit wide of 2 groups of 64bit bit wides；Wherein, 64bit bit wides
DDR3 is used for the read-write cache of high-speed data；The DDR3 of 32bit bit wides is internally embedded microsever as FPGA
The operation of MicroBlaze caches；Solid state disk array module forms one admittedly by the SATA solid state disks that 16 capacity are 1TB
State hard disk array realizes that high speed reliably stores mass data under being uniformly controlled of FPGA；Power management module for realizing
Voltage is converted, and the burning voltage of various different range is provided for entire hardware circuit；High precision clock module is FPGA and various
Data-interface provides high precision clock.
2. multi-source unformatted wideband data high speed magnanimity as described in claim 1 formats storage and feature security method,
It is characterized in that, the hardware system supports 8 road SRIO optical fiber interfaces, MPO multicore watertights optical fiber connector, HTA8530 are selected
Optical-electric module and the GTX high speed serialization transceivers joint built in FPGA constitute high speed fibre interface module；By controlling single channel
SRIO optical fiber links data rate come avoid optical fiber link complex electromagnetic environment caused by rate is excessively high to system stability produce
Raw influence, and by designing high precision clock circuit, improve the reliability of data transmission.
3. multi-source unformatted wideband data high speed magnanimity as claimed in claim 1 or 2 formats storage and the feature side of saving from damage
Method, which is characterized in that the unitized of data format is realized using variable length frame head strategy, multi-source nonformatted data according to setting
Fixed data format is stored；And data format Dynamic Configuration is used, configure each channel using control software setting
Data format, realize the dynamically configurable of data format.
4. multi-source unformatted wideband data high speed magnanimity as claimed in claim 1 or 2 formats storage and the feature side of saving from damage
Method, which is characterized in that by using multistage front end buffering area, poll processing rear end buffering area mechanism, multi-stage pipeline technology and
High-speed high capacity data buffer storage realizes synchronization and the reliable memory between multi-channel data, it can be ensured that overall process data record
Integrality, realize that overall process signal characteristic is saved from damage, can be that subsequent data analysis and processing provide effective data support.
5. multi-source unformatted wideband data high speed magnanimity as claimed in claim 1 or 2 formats storage and the feature side of saving from damage
Method, which is characterized in that this method uses full-duplex data bussing technique, devises and reads while write operating process, declines in insertion
Processor is uniformly coordinated under control, real using automatic adjusument input data buffer memory capacity and solid state disk digital independent quantity
Showed the read-write hybrid manipulation of data, can effectively realize under the premise of not influencing data reliable memory record support simultaneously and
It accesses.
6. multi-source unformatted wideband data high speed magnanimity as claimed in claim 3 formats storage and feature security method,
It is characterized in that, variable length frame head strategy includes the following steps：Minimum data storage unit is set as 512 bytes, it is desirable that data
The size of frame is necessary for the integral multiple of 512 bytes, minimum 512 byte；Frame head format, which includes 36 bytes, particular meaning
Tag field and a variable-length reserved field, wherein 36 bytes particular meaning label include 16 bytes frame
The frame of label, the channel labelled notation of 1 byte, the channel pattern label of 1 byte, the frame frequency label of 2 bytes, 2 bytes
The time mark of labelled notation, the color depth label of 2 bytes, the columns label of 2 bytes, the line number label of 2 bytes, 5 bytes
The frame length scale designation of note, 3 bytes；In the time label of wherein 5 bytes, when, minute, second account for 1 byte respectively, millisecond accounts for 2
A byte；Variable-length reserved field is used for according to real data length compensation data frame sign, when data frame is less than 512 bytes
When, supply 512 bytes by increasing the length of reserved field in frame head so that all data frame lengths of record are 512
The integral multiple of byte realizes the unitized of data format with this.
7. multi-source unformatted wideband data high speed magnanimity as claimed in claim 4 formats storage and feature security method,
It is characterized in that, multistage front end buffering area concrete scheme is as follows：Front end data buffering area is formed by two-stage FIFO cachings；No
Data with channel are completed by corresponding data collector in FPGA after receiving, and first order FIFO is first written, write it is enabled be by
What the data enable signal of input data determined；When needing the FIFO in synchronous multiple channels there are data, while reading every
Data in a FIFO；It is enabled enabled as writing for second level FIFO by the reading of first order FIFO, to ensure that multi-channel data is same
Step ground write-in second level FIFO, subsequent data transmission are operated only for second level FIFO；
The poll processing rear end buffering area mechanism concrete scheme is as follows：The juche idea of polling mechanism, which is exactly priority processing, number
According to channel, be immediately switched in addition there is the channel of data to be handled when having handled a channel；It is ordered when receiving storage
Whether when enabling, it is ready to first check for first channel data, and immediately reading out data if ready is stored, such as
Fruit is offhand ready just to be automatically switched to second channel and is polled；And so on, the data in all channels are taken turns
Inquiry is handled.
8. multi-source unformatted wideband data high speed magnanimity as claimed in claim 4 formats storage and feature security method,
It is characterized in that, the multi-stage pipeline technology and high-speed high capacity data buffer storage concrete scheme are as follows：One level production line and three
Level production line be by FPGA inside FIFO complete, be mainly used for realizing data buffer storage and clock-domain crossing data processing；
Second level flowing water is realized by high-speed high capacity DDR3 data buffers plug-in FPGA.
9. multi-source unformatted wideband data high speed magnanimity as claimed in claim 5 formats storage and feature security method,
It is characterized in that, to the Read-write Catrol of solid state disk array operation be by FPGA inside embedded microprocessor realize,
And embedded microprocessor is to initiate and terminate read-write operation by receiving superior instructions；When embedded microprocessor receives
To after read write command, read-write operation is initiated；When executing read-write operation, first look at whether outer input data caching prepares just
Thread first carries out data write operation if ready to solid state disk, to ensure that valid data will not be lost, otherwise, just first
Data reading operation is carried out to solid state disk；
The data that can be written with valid cache by data cache module, while executing data cached, embedded microprocessor
Device can carry out data read-write operation to solid state disk, and the read-write nested operation under single thread is realized with this；
The reading of data is also realized by using automatic adjusument input data buffer memory capacity and solid state disk digital independent quantity
Write hybrid manipulation；When needing to carry out high band wide data storage, then by increasing data buffer storage capacity, reducing digital independent quantity
The method of ratio is realized；When front end data input tape is wide smaller, then can be read by reducing data buffer storage capacity, increasing data
The method of quantitative proportion is taken to realize.
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