CN110334040B - Satellite-borne solid-state storage system - Google Patents
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- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
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- G06F13/1694—Configuration of memory controller to different memory types
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Abstract
The invention belongs to the technical field of satellite-borne solid-state memories, and particularly relates to a satellite-borne solid-state memory system, which comprises: the system comprises a main control CPU module arranged on a CPU, a storage control module arranged on an FPGA and an FLASH array; the FLASH array comprises a plurality of FLASH memories; the main control CPU module is used for generating a configuration instruction according to the received instruction transmitted by the ground station and the data address in the FLASH array and sending the configuration instruction to the storage control module; the storage control module is used for receiving the data source packet generated by the payload, performing RS error correction coding on the data source packet, and storing the data source packet subjected to the error correction coding in a plurality of FLASH memories; and extracting the corresponding error correction coded data source packet stored in the FLASH memory according to the received configuration instruction, carrying out RS decoding processing on the error correction coded data source packet, and transmitting the decoded data source packet back to the ground station through the data transmission transmitter.
Description
Technical Field
The invention belongs to the technical field of aerospace aircraft electronic systems, satellite-borne solid-state memories, aviation and aerospace electronic data processing, storing and transmitting, and particularly relates to a satellite-borne solid-state storage system.
Background
At present, the mainstream storage medium on a spacecraft is a NAND-type FLASH. It has the following outstanding advantages: the data is nonvolatile, and the power failure data is not lost; the power consumption is low, and data can be kept for a long time without power supply; the service life is long, and the erasing times can reach 10 ten thousand; the density is large, the single chip can reach more than 1GB, and the capacity of a single stacked module is more than 8 GB. Due to these advantages, it is widely used in the development of on-board solid-state memories.
The function of the satellite-borne solid-state storage controller is as follows:
1. receiving scientific data input by an external payload and satellite engineering parameters from an upper-layer satellite computer;
2. respectively forming data source packets by the received data according to corresponding telemetry source packet data formats, and then carrying out RS error correction coding on the data source packets;
3. the coded data source packet is cached in a partition mode according to load data and the star project parameters and is automatically stored into a fixed partition in a FLASH memory;
4. generating operation signals of reading, writing, erasing and the like of the FLASH memory;
5. detecting error information such as programming and erasing in the storage area, marking error pages and blocks, and timely notifying software in the form of external interrupt application;
6. the operations such as on-demand playback, erasing and the like aiming at the specified FLASH storage area can be started through software commands;
7. the hardware interrupt control device is provided with a register for representing the hardware working state and the interrupt state, and the content of the register can be read from a specific address by software;
8. the playback data is subjected to RS error correction decoding and output to the multiplexing module;
9. a "Block Allocation Table" (BAT) reflecting the use of all blocks of the memory area may be generated and may be read by software from the specified address.
The satellite-borne solid-state storage system is complex in function and high in reliability requirement, and in the prior art, each CPU instruction is usually set up in a corresponding register in an FPGA (field programmable gate array), and the FPGA finishes instruction communication by reading the register. Therefore, the hardware and software design of the on-board solid-state storage system is very complex, and the complexity and the cost of the system are increased. With the continuous improvement of the integration level and the complexity of the satellite-borne solid-state storage system, the difficulty of design, integration, test and later version upgrade of the satellite-borne solid-state storage system is further increased in the prior art. In addition, the prior art cannot support NAND type FLASH memory arrays of different FLASH chip manufacturers, different FLASH chip capacities and different stacking configurations.
Disclosure of Invention
The invention aims to solve the defects of the conventional satellite-borne solid-state storage system, and provides the satellite-borne solid-state storage system, which solves the technical problem that the APB (advanced peripheral bus) bus cannot be used for uniformly managing and scheduling each functional module in the satellite-borne solid-state storage system, and supports the online configurable function of parameters. Meanwhile, the technical problems of complexity, poor universality, difficult upgrading, difficult maintenance, high cost and the like of the conventional satellite-borne solid-state storage system are solved, so that the satellite-borne solid-state storage system which is standardized, configurable, low in cost and universal is provided.
In order to achieve the above object, the present invention provides a satellite-borne solid-state storage system, which includes: the system comprises a main control CPU module arranged on a CPU, a storage control module arranged on an FPGA and an FLASH array; the FLASH array comprises a plurality of FLASH memories;
the main control CPU module is used for generating a configuration instruction according to the received instruction transmitted by the ground station and the data address in the FLASH array and sending the configuration instruction to the storage control module;
the storage control module is used for receiving the data source packet generated by the payload, performing RS error correction coding on the data source packet, and storing the data source packet subjected to the error correction coding in a plurality of FLASH memories;
and extracting the corresponding error correction coded data source packet stored in the FLASH memory according to the received configuration instruction, carrying out RS decoding processing on the error correction coded data source packet, and transmitting the decoded data source packet back to the ground station through the data transmission transmitter.
As one improvement of the technical scheme, the CPU, the FPGA and the FLASH array are connected through an advanced peripheral bus, and communication among the CPU, the FPGA and the FLASH array is realized through the advanced peripheral bus; and an HPI interface is adopted between the CPU and the FPGA.
As an improvement of the above technical solution, the storage control module specifically includes: the device comprises a combination input sub-module, a storage operation sub-module, a multiplexing output sub-module and an APB bridge sub-module;
the combining input sub-module is used for receiving multi-path high-speed parallel data generated by an external effective load and satellite engineering parameters from an upper-layer satellite service computer; grouping the received multi-path high-speed parallel data, independently forming a data source packet by each group of data, carrying out RS error correction coding on the data source packet, caching the data source packet after error correction coding, and obtaining a cached data source packet; outputting the cached data source packet to a storage operation submodule; wherein the data source package comprises payload generated data and a satellite engineering parameter package from a satellite service;
the storage operation submodule is used for initializing a FLASH memory in the FLASH array; the data source module is also used for carrying out configuration, data writing, BAT table organization, data erasing, mark invalidation and data playback operation on data addresses in the cached data source packet, obtaining the operated data source packet and storing the operated data source packet to a plurality of FLASH memories; extracting the corresponding error correction coded data source packet stored in the FLASH memory according to the received configuration instruction, performing RS decoding processing on the error correction coded data source packet, and sending the decoded data source packet to a multiplexing output submodule;
the multiplexing output submodule is used for carrying out data caching on the data source packet after the decoding processing, forming a data framing together with the file number and the time code and outputting the data framing to the data transmission transmitter;
and the APB bridge submodule is used for finishing the communication between the CPU and the FPGA.
As an improvement of the above technical solution, the storage operation sub-module specifically includes: the device comprises an APB management unit, a combining input unit, an RAM cache unit, a FLASH control unit, a BAT RAM cache unit and a multiplexing output unit;
the APB management unit is used for managing each unit in the storage control sub-module;
the combining input unit is used for carrying out RS error correction coding on the data source packet to obtain the data source packet after error correction coding, sending the data source packet after error correction coding into the asynchronous FIFO for caching, and sending the cached data source packet to the RAM cache unit;
the RAM cache unit is used for carrying out secondary cache on the cached data source packet and sending the data source packet subjected to secondary cache to the FLASH control unit;
the FLASH control unit is used for respectively carrying out initialization and parameter configuration on a plurality of FLASH memories and storing error correction coded data source packets; the system is also used for organizing BAT (Block Assignment Table) information and sending the BAT information to the BAT RAM cache unit; the data source package is also used for executing the operations of writing, replaying, erasing and marking invalid of the data source package after error correction coding to obtain the data source package after operation;
the BAT RAM cache unit is used for storing the BAT information sent by the FLASH control unit and sending the BAT information to the APB management unit;
and the multiplexing output unit is used for RS decoding the error-correction coded data source packet output by the FLASH control unit and writing the decoded data source packet into the asynchronous FIFO for caching.
As an improvement of the above technical solution, the FLASH control unit specifically includes: the device comprises an initialization and parameter configuration subunit, a data writing subunit, an organization BAT table subunit, a data erasing subunit, a marking invalidation subunit and a data playback subunit;
the initialization and parameter configuration subunit is used for respectively performing initialization scanning on a plurality of FLASH memories in the NAND FLASH array, generating corresponding FLASH bad block information, configuring configurable parameters of a storage system and configuring data addresses in the cached data source packet;
the data writing subunit is configured to write data in the cached data source packet according to the configured data address;
the organizing BAT table subunit is used for forming the FLASH bad block information generated in the initialization and parameter configuration subunit into block distribution table information, namely BAT information, and sending the BAT information to the BAT RAM cache unit;
the data erasing subunit is used for erasing the initially written data when the FLASH memory is full of the data in the cached data source packet;
the marking invalid subunit is used for marking a certain block in the FLASH memory as an invalid block when the situation that the certain block cannot write or erase data in the FLASH memory is found in the process of writing or erasing the data; this block will be skipped the next time a write or erase operation is performed;
and the data playback subunit is used for extracting the corresponding data source packet after error correction coding stored in the FLASH memory according to the configuration instruction sent by the main control CPU module and outputting the data source packet after error correction coding to the multiplexing output unit.
As one improvement of the above technical solution, an external interface is further provided outside the storage control module, and is used for performing connection communication with corresponding hardware;
the external interface includes: the device comprises a data input interface, a storage control interface, a transmission frame output interface, a CAN communication interface, an AD telemetering acquisition interface, a main control CPU unit interface, an OC instruction output interface and a digital clock interface;
the data input interface is used for receiving data generated by a payload from the outside through the LVDS receiving chip; receiving a satellite engineering parameter packet from a satellite service through an asynchronous RS422 receiving chip; forming a data source packet by data generated by the effective load and a satellite engineering parameter packet from a satellite service;
the storage control interface is used for storing the data source packet subjected to error correction coding to a plurality of FLASH memories in the FLASH array according to the state bus, the control bus and the data bus;
the transmission frame output interface is used for framing and outputting the data to the data transmission transmitter through the LVDS chip;
the CAN communication interface is used for receiving data transmission instructions and time code information sent by the house service computer; and the main control CPU module is also used for receiving a parameter configuration instruction sent by the main control CPU module.
As an improvement of the above technical solution, the FLASH control unit further includes: a parameter configuration layer; the NAND type FLASH memory array is used for supporting different FLASH chip manufacturers, different FLASH chip capacities and different stacking configurations. The parameter configuration layer comprises: the device comprises a parameter configuration instruction analysis unit and a parameter configuration unit;
the parameter configuration instruction analysis unit is used for analyzing the configuration information of the data source packet stored in the FLASH;
and the parameter configuration storage unit is used for storing the analyzed parameter configuration instruction.
Compared with the prior art, the invention has the beneficial effects that:
(1) the compatibility is high, and NAND type FLASH memory arrays of different FLASH chip manufacturers, different FLASH chip capacities and different stacking configurations are supported;
(2) the integration level is high, and the workload and the complexity of CPU software and FPGA software are reduced;
(3) the engineering is simple to realize and the cost is low.
Drawings
FIG. 1 is a schematic structural diagram of a satellite-borne solid-state storage system according to the present invention;
FIG. 2 is a schematic structural diagram of a satellite-borne solid-state storage system according to the present invention;
FIG. 3 is a schematic diagram of an external interface of a satellite-borne solid-state storage system according to the present invention;
FIG. 4 is a state diagram of a parameter configuration layer parameter configuration instruction parsing unit of the satellite-borne solid-state storage system according to the present invention;
fig. 5 is a schematic diagram of a parameter configuration layer parameter configuration unit of a satellite-borne solid-state storage system according to the present invention.
Detailed Description
The invention will now be further described with reference to the accompanying drawings.
As shown in fig. 1 and 2, the present invention proposes a satellite-borne solid-state storage system, comprising: a main control CPU module disposed on a CPU (Central Processing Unit), a storage control module disposed on an FPGA (field programmable Gate Array), and a NAND-type FLASH Array;
the main control CPU module is used for generating a configuration instruction according to the received instruction transmitted by the ground station and the data address in the FLASH array and sending the configuration instruction to the storage control module;
the storage control module is used for receiving a data source packet generated by a payload, performing RS (Reed-Solomon code) error correction coding on the data source packet, and storing the data source packet subjected to the error correction coding in a plurality of FLASH memories;
and extracting the corresponding error correction coded data source packet stored in the FLASH memory according to the received configuration instruction, carrying out RS decoding processing on the error correction coded data source packet, outputting the decoded data source packet to a data transmission transmitter, and transmitting the data source packet back to the ground station in a wireless communication mode.
The FLASH array comprises a plurality of FLASH memories; the CPU, the FPGA and the FLASH array are connected through an Advanced Peripheral Bus (APB Bus), and communication among the CPU, the FPGA and the FLASH array is realized through the APB Bus; and an HPI interface is adopted between the CPU and the FPGA.
The storage control module specifically comprises: the device comprises a combination input sub-module, a storage operation sub-module, a multiplexing output sub-module and an APB bridge sub-module;
the combining input sub-module is used for receiving multi-path high-speed parallel data generated by an external effective load and satellite engineering parameters from an upper-layer satellite service computer; grouping the received multi-path high-speed parallel data, independently forming a data source packet by each group of data, carrying out RS error correction coding on the data source packet, sending the data source packet subjected to the error correction coding into an asynchronous FIFO (first in first out) for caching, and obtaining a cached data source packet; outputting the cached data source packet to a storage operation submodule;
the storage operation submodule is used for initializing a FLASH memory in the FLASH array; the data source module is also used for carrying out configuration, data writing, BAT table organization, data erasing, mark invalidation and data playback operation on data addresses in the cached data source packet, obtaining the operated data source packet and storing the operated data source packet to a plurality of FLASH memories; extracting the corresponding error correction coded data source packet stored in the FLASH memory according to the received configuration instruction, performing RS decoding processing on the error correction coded data source packet, and sending the decoded data source packet to a multiplexing output submodule;
wherein, the storage operation sub-module specifically comprises: the device comprises an APB management unit, a combining input unit, an RAM cache unit, a FLASH control unit, a BAT RAM cache unit and a multiplexing output unit;
and the APB management unit is used for managing each unit in the storage control sub-module. The APB management unit generates an address decoding strobe signal to strobe the corresponding Slave. When receiving a configuration instruction sent by a main control CPU module, gating a corresponding Slave and writing the configuration instruction into a predefined register in each functional unit. Then, each functional unit reads out the instruction in the corresponding register through an internal APB bus; and the BAT RAM is also used for receiving BAT information output by the BAT RAM buffer unit.
The combining input unit is used for carrying out RS error correction coding on the data source packet to obtain the data source packet after error correction coding, sending the data source packet after error correction coding into the asynchronous FIFO for caching, and sending the cached data source packet to the RAM cache unit;
the RAM cache unit is used for carrying out secondary cache on the cached data source packet and sending the data source packet subjected to secondary cache to the FLASH control unit;
the FLASH control unit is used for initializing the FLASH memory, configuring parameters and storing the error correction coded data source packet; the system is also used for organizing BAT (Block Assignment Table) information and sending the BAT information to the BAT RAM cache unit; the data source package is also used for executing the operations of writing, replaying, erasing and marking invalid of the data source package after error correction coding to obtain the data source package after operation;
wherein, the FLASH control unit specifically comprises: the device comprises an initialization and parameter configuration subunit, a data writing subunit, an organization BAT table subunit, a data erasing subunit, a marking invalidation subunit and a data playback subunit;
the initialization and parameter configuration subunit is used for respectively performing initialization scanning on a plurality of FLASH memories in the NAND FLASH array, generating corresponding FLASH bad block information, configuring configurable parameters of a storage system and configuring data addresses in the cached data source packet;
the data writing subunit is configured to write data in the cached data source packet according to the configured data address;
the organizing BAT table subunit is used for forming the FLASH bad block information generated in the initialization and parameter configuration subunit into block distribution table information, namely BAT information, and sending the BAT information to the BAT RAM cache unit;
the data erasing subunit is used for erasing the initially written data when the FLASH memory is full of the data in the cached data source packet;
the marking invalid subunit is used for marking a certain block in the FLASH memory as an invalid block when the situation that the certain block cannot write or erase data in the FLASH memory is found in the process of writing or erasing the data; this block will be skipped the next time a write or erase operation is performed;
the data playback subunit is used for extracting the corresponding data source packet after error correction coding stored in the FLASH memory according to the configuration instruction sent by the main control CPU module and outputting the data source packet after error correction coding to the multiplexing output unit;
wherein, the FLASH control unit further comprises: a parameter configuration layer; the configurable and universal functions are realized through a parameter configuration layer and are used for supporting NAND type FLASH memory arrays of different FLASH chip manufacturers, different FLASH chip capacities and different stacking configurations. The parameter configuration layer comprises: the device comprises a parameter configuration instruction analysis unit and a parameter configuration storage unit;
specific configurable parameters and parameter configuration instructions for the storage system are shown in table 1. The length of the parameter configuration instruction is 16 bits, and the parameter configuration instruction comprises internal time parameters, operation bit number, FLASH memory number, block number, page size and the like.
TABLE 1 parameter configuration instruction (ssr _ cfg)
The parameter configuration instruction parsing unit is shown in fig. 4. The main control CPU module is used for analyzing a parameter configuration instruction sent by the main control CPU module; specifically, a Finite State Machine (FSM) with an arbitration circuit is adopted to analyze the parameter configuration instruction sent by the main control CPU module. Initially, the reset state machine is in an idle state (idle) with no grant signal. When the parameter configuration instruction (ssr _ cfg) is received, bit0 of the parameter configuration instruction ssr _ cfg is parsed and a level 1 grant signal 1xx is generated, whereupon the state jumps to gnt1, where the configuration of "page size" in the memory control module is completed at gnt 1. After the parameter configuration operation under the gnt1 state is completed, a 2-level authorization signal x1x is generated, the state jumps to gnt2, the configuration of the number of pages in the block in the FLASH memory is carried out, and after the configuration is completed, the next-level authorization signal is generated, and the steps are repeated until 7 parameter configuration instructions are completely analyzed, and the initialization of the FLASH array is completed.
The parameter configures the storage unit as shown in fig. 5. The parameter configuration instruction is used for storing the analyzed parameter configuration instruction; specifically, each stage of parameter configuration operation is realized by controlling a register through a multiplexer to store the configuration parameters after parsing. The grant signal is connected to the enable terminal of the multiplexer, which is set to 1 when the grant signal arrives at this stage. The multiplexer determines which configuration parameter to store in the register according to the contents of the parameter configuration instruction.
For the parameter configuration commands bits 0-bit 6(gnt 1-gnt 5), which are only related to the operation addresses in the memory control module, the default operation addresses for page programming and page playback are set to the maximum values among the configuration parameters. In the process of data writing and playback, the configuration parameter registers are accessed in sequence according to the priority, and after the configuration parameter registers are read, high-order addresses which cannot be used in operations such as reading and writing are shielded by taking the read configuration parameters as a reference.
The configuration of the internal time parameters and the operation bit numbers (gnt 6-gnt 7) is complicated, so that the idea of code blocks is adopted to pack the codes of the time parameters and the operation bit numbers in each unit in the storage control module into one code block (in the same process) during development, and one code block is generated for each configuration parameter. When the parameter configuration is carried out, firstly, the configuration parameters in the parameter configuration register are read, and then, the corresponding codes are selected to execute according to the read parameter instructions, so that the configuration of the internal time parameters and the operation digits of the storage control module is completed. When the parameter configuration is completed, a mask signal is generated, and the code blocks which are not used under the parameter are masked. When the storage control module carries out a new round of operation, the code block under each configuration condition does not need to be traversed, but the parameters in the parameter configuration register are directly read, and the corresponding code block is executed. Since the configuration parameters are stored in the register, the parameter configuration instruction does not need to be analyzed when the system performs subsequent operations. This reduces both the complexity of the memory controller and minimizes the impact of parameter configuration operations on the memory rate.
The BAT RAM cache unit is used for storing BAT information sent by the FLASH control unit and sending the BAT information to the APB management unit, the main control CPU module sends a parameter configuration instruction to the APB management unit, and the APB management unit configures a corresponding FLASH memory according to the parameter configuration instruction sent by the main control CPU module and the received BAT information and stores a corresponding data source packet;
and the multiplexing output unit is used for RS decoding the error-correction coded data source packet output by the FLASH control unit and writing the decoded data source packet into the asynchronous FIFO for caching.
Specifically, when the data volume of the cached data source packet reaches the size of one page of FLASH, starting FLASH page programming, performing data address configuration, data writing, BAT table organization, data erasing and invalid mark operation on the cached data source packet reaching the page of FLASH, storing the data source packet into the NAND FLASH array, and loading the data source packet stored into the NANDFLASH array to the multiplexing output subunit through data playback operation;
the multiplexing output submodule is used for carrying out data caching on the data source packet after the decoding processing, forming a data framing together with the file number and the time code and outputting the data framing to the data transmission transmitter;
and the APB bridge submodule is used for managing and scheduling each submodule in the storage control module and is also used for finishing the communication between the CPU and the FPGA. The FPGA and the CPU are communicated through an APB bridge.
As shown in fig. 3, an external interface is further provided outside the storage control module, and is used for performing connection communication with corresponding hardware;
the external interface includes: the device comprises a data input interface, a storage control interface, a transmission frame output interface, a CAN communication interface, an AD telemetering acquisition interface, a main control CPU unit interface, an OC instruction output interface and a digital clock interface;
the data input interface is used for receiving data generated by a payload from the outside through the LVDS receiving chip; receiving a satellite engineering parameter packet from a satellite service through an asynchronous RS422 receiving chip; forming a data source packet by data generated by the effective load and a satellite engineering parameter packet from a satellite service;
the storage control interface is used for storing the data source packet subjected to error correction coding to a plurality of FLASH memories in the FLASH array according to the state bus, the control bus and the data bus;
the transmission frame output interface is used for framing and outputting the data to the data transmission transmitter through the LVDS chip;
the CAN communication interface is used for receiving data transmission instructions and time code information sent by the house service computer; the main control CPU module is also used for receiving a parameter configuration instruction sent by the main control CPU module;
the AD telemetering acquisition interface is used for completing telemetering acquisition of the temperature of the CPU and the temperature of the FPGA through control management of the AD circuit and forwarding the telemetering acquisition to the main control CPU module;
the main control CPU module interface is used for realizing the input of combining multiplexing storage related instruction words, state word query, BAT table reading, storage reading and writing, work parameter input of the solid-state storage controller, interruption and the like;
and the OC instruction output interface is used for generating an OC control instruction according to the instruction of the main control CPU module, generating a corresponding OC instruction pulse after analysis, and sending the OC instruction pulse to the peripheral OC chip so as to control the modulation power supply to power on and off the data transmission transmitter.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (6)
1. An on-board solid state storage system, comprising: the system comprises a main control CPU module arranged on a CPU, a storage control module arranged on an FPGA and an FLASH array; the FLASH array comprises a plurality of FLASH memories;
the main control CPU module is used for generating a configuration instruction according to the received instruction transmitted by the ground station and the data address in the FLASH array and sending the configuration instruction to the storage control module;
the storage control module is used for receiving a data source packet generated by a payload, performing Reed-Solomon code error correction coding on the data source packet, and storing the data source packet subjected to error correction coding in a plurality of FLASH memories;
the storage control module specifically comprises: the device comprises a combination input sub-module, a storage operation sub-module, a multiplexing output sub-module and an advanced peripheral bus bridge sub-module;
the combining input sub-module is used for receiving multi-path high-speed parallel data generated by an external effective load and satellite engineering parameters from an upper-layer satellite service computer; grouping the received multi-path high-speed parallel data, independently forming a data source packet by each group of data, carrying out Reed-Solomon code error correction coding on the data source packet, caching the data source packet after error correction coding, and obtaining the cached data source packet; outputting the cached data source packet to a storage operation submodule;
the storage operation submodule is used for initializing a FLASH memory in the FLASH array; the FLASH memory is also used for carrying out configuration, data writing, block allocation table organization, data erasing, mark invalidation and data playback operation on data addresses in the cached data source packet, obtaining the operated data source packet and storing the operated data source packet to a plurality of FLASH memories; extracting the corresponding error correction coded data source packet stored in the FLASH memory according to the received configuration instruction, performing Reed-Solomon code decoding processing on the error correction coded data source packet, and sending the decoded data source packet to a multiplexing output sub-module;
the multiplexing output submodule is used for carrying out data caching on the data source packet after the decoding processing, forming a data framing together with the file number and the time code and outputting the data framing to the data transmission transmitter;
and the advanced peripheral bus bridge submodule is used for finishing the communication between the CPU and the FPGA.
2. The satellite-borne solid-state storage system according to claim 1, wherein the CPU, the FPGA, and the FLASH array are connected by an advanced peripheral bus, and communication among the CPU, the FPGA, and the FLASH array is realized by the advanced peripheral bus; and an HPI interface is adopted between the CPU and the FPGA.
3. The on-board solid-state storage system according to claim 1, wherein the storage operation submodule specifically includes: the device comprises a high-level peripheral bus management unit, a combining input unit, a random access memory cache unit, a FLASH control unit, a block allocation table random access memory cache unit and a multiplexing output unit;
the advanced peripheral bus management unit is used for managing each unit in the storage control submodule;
the combining input unit is used for performing Reed-Solomon code error correction coding on the data source packet to obtain the data source packet after error correction coding, sending the data source packet after error correction coding into the asynchronous first-in first-out memory for caching, and sending the cached data source packet to the random access memory caching unit;
the random access memory cache unit is used for carrying out secondary cache on the cached data source packet and sending the data source packet after secondary cache to the FLASH control unit;
the FLASH control unit is used for respectively carrying out initialization and parameter configuration on a plurality of FLASH memories and storing error correction coded data source packets; the cache unit is also used for organizing the block allocation table information and sending the block allocation table information to the random access memory cache unit of the block allocation table; the data source package is also used for executing the operations of writing, replaying, erasing and marking invalid of the data source package after error correction coding to obtain the data source package after operation;
the block allocation table random access memory cache unit is used for storing the block allocation table information sent by the FLASH control unit and sending the block allocation table information to the high-level peripheral bus management unit;
the multiple output unit is used for decoding the error-correction coded data source packet output by the FLASH control unit by Reed-Solomon codes and writing the decoded data source packet into the asynchronous first-in first-out memory for caching.
4. The on-board solid-state storage system according to claim 3, wherein the FLASH control unit specifically comprises: the device comprises an initialization and parameter configuration subunit, a data writing subunit, an organization block allocation table subunit, a data erasing subunit, a marking invalid subunit and a data playback subunit;
the initialization and parameter configuration subunit is used for respectively performing initialization scanning on a plurality of FLASH memories in the FLASH array, generating corresponding FLASH bad block information, configuring configurable parameters of a storage system and configuring data addresses in the cached data source packet;
the data writing subunit is configured to write data in the cached data source packet according to the configured data address;
the organization block allocation table subunit is used for forming the FLASH bad block information generated in the initialization and parameter configuration subunit into block allocation table information, namely BAT information, and sending the BAT information to the block allocation table random access memory cache unit;
the data erasing subunit is used for erasing the initially written data when the FLASH memory is full of the data in the cached data source packet;
the marking invalid subunit is used for marking a certain block in the FLASH memory as an invalid block when the situation that the certain block cannot write or erase data in the FLASH memory is found in the process of writing or erasing the data; this block will be skipped the next time a write or erase operation is performed;
and the data playback subunit is used for extracting the corresponding data source packet after error correction coding stored in the FLASH memory according to the configuration instruction sent by the main control CPU module and outputting the data source packet after error correction coding to the multiplexing output unit.
5. The on-board solid state storage system of claim 4, wherein the FLASH control unit further comprises: a parameter configuration layer; the parameter configuration layer comprises: the device comprises a parameter configuration instruction analysis unit and a parameter configuration storage unit;
the parameter configuration instruction analysis unit is used for analyzing the configuration information of the data source packet stored in the FLASH;
and the parameter configuration storage unit is used for storing the analyzed parameter configuration instruction.
6. The spaceborne solid-state storage system according to claim 1, wherein an external interface is further arranged outside the storage control module and used for connecting and communicating with corresponding hardware;
the external interface includes: the device comprises a data input interface, a storage control interface, a transmission frame output interface, a controller local area network communication interface, an analog digital telemetering acquisition interface, a main control CPU unit interface, a pulse output control instruction output interface and a digital clock interface;
the data input interface is used for receiving data generated by a payload from the outside through a low-voltage differential signal chip; receiving a satellite engineering parameter packet from a satellite computer through an asynchronous RS422 receiving chip; forming a data source packet by data generated by the effective load and a satellite engineering parameter packet from a satellite computer;
the storage control interface is used for storing the data source packet subjected to error correction coding to a plurality of FLASH memories in the FLASH array according to the state bus, the control bus and the data bus;
the transmission frame output interface is used for framing and outputting the data to the data transmission transmitter through the low-voltage differential signal chip;
the controller local area network communication interface is used for receiving the data transmission instruction and the time code information sent by the house keeping computer; and the main control CPU module is also used for receiving a parameter configuration instruction sent by the main control CPU module.
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| CN113722770B (en) * | 2021-08-18 | 2024-06-18 | 上海励驰半导体有限公司 | End-to-end protection method and system based on hierarchical data integrity |
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