CN206075266U

CN206075266U - Multichannel ARINC429 Communication Cards

Info

Publication number: CN206075266U
Application number: CN201620798476.9U
Authority: CN
Inventors: 战仕成; 杜春雷; 史磊; 于晓菲
Original assignee: SNEFETECH Corp
Current assignee: SNEFETECH Corp
Priority date: 2016-07-27
Filing date: 2016-07-27
Publication date: 2017-04-05
Anticipated expiration: 2026-07-27

Abstract

The utility model is related to Data Transmission Controlling field, and in particular to a kind of multichannel ARINC429 Communication Cards.A kind of multichannel ARINC429 Communication Cards, which includes：Pci bus interface；The FPGA that reception and the information for sending can be processed；The bus switch of connection pci bus interface and FPGA；429 electrical level transferring chips can be connected with FPGA.Electrical level transferring chip is connected with communications connector.Parallel connection protection circuit between electrical level transferring chip and communications connector.FPGA completes the FIFO storages to receiving data by controlling SDRAM memory；FPGA completes the refreshing storage to receiving data by controlling SRAM memory.It is high that this sample card possesses Mode integrating degree, arrange flexibly, electrical isolation the features such as, can meet the upper layer application for becoming increasingly complex, and can preferably protection equipment.

Description

Multichannel ARINC429 Communication Cards

Technical field

The utility model is related to Data Transmission Controlling field, and in particular to a kind of multichannel ARINC429 Communication Cards.

Background technology

ARINC429 bus protocols are the US Airways electronic engineering committee (Airlines Engineering Committee) propose in July, 1977 and deliver and get the Green Light what is used.Its full name is digital information Transmission system (DITS).Consensus standard defines avionic device and requires about the digital information transmission between system.

ARINC429 bus structures are simple, stable performance, strong interference immunity.Maximum advantage is that reliability is high, and this is As decentralized control, transmission are reliable, mistake isolation is good.

As the bus form of the smart machine of mutual commissure in air equipment is realized in the way of isa bus mostly, this Problem with regard to bringing the design of the ARINC429 serial bus interface IPs in isa bus microsystem, in addition, pci interface pair Processing speed of the process of data far faster than ISA.

Utility model content

The purpose of this utility model is under above-mentioned reality, there is provided a kind of multichannel ARINC429 communication cards.

Multichannel ARINC429 Communication Cards of the present utility model are namely based on what the standard of ARINC429 buses was developed.Its Main principle is that the realization of 429 agreements is completed using FPGA, HI-8592PSTF and HI-8588-PSI chips complete 429 signals Level conversion be received and transmitted with realizing bus data.During data is activation, first then caching is encoded by FPGA, so Sent by sendaisle afterwards.During data receiver, decoding storage is carried out by FPGA first and then is read for computer.

Specifically, it is to realize object above, the utility model can adopt following scheme.

A kind of multichannel ARINC429 Communication Cards, it is characterised in that the board includes：Pci bus interface；Can be right The FPGA processed by the information for receiving and sending；Connect the bus switch of the pci bus interface and the FPGA；Can 429 electrical level transferring chips being connected with the FPGA.

Preferably, 429 electrical level transferring chip is connected with communications connector, 429 electrical level transferring chip with it is described Parallel connection protection circuit between communications connector.

Preferably, the FPGA is connected with FIFO storage chips.

Preferably, the FPGA is included No. 16 transmitter FIFO and is communicated to connect with SDRAM receivers FIFO.

Preferably, the FPGA is communicated in the way of it can realize the storage of 16 circuit-switched datas with the SDRAM receivers FIFO Connection.

Preferably, the FPGA is connected with storage chip is refreshed.

Preferably, the FPGA and SRAM receivers are can realize communicating to connect in the way of 16 circuit-switched datas refresh storage.

Preferably, the FPGA is connected with input and output triggering clock.

Preferably, the input and output triggering clock includes isolating device.

Preferably, the transmission level conversion chip of 429 electrical level transferring chip is HI-8592PSTF chips；Described 429 The reception electrical level transferring chip of electrical level transferring chip is HI-8588-PSI chips；The communications connector is ARINC429 buses Interface.

Wherein, FPGA completes the FIFO storages to receiving data by controlling SDRAM memory；FPGA is by controlling SRAM Memory completes the refreshing to receiving data and stores.

Alternatively, the FPGA is communicated with SDRAM receiver FIFO and realizes that 16 circuit-switched datas are stored.

Preferably, the input and output ARINC429 signals connect protection circuit.

It is high that multichannel ARINC429 Communication Cards of the present utility model possess Mode integrating degree, arrange flexibly, electrically every From the features such as, can meet the upper layer application for becoming increasingly complex, and can preferably protection equipment.

Description of the drawings

Fig. 1 is the positive structure schematic of multichannel ARINC429 Communication Cards of the present utility model.

Fig. 2 is the reverse structure schematic of multichannel ARINC429 Communication Cards of the present utility model.

Fig. 3 is another structural representation of multichannel ARINC429 Communication Cards of the present utility model.

Specific embodiment

This board is a ARINC429 interface communication boards based on pci bus.33MHZ/32bits PCI are total for configuration Line interface.There is provided during transmission and meet the data form for requiring, including the renewal of data, the verification mode of data, the length of data bit Degree, the setting of baud rate, the selection of interior external trigger.SD and label are filtered during reception selection design, 32 bit data formats turn Change, receive addition markers, then data are stored in SDRAM by FIFO forms, SRAM are stored in and are supplied PC by refreshing form Read.

Principle of the present utility model and illustrative embodiments are illustrated referring to Fig. 1 to Fig. 3.

Fig. 1 is the positive structure schematic of multichannel ARINC429 Communication Cards of the present utility model.Fig. 2 is that this practicality is new The reverse structure schematic of the multichannel ARINC429 Communication Cards of type.

In FIG, mark 1 represents bus switch (BUS SWITCH), and which is, for example, SN74CBTD16210DGGR, bears Signal level between duty conversion pci bus interface 5 and FPGA 2.At the main information to receiving and sending of FPGA 2 Reason.Mark 3 represents the storage chip of FIFO.Mark 4 represents the storage chip for refreshing.Mark 6 represents that bus receives level conversion Chip, which is, for example, SN74ALVC164245DGGR.Mark 7 represents protection circuit.Mark 8 represents communications connector, is responsible for The reception and transmission of ARINC429 data.Mark 9 represents ARINC429 received signal level conversion chips.Mark 10 is represented ARINC429 sending signal electrical level transferring chips.Mark 11 represents input and output triggering clock.The size of the board is, for example, 174.63mm×98.43mm。

In figure 3, mark 5 represents pci bus interface, and mark 2 represents FPGA controller, and mark 3 represents No. 16 receivers The storage chip of FIFO, i.e. SDRAM, mark 4 represent that receiver refreshes SRAM, and mark 10 represents ARINC429 dispensing devices, mark Note 18 represents incoming level conversion equipment, and mark 7 represents input, output protecting device, when mark 11 represents that input and output are triggered Clock, which has isolating device.Mark 8 represents communications connector.More specifically, input and output triggering clock 11 includes and communication link 16 tunnel external trigger inputs, optical coupling isolation device and the driver of the connection of device 8 are connect, driver is connected to FPGA controller 2.Input is defeated Go out to trigger optical coupling isolation device and 16 tunnel internal trigger outputs that clock 11 also includes being connected with FPGA controller 2, touch in 16 tunnel Send out output to be connected with communications connector.

Multichannel ARINC429 Communication Cards of the present utility model can include：Pci bus interface 5；Can to receive and The FPGA 2 processed by the information of transmission；The bus switch 1 of connection pci bus interface 5 and FPGA 2；Can be with FPGA 2 Connection and the chip 9,10 that ARINC429 data levels can be changed.

Preferably, electrical level transferring chip 9,10 is connected with a communications connector 8.

Preferably, FPGA 2 is connected with FIFO storage chips 3.

Preferably, FPGA 2 is included 16 mouthfuls of transmitter FIFO and can be communicated with the SDRAM 3 of 16 mouthfuls of receiver FIFO.

Preferably, FPGA 2 is connected with storage chip 4 is refreshed.

Preferably, FPGA 2 is connected with input and output triggering clock 11.

Preferably, input and output triggering clock 11 includes isolating device, it is preferable that the isolating device is filled for light-coupled isolation Put.

The mode of operation of board of the present utility model is illustrated below.

The transmission process of data is as follows：

Data write to be sent is sent into FIFO first, by a series of parsings inside FPGA 2 and control by one The data of 32bit complete serioparallel exchange into ARINC429 data forms.By transmission level conversion chip HI-8592PSTF by electricity Flat turn is changed to ARINC429 level serials and sends to ARINC429 buses.

The reception process of data is as follows：

For the serial data in bus, needs first pass through reception electrical level transferring chip HI-8588-PSI and complete Then data are entered FPGA 2, after 17 switching levels of driver by FPGA 2 by data by ARINC429 level conversions Reception FIFO is write data into after process and refreshes SRAM, processing procedure includes filtration, the word lattice of 32 data of SD and label Formula conversion, the markers addition of receiving data.

Multichannel ARINC429 Communication Cards of the present utility model can be for example widely used in advanced airline carriers of passengers, Such as B-737, B757, B-767, Russian military aircraft also can select similar technology.

The one of real work checking and client with confidentiality obligations of the board of the present utility model through applicant more than 1 year The periodically use of limit, work are good, disclosure satisfy that the demand under varying environment.

Above with reference to preferred embodiment of the present utility model has been illustrated, it is understood, however, that described above is only Exemplary.Those skilled in the art can be on the premise of without departing from spirit and scope of the present utility model, to this practicality It is new that various modification can be adapted and modification.Protection domain of the present utility model is limited by the accompanying claims.

Claims

1. a kind of multichannel ARINC429 Communication Cards, it is characterised in that the board includes：Pci bus interface；Can dock The FPGA processed by the information received and send；Connect the bus switch of the pci bus interface and the FPGA；Can be with 429 electrical level transferring chips of the FPGA connections.

2. multichannel ARINC429 Communication Cards according to claim 1, it is characterised in that

429 electrical level transferring chip is connected with communications connector, 429 electrical level transferring chip and the communications connector it Between parallel connection protection circuit.

3. multichannel ARINC429 Communication Cards according to claim 1, it is characterised in that

The FPGA is connected with FIFO storage chips.

4. multichannel ARINC429 Communication Cards according to claim 3, it is characterised in that

The FPGA is included No. 16 transmitter FIFO and is communicated to connect with SDRAM receivers FIFO.

5. multichannel ARINC429 Communication Cards according to claim 4, it is characterised in that

The FPGA and SDRAM receivers FIFO is can realize communicating to connect in the way of 16 circuit-switched datas are stored.

6. multichannel ARINC429 Communication Cards according to any one of claim 1 to 5, it is characterised in that

The FPGA is connected with storage chip is refreshed.

7. multichannel ARINC429 Communication Cards according to claim 6, it is characterised in that

The FPGA and SRAM receivers are can realize communicating to connect in the way of 16 circuit-switched datas refresh storage.

8. multichannel ARINC429 Communication Cards according to any one of claim 1 to 5, it is characterised in that

The FPGA is connected with input and output triggering clock.

9. multichannel ARINC429 Communication Cards according to claim 8, it is characterised in that

The input and output triggering clock includes isolating device.

10. multichannel ARINC429 Communication Cards according to claim 2, it is characterised in that

The transmission level conversion chip of 429 electrical level transferring chip is HI-8592PSTF chips；The 429 level conversion core The reception electrical level transferring chip of piece is HI-8588-PSI chips；The communications connector is ARINC429 EBIs.