CN108493159A - The manufacturing method of grid - Google Patents
The manufacturing method of grid Download PDFInfo
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- CN108493159A CN108493159A CN201810330450.5A CN201810330450A CN108493159A CN 108493159 A CN108493159 A CN 108493159A CN 201810330450 A CN201810330450 A CN 201810330450A CN 108493159 A CN108493159 A CN 108493159A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
The invention discloses a kind of manufacturing methods of grid, including step：Step 1: forming gate dielectric layer and polysilicon gate；Step 2: forming hard mask layers；Step 3: chemical wet etching forms multiple grids；Step 4: forming the side wall being made of nitration case in the side of grid；Step 5: the hard mask layers at the top of removal polysilicon gate；Step 6: forming the contact hole etching stop-layer being made of nitration case；Step 7: forming the interlayer film being made of oxide layer；Step 8: carrying out carrying out interlayer film thinned first time chemical mechanical grinding by stop-layer of contact hole etching stop-layer；Step 9: carrying out being stop-layer using polysilicon gate while second of chemical mechanical grinding for being ground contact hole etching stop layer, side wall and interlayer film and the planarization for realizing grid.The present invention can improve the height control between first layer interlayer film and grid after grid, improve the high consistency between first layer interlayer film and polysilicon gate.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture methods, more particularly to a kind of manufacturing method of grid.
Background technology
In existing advanced logic chip technique, original paper generally includes n type field effect transistor (FET) i.e. nFET and p-type field
Effect transistor, that is, pFET can additionally carry out original paper enhancing work to increase original paper electrical performance outside the technique of pFET or nFET
Skill.These original paper enhancing techniques will have a direct impact on gate height between follow-up various different original papers, cause between follow-up different original papers
The difference of gate height and to influence original paper electrical.It is the device junction composition in each step of existing method as shown in Figure 1A to Fig. 1 D,
The manufacturing method of existing grid includes the following steps：
Step 1: as shown in Figure 1A, providing semi-conductive substrate 101, being sequentially formed on 101 surface of the semiconductor substrate
Gate dielectric layer and polysilicon gate 103.
The semiconductor substrate 101 is silicon substrate.The gate dielectric layer is gate oxide.In the semiconductor substrate 101
In be formed with field oxide 102, active area is isolated by the field oxide 102.The field oxide 102 is shallow trench field
Oxygen is formed using shallow ditch groove separation process.
The active area includes the corresponding active area of the corresponding active area of nucleus and input and output region.
The corresponding original paper of the grid includes core original paper and input and output original paper.The original paper is field-effect transistor.
The original paper includes n type field effect transistor and p-type field effect transistor.Core nFET201, core are shown in Figure 1A
PFET202, input and output nFET203, input and output pFET204.
Step 2: forming hard mask layers on the surface of the polysilicon gate 103.
The hard mask layers are made of nitration case.
Step 3: carrying out chemical wet etching forms multiple grids, each grid is by the gate dielectric layer, described after etching
Polysilicon gate 103 and the hard mask layers are formed by stacking.
Step 4: forming the side wall 104 being made of nitridation layer material in the side of each grid.
The side wall 104 further includes forming original on 101 surface of the semiconductor substrate of the grid both sides after being formed
The step of source region of part and drain region.
Include original paper enhancing technique during forming source region and the drain region of the original paper, the original paper enhancing technique makes
The height of the grid of the corresponding original paper reduces, and increases the difference in height between each grid.In existing, the original paper enhancing
Technique is germanium silicon technology.The original paper enhancing technique forms germanium silicon layer in the source region of the p-type field effect transistor or drain region
105.Such that the corresponding gate structure of p-type field effect transistor gate structure corresponding compared with n type field effect transistor is short,
As shown in the AA lines in Figure 1A.
Step 5: removing the hard mask layers at 103 top of the polysilicon gate, the side wall 104, which has, to be protruded
The protrusion structure at 103 top of the polysilicon gate.Equally, there is difference in height, such as Figure 1A between the top surface of the side wall 104
In BB lines shown in, the height of the top surface of the side wall 104 of core nFET201 and input and output nFET203 is higher than core
The height of the top surface of the side wall 104 of heart pFET202 and input and output pFET204.
The hard mask layers generally use photoresist for removing 103 top of the polysilicon gate returns quarter (PR etching
Back, PREB) technique realization.PREB is first to be coated with a layer photoresist i.e. photoresist, then to photoresist carve, the light of Hui Kehou
It hinders in the interval region between grid, later covers the hard at all 103 tops of polysilicon gate using photoresist as autoregistration mask
Mold layer removes.
Step 6: as shown in Figure 1B, forming the contact hole etching stop-layer 106 being made of nitration case, the contact hole is carved
Erosion stop-layer 106 be covered in 103 surface of the polysilicon gate, the side wall 4 protrusion structure surface and the side wall 104
Protrusion structure under the side wall 104 side and the grid between 101 surface of the semiconductor substrate.
Step 7: as shown in Figure 1 C, the interlayer film 107 that is made of oxide layer is formed, the interlayer film 107 is by the grid
Between gap be filled up completely and extend to the top of the grid.
Step 8: as shown in figure iD, carrying out chemical mechanical grinding, the lapping liquid of the chemical mechanical grinding is to oxide layer
Selection ratio is more than the selection ratio to nitration case, and the secondary chemical mechanical grinding described in this way is with the contact hole etching stop-layer 106
Stop-layer to the interlayer film 107 be thinned and reveals 106 surface of contact hole etching stop-layer of the top portions of gates
Go out.After the chemical mechanical milling tech of interlayer film 107, the apparent height of the interlayer film 107 is simultaneously uneven, such as BB lines institute
Show；Uneven reason is mainly by the difference in height between the corresponding grid in Fig. 3 A, exactly because there is height between grid
Degree is poor, just makes the apparent height of the last interlayer film 107 uneven.
Invention content
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of grid, can improve the first layer after grid
Height control between interlayer film and grid, improves the high consistency between first layer interlayer film and polysilicon gate.
In order to solve the above technical problems, the manufacturing method of grid provided by the invention includes the following steps：
Step 1: providing semi-conductive substrate, gate dielectric layer and polysilicon are sequentially formed in the semiconductor substrate surface
Grid.
Step 2: forming hard mask layers on the surface of the polysilicon gate.
Step 3: carrying out chemical wet etching forms multiple grids, each grid is by the gate dielectric layer, described after etching
Polysilicon gate and the hard mask layers are formed by stacking.
Step 4: forming the side wall being made of nitridation layer material in the side of each grid.
Step 5: removing the hard mask layers at the top of the polysilicon gate, the side wall has prominent described more
Protrusion structure at the top of crystal silicon grid.
Step 6: forming the contact hole etching stop-layer being made of nitration case, the contact hole etching stop-layer is covered in
The surface of the protrusion structure of the polycrystalline silicon gate surface, the side wall and the side wall under the protrusion structure of the side wall
The semiconductor substrate surface between side and the grid.
Step 7: forming the interlayer film being made of oxide layer, the interlayer film fills out in the gap between the grid completely
Fill and extend to the top of the grid.
Step 8: carrying out first time chemical mechanical grinding, the lapping liquid of the first time chemical mechanical grinding is to oxide layer
Selection than being more than to the selection ratio of nitration case, make the first time chemical mechanical grinding be with the contact hole etching stop-layer
Stop-layer be thinned and the contact hole etching of the top portions of gates is stopped layer surface exposing to the interlayer film.
Step 9: carrying out second of chemical mechanical grinding, the lapping liquid of second of chemical mechanical grinding is to nitration case
Selection with oxide layer makes second of chemical mechanical grinding with described more than identical and both greater than to the selection ratio of polysilicon
Crystal silicon grid are stop-layer simultaneously to being stopped by the contact hole etching that nitration case forms higher than the polysilicon gate top surface
Only layer and the side wall and the planarization for realizing the grid is ground by the interlayer film that oxide layer forms.
A further improvement is that the hard mask layers are made of nitration case.
A further improvement is that the semiconductor substrate is silicon substrate.
A further improvement is that the gate dielectric layer is gate oxide.
A further improvement is that field oxide is formed in the semiconductor substrate that step 1 provides, by the field oxygen
Change layer and isolates active area.
A further improvement is that the active area includes that the corresponding active area of nucleus and input and output region are corresponding
Active area.
A further improvement is that the corresponding original paper of the grid includes core original paper and input and output original paper.
A further improvement is that the original paper is field-effect transistor.
A further improvement is that the original paper includes n type field effect transistor and p-type field effect transistor.
A further improvement is that it further includes partly being led in the described of the grid both sides that the side wall of step 4, which is formed later,
Body substrate surface forms the step of source region and drain region of original paper.
A further improvement is that including original paper enhancing technique, institute during forming source region and the drain region of the original paper
Stating original paper enhancing technique makes the height of the grid of the corresponding original paper reduce, and increases the difference in height between each grid.
A further improvement is that the original paper enhancing technique is germanium silicon technology.
A further improvement is that the original paper enhancing technique is formed in the source region of the p-type field effect transistor or drain region
Germanium silicon layer.
A further improvement is that the field oxide is shallow trench field oxygen, formed using shallow ditch groove separation process.
A further improvement is that the lapping liquid of second of chemical mechanical grinding described in step 9 is to nitration case, oxide layer
With polysilicon to select to compare be 5:5:1.
After first layer interlayer film of the present invention after grid is formed, the chemical machinery that lapping liquid is different twice is carried out and has ground
Mill, the lapping liquid of first time chemical mechanical grinding than being more than the selection ratio to nitration case, can thus lead to the selection of oxide layer
It crosses first time chemical mechanical grinding and interlayer film be thinned and by top portions of gates using contact hole etching stop-layer as stop-layer
Contact hole etching stop layer surface expose；Later, be then ground liquid to the selection of nitration case and oxide layer than identical and
Both greater than to second of chemical mechanical grinding of the selection ratio of polysilicon, the polysilicon gate top surface can thus will be above
Nitration case include contact hole etching stop-layer and side wall and oxide layer includes that interlayer film all removes, to can finally make interlayer
The surface of film is equal with the surface of polysilicon gate, namely the present invention can improve between first layer interlayer film and grid after grid
Height controls, and improves the high consistency between first layer interlayer film and polysilicon gate；Even if in the grid knot of different original papers
When having larger difference in height between structure, the height that the grid of the PMOS tube of germanium silicon layer such as is formed in source and drain can be less than not having
The height of the grid of the NMOS tube of germanium silicon layer can eliminate the influence of the gate height in each region using the present invention, finally so that not
It is all consistent with the interlayer film in region and the height of polysilicon gate, improve flattening effect.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Figure 1A-Fig. 1 D are the device junction compositions in each step of manufacturing method of existing grid；
Fig. 2 is the flow chart of present invention method；
Fig. 3 A- Fig. 3 D are the device junction compositions in each step of present invention method.
Specific implementation mode
As shown in Fig. 2, being the flow chart of present invention method；It is the embodiment of the present invention as shown in Fig. 3 A to Fig. 3 D
Device junction composition in each step of method, the manufacturing method of grid of the embodiment of the present invention include the following steps：
Step 1: as shown in Figure 3A, providing semi-conductive substrate 1, sequentially forming grid on 1 surface of the semiconductor substrate is situated between
Matter layer and polysilicon gate 3.
The semiconductor substrate 1 is silicon substrate.The gate dielectric layer is gate oxide.The shape in the semiconductor substrate 1
At there is field oxide 2, active area is isolated by the field oxide 2.The field oxide 2 is shallow trench field oxygen, using shallow ridges
Slot isolation technology is formed.
The active area includes the corresponding active area of the corresponding active area of nucleus and input and output region.
The corresponding original paper of the grid includes core original paper and input and output original paper.The original paper is field-effect transistor
(FET).The original paper includes n type field effect transistor and p-type field effect transistor.In Fig. 3 A show core nFET301,
Core pFET302, input and output nFET303, input and output pFET304.
Step 2: forming hard mask layers on the surface of the polysilicon gate 3.
The hard mask layers are made of nitration case.
Step 3: carrying out chemical wet etching forms multiple grids, each grid is by the gate dielectric layer, described after etching
Polysilicon gate 3 and the hard mask layers are formed by stacking.
Step 4: forming the side wall 4 being made of nitridation layer material in the side of each grid.
The side wall 4 further includes forming original paper on 1 surface of the semiconductor substrate of the grid both sides after being formed
The step of source region and drain region.
Include original paper enhancing technique during forming source region and the drain region of the original paper, the original paper enhancing technique makes
The height of the grid of the corresponding original paper reduces, and increases the difference in height between each grid.It is described in the embodiment of the present invention
It is germanium silicon technology that original paper, which enhances technique,.The original paper enhancing technique is formed in the source region of the p-type field effect transistor or drain region
Germanium silicon layer 5.Such that the corresponding gate structure of p-type field effect transistor grid knot corresponding compared with n type field effect transistor
Structure is short, as shown in the CC lines in Fig. 3 A.
Step 5: removing the hard mask layers at 3 top of the polysilicon gate, the side wall 4 has prominent described
The protrusion structure at 3 top of polysilicon gate.Equally, there is difference in height, such as the CC lines in Fig. 3 A between the top surface of the side wall 4
It is shown, the height of the top surface of the side wall 4 of core nFET301 and input and output nFET303 higher than core pFET302 and
The height of the top surface of the side wall 4 of input and output pFET304.
The hard mask layers generally use photoresist for removing 3 top of the polysilicon gate returns carving technology realization.PREB is
It is first coated with a layer photoresist i.e. photoresist, then photoresist carve, the interval region of the photoresist of Hui Kehou between grid
In, the hard mask layers at all 3 tops of polysilicon gate are removed using photoresist as autoregistration mask later.
Step 6: as shown in Figure 3B, forming the contact hole etching stop-layer 6 being made of nitration case, the contact hole etching
Stop-layer 6 is covered in 3 surface of the polysilicon gate, the surface of protrusion structure of the side wall 4 and the prominent of the side wall 4 and ties
1 surface of the semiconductor substrate between the side and the grid of the side wall 4 under structure.
Step 7: as shown in Figure 3 C, forming the interlayer film 7 being made of oxide layer, the interlayer film 7 will be between the grid
Gap be filled up completely and extend to the top of the grid.
Step 8: carrying out first time chemical mechanical grinding, the lapping liquid of the first time chemical mechanical grinding is to oxide layer
Selection than being more than to the selection ratio of nitration case, make the first time chemical mechanical grinding with the contact hole etching stop-layer 6
The interlayer film 7 be thinned for stop-layer and exposes 6 surface of contact hole etching stop-layer of the top portions of gates.
Step 9: as shown in Figure 3D, carrying out second of chemical mechanical grinding, the grinding of second of chemical mechanical grinding
Liquid than identical and both greater than to the selection ratio of polysilicon, makes second of chemical machinery grind the selection of nitration case and oxide layer
Mill is stop-layer simultaneously to described in being made of nitration case higher than 3 top surface of the polysilicon gate with the polysilicon gate 3
It contact hole etching stop-layer 6 and the side wall 4 and is ground by the interlayer film 7 that oxide layer forms and realizes the grid
Planarization.
The lapping liquid of second of chemical mechanical grinding to nitration case, oxide layer and polysilicon to select to compare be 5:5:1.
After first layer interlayer film 7 of the embodiment of the present invention after grid is formed, the change that lapping liquid is different twice has been carried out
Mechanical lapping is learned, the lapping liquid of first time chemical mechanical grinding is more than the selection ratio to nitration case to the selection ratio of oxide layer, this
Sample can be that stop-layer to interlayer film 7 be thinned simultaneously by first time chemical mechanical grinding and with contact hole etching stop-layer 6
6 surface of contact hole etching stop-layer of top portions of gates is exposed；Later, then it is ground choosing of the liquid to nitration case and oxide layer
It selects than second of chemical mechanical grinding identical and both greater than to the selection ratio of polysilicon, can thus will be above the polysilicon
The nitration case of 3 top surface of grid includes contact hole etching stop-layer 6 and side wall 4 and oxide layer includes that interlayer film 7 all removes, from
And can finally make the surface of interlayer film 7 equal with the surface of polysilicon gate 3 namely the embodiment of the present invention can improve after grid
Height control between from level to level between film 7 and grid, improves the consistent of the height between first layer interlayer film 7 and polysilicon gate 3
Property；Even if there is larger difference in height between the gate structure of different original papers, the PMOS of germanium silicon layer 5 is such as formed in source and drain
The height of the grid of pipe can be less than the height of the grid of the NMOS tube without germanium silicon layer 5, can be eliminated using the embodiment of the present invention
The influence of the gate height in each region improves finally so that the interlayer film 7 of different zones and the height of polysilicon gate 3 are all consistent
Flattening effect.
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of manufacturing method of grid, which is characterized in that include the following steps：
Step 1: providing semi-conductive substrate, gate dielectric layer and polysilicon gate are sequentially formed in the semiconductor substrate surface；
Step 2: forming hard mask layers on the surface of the polysilicon gate；
Step 3: carrying out chemical wet etching forms multiple grids, each grid is by the gate dielectric layer, the polycrystalline after etching
Si-gate and the hard mask layers are formed by stacking；
Step 4: forming the side wall being made of nitridation layer material in the side of each grid；
Step 5: removing the hard mask layers at the top of the polysilicon gate, the side wall has prominent in the polysilicon
Protrusion structure at the top of grid；
Step 6: forming the contact hole etching stop-layer being made of nitration case, the contact hole etching stop-layer is covered in described
The surface of the protrusion structure of polycrystalline silicon gate surface, the side wall and the side of the side wall under the protrusion structure of the side wall
And the semiconductor substrate surface between the grid；
Step 7: forming the interlayer film being made of oxide layer, the gap between the grid is filled up completely simultaneously by the interlayer film
Extend to the top of the grid；
Step 8: first time chemical mechanical grinding is carried out, the choosing of the lapping liquid of the first time chemical mechanical grinding to oxide layer
It selects than more than the selection ratio to nitration case, making the first time chemical mechanical grinding with the contact hole etching stop-layer for stopping
Layer be thinned and the contact hole etching of the top portions of gates is stopped layer surface exposing to the interlayer film；
Step 9: carrying out second of chemical mechanical grinding, the lapping liquid of second of chemical mechanical grinding is to nitration case and oxygen
Change the selection of layer than identical and both greater than to the selection ratio of polysilicon, makes second of chemical mechanical grinding with the polysilicon
Grid are stop-layer simultaneously to the contact hole etching stop-layer being made of nitration case higher than the polysilicon gate top surface
The interlayer film formed with the side wall and by oxide layer is ground the planarization for realizing the grid.
2. the manufacturing method of grid as described in claim 1, it is characterised in that：The hard mask layers are made of nitration case.
3. the manufacturing method of grid as described in claim 1, it is characterised in that：The semiconductor substrate is silicon substrate.
4. the manufacturing method of grid as described in claim 1, it is characterised in that：The gate dielectric layer is gate oxide.
5. the manufacturing method of grid as described in claim 1, it is characterised in that：In the semiconductor substrate that step 1 provides
It is formed with field oxide, active area is isolated by the field oxide.
6. the manufacturing method of grid as claimed in claim 5, it is characterised in that：The active area includes that nucleus is corresponding
The corresponding active area of active area and input and output region.
7. the manufacturing method of grid as claimed in claim 6, it is characterised in that：The corresponding original paper of the grid includes core original
Part and input and output original paper.
8. the manufacturing method of grid as claimed in claim 7, it is characterised in that：The original paper is field-effect transistor.
9. the manufacturing method of grid as claimed in claim 8, it is characterised in that：The original paper includes n type field effect transistor
And p-type field effect transistor.
10. the manufacturing method of grid as claimed in claim 9, it is characterised in that：The side wall of step 4 is gone back after being formed
The step of being included in source region and the drain region of the semiconductor substrate surface formation original paper of the grid both sides.
11. the manufacturing method of grid as claimed in claim 10, it is characterised in that：In source region and the drain region for forming the original paper
During include original paper enhancing technique, the original paper enhancing technique makes the height reduction of the grid of the corresponding original paper, increasing
Add the difference in height between each grid.
12. the manufacturing method of grid as claimed in claim 11, it is characterised in that：The original paper enhancing technique is germanium silicon work
Skill.
13. the manufacturing method of grid as claimed in claim 12, it is characterised in that：The original paper enhances technique in the p-type
The source region of field-effect transistor or drain region form germanium silicon layer.
14. the manufacturing method of grid as claimed in claim 5, it is characterised in that：The field oxide is shallow trench field oxygen, is adopted
It is formed with shallow ditch groove separation process.
15. the manufacturing method of grid as described in claim 1, it is characterised in that：Second of chemical machinery described in step 9
The lapping liquid of grinding to nitration case, oxide layer and polysilicon to select to compare be 5:5:1.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109637927A (en) * | 2018-12-12 | 2019-04-16 | 上海华力集成电路制造有限公司 | The manufacturing method of metal gate |
| CN110148552A (en) * | 2019-04-15 | 2019-08-20 | 上海华力集成电路制造有限公司 | The manufacturing method of level 0 interlayer film |
| CN110391184A (en) * | 2019-07-24 | 2019-10-29 | 上海华力集成电路制造有限公司 | The manufacturing method of level 0 interlayer film |
| CN110473834A (en) * | 2019-08-29 | 2019-11-19 | 上海华力集成电路制造有限公司 | The manufacturing method of grid |
| CN111199879A (en) * | 2018-11-19 | 2020-05-26 | 中芯国际集成电路制造（天津）有限公司 | Method for flattening grid structure |
| CN114038752A (en) * | 2021-10-09 | 2022-02-11 | 上海华力集成电路制造有限公司 | High-voltage MOSFET device and manufacturing method thereof |
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