CN108695259A - The manufacturing method of MOS transistor with HKMG - Google Patents
The manufacturing method of MOS transistor with HKMG Download PDFInfo
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- CN108695259A CN108695259A CN201810486162.9A CN201810486162A CN108695259A CN 108695259 A CN108695259 A CN 108695259A CN 201810486162 A CN201810486162 A CN 201810486162A CN 108695259 A CN108695259 A CN 108695259A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Abstract
The invention discloses a kind of manufacturing methods of the MOS transistor with HKMG, including step:Step 1: forming pseudo- grid structure until forming interlayer film and planarizing;The region of PMOS is opened Step 2: forming the first photoetching offset plate figure;Step 3: the dummy poly grid in the region of removal PMOS;Step 4: forming corresponding first work-function layers of PMOS;The region of NMOS is opened Step 5: forming the second photoetching offset plate figure;Step 6: the first work-function layer in the region of removal NMOS and dummy poly grid;Step 7: forming corresponding second work-function layers of NMOS;Step 8: forming the metal material layer of metal gate;Step 9: being planarized to metal material layer.The present invention can remove dummy poly grid well, eliminate defect caused by the etching load difference of the dummy poly grid of different height.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, more particularly to a kind of MOS transistor with HKMG
Manufacturing method.
Background technology
HKMG has the gate dielectric layer and metal gate (MG) of high-k (HK), therefore is commonly abbreviated as in this field
HKMG.In existing method, the making technology node of HKMG reaches 28nm or less.
In existing method, the dummy poly grid in each region remove simultaneously, before removing dummy poly grid, front layer due to
Manufacturing process different with PFET, that is, PMOS NFET, that is, NMOS can cause polysilicon gate height (gate between NFET and PFET
High) there is load (loading).In the case where the process window (window) of the CMP of interlayer film is inadequate, in certain figures
It (pattern) may be by the SiN even residual of Oxide, that is, oxide layer, so as to cause some defects (defect) on.
Invention content
Technical problem to be solved by the invention is to provide a kind of manufacturing methods of the MOS transistor with HKMG, can be very
Good removal dummy poly grid eliminate defect caused by the etching load difference of the dummy poly grid of different height.
In order to solve the above technical problems, the manufacturing method of the MOS transistor provided by the invention with HKMG includes as follows
Step:
Step 1: MOS transistor includes NMOS and PMOS, pseudo- grid structure, the source of NMOS are formed in semiconductor substrate surface
Drain region, the source-drain area of PMOS, side wall, contact hole etching stop-layer and interlayer film, dummy gate structure are more by gate dielectric layer and puppet
Crystal silicon grid are formed by stacking;The interlayer film is planarized using chemical mechanical milling tech, the chemical mechanical grinding work
Skill exposes the surface of the dummy poly grid.
Step 2: carrying out first time photoetching process forms the first photoetching offset plate figure by the locality protection of the NMOS, by institute
It opens in the region for stating PMOS.
Step 3: the dummy poly grid in removing the region of the PMOS, remove the first photoresist figure later
Shape.
Step 4: forming the first work-function layer, first work-function layer is the work-function layer of PMOS.
Step 5: carrying out second of photoetching process forms the second photoetching offset plate figure by the locality protection of the PMOS, by institute
It opens in the region for stating NMOS.
Step 6: first work-function layer in removing the region of the NMOS and the dummy poly grid, go later
Except second photoetching offset plate figure.
Step 7: forming the second work-function layer, second work-function layer is the work-function layer of NMOS, the PMOS's
In region, second work-function layer is superimposed upon the surface of first work-function layer.
Step 8: forming the metal material layer of metal gate.
It is formed Step 9: carrying out planarization to the metal material layer using chemical mechanical milling tech by being filled in
The metal gate of the metal material layer composition in dummy poly grid removal region;The HKMG of the PMOS includes by institute
State the structure that gate dielectric layer, first work-function layer, second work-function layer and the metal gate are formed by stacking;It is described
The HKMG of NMOS includes the structure being formed by stacking by the gate dielectric layer, second work-function layer and the metal gate.
A further improvement is that the semiconductor substrate is silicon substrate.
A further improvement is that the material of the side wall includes silicon oxide or silicon nitride.
A further improvement is that the material of the contact hole etching stop-layer is silicon nitride.
A further improvement is that the material of the interlayer film is silica.
A further improvement is that the material that first work-function layer is is TiN, the material that second work-function layer is
For TiAl.
A further improvement is that the gate dielectric layer includes high dielectric constant layer.
A further improvement is that the gate dielectric layer further includes boundary layer, the boundary layer is located at the high-k
Between layer and semiconductor substrate.
A further improvement is that the material of the boundary layer includes silica.
A further improvement is that the material of the high dielectric constant layer includes silica, and silicon nitride, alundum (Al2O3),
Tantalum pentoxide, yttrium oxide, hafnium silicate oxygen compound, hafnium oxide, lanthana, zirconium dioxide, strontium titanates, zirconium silicate oxidation are closed
Object.
A further improvement is that being formed with channel region and described by the semiconductor substrate surface that the HKMG is covered
The surface of channel region is used to form raceway groove, and the length of the raceway groove is 28nm or less.
A further improvement is that the channel region of the PMOS tube is n-type doping, the source-drain area of the PMOS be P+ adulterate and
The source-drain area of the PMOS is located at the both sides of the corresponding HKMG.
A further improvement is that being formed with embedded germanium silicon epitaxial layer in the source-drain area of the PMOS.
A further improvement is that the channel region of the NMOS tube is p-type doping, the source-drain area of the NMOS be N+ adulterate and
The source-drain area of the NMOS is located at the both sides of the corresponding HKMG.
A further improvement is that the metal material layer of the metal gate is Al.
When being removed to dummy poly grid it is not to carry out region-wide i.e. NMOS area and PMOS area in the present invention
Dummy poly grid remove simultaneously, but the method for using lithographic definition, and first photoetching opens PMOS area and removes PMOS area
Dummy poly grid are forming corresponding first work-function layers of PMOS later;It uses photoetching to open NMOS area again later, goes later
Except the first work-function layer and dummy poly grid of NMOS area;It is further continued for corresponding second work functions of subsequent formation NMOS later
And formation and the chemical mechanical milling tech technique of the metal material layer of metal gate;As can be seen that due to the present invention's
The dummy poly grid of NMOS area and PMOS area individually remove, therefore can eliminate NMOS area and PMOS area
Non-uniform problem in etching load surface caused by the height of dummy poly grid is different, so as to prevent in removal dummy poly
During grid due to etching load is different and caused by contact hole etching stop-layer at the top of dummy poly grid and interlayer film
The residual of the residual of material such as silicon nitride or silica, can also prevent residual polycrystalline silicon, can finally prevent in dummy poly grid
Defect is generated after etching.
In addition, compared with the existing technology, open NMOS area photoetching process and existing middle removal NMOS area first
The photoetching process of work-function layer is identical, and the present invention only needs the photoetching process for increasing step opening PMOS area can be realized.
Description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Figure 1A-Fig. 1 D be the existing MOS transistor with HKMG each step of manufacturing method in device structural schematic diagram;
Fig. 2 is the flow chart of the manufacturing method of MOS transistor of the embodiment of the present invention with HKMG;
The knot of device in each step of manufacturing method of Fig. 3 A- Fig. 3 H MOS transistors with HKMG that are the embodiment of the present invention
Structure schematic diagram.
Specific implementation mode
Existing method:
As shown in Figure 1A to Fig. 1 D, be the existing MOS transistor with HKMG each step of manufacturing method in device knot
The manufacturing method of structure schematic diagram, the existing MOS transistor with HKMG includes the following steps:
Step 1: as shown in Figure 1A, MOS transistor includes NMOS and PMOS, and pseudo- grid are formed on 101 surface of semiconductor substrate
Structure, the source-drain area 109 of NMOS, the source-drain area 108 of PMOS, side wall 107, contact hole etching stop-layer 110 and interlayer film 111,
Dummy gate structure is formed by stacking by gate dielectric layer and dummy poly grid 106;Using chemical mechanical grinding (CMP) technique to described
Interlayer film 111 is planarized, and the chemical mechanical milling tech exposes the surface of the dummy poly grid 106.
In general, the semiconductor substrate 101 is silicon substrate.
The material of the side wall 107 includes silicon oxide or silicon nitride.
The material of the contact hole etching stop-layer 110 is silicon nitride.
The material of the interlayer film 111 is silica.
The gate dielectric layer includes high dielectric constant layer 105.
The gate dielectric layer further includes boundary layer 105a, and the boundary layer 105a is located at 105 He of the high dielectric constant layer
Between semiconductor substrate 101.
The material of the boundary layer 105a includes silica.
The material of the high dielectric constant layer 105 includes silica, silicon nitride, alundum (Al2O3), tantalum pentoxide, oxygen
Change yttrium, hafnium silicate oxygen compound, hafnium oxide, lanthana, zirconium dioxide, strontium titanates, zirconium silicate oxygen compound.
The surface of channel region and the channel region is formed with by 101 surface of the semiconductor substrate that the HKMG is covered
It is used to form raceway groove, the length of the raceway groove is 28nm or less.Namely the making technology node of the corresponding HKMG of the present invention is
28nm or less.
The channel region 103 of the PMOS tube is n-type doping, and generally use N traps are formed;The source-drain area 108 of the PMOS is P
The source-drain area 108 of+doping and the PMOS are located at the both sides of the corresponding HKMG.It is formed in the source-drain area 108 of the PMOS
There is embedded germanium silicon epitaxial layer, embedded germanium silicon epitaxial layer is not shown in Figure 1A.Embedded germanium silicon epitaxial layer is typically in puppet
The both sides of grid structure form groove, and filling germanium silicon epitaxial layer is formed in a groove again later;In general, the two sides of groove are all in
" ∑ " shape.
The channel region 104 of the NMOS tube adulterates for p-type, and generally use p-well is formed;The source-drain area 109 of the NMOS is N
The source-drain area 109 of+doping and the NMOS are located at the both sides of the corresponding HKMG.
It is also formed in the semiconductor substrate 1 by shallow trench field oxygen 2.
Step 2: as shown in Figure 1B, while removing all dummy poly grid 106.And in fact, described NMOS pairs
The height for the dummy poly grid 106 answered and the corresponding 106 highly i.e. gate high of the dummy poly grid of the PMOS are simultaneously
It differs, the two has difference in height.The etching load (loading) of the dummy poly grid 106 of different height is different, finally
Corresponding substance residual is will produce, such as silicon nitride, silica or residual polycrystalline silicon, to cause defect.
Step 3: as shown in Figure 1 C, forming the first work-function layer 112, first work-function layer 112 is the work content of PMOS
Several layers.
The material that first work-function layer 112 is is TiN.
Step 4: as shown in Figure 1 C, carrying out photoetching process formation photoetching offset plate figure and the region of the NMOS being opened and gone
Except first work-function layer 112 in the region of the NMOS.
Step 5: as shown in Figure 1 C, forming the second work-function layer 113, second work-function layer 113 is the work content of NMOS
Several layers, in the region of the PMOS, second work-function layer 113 is superimposed upon the surface of first work-function layer 112.
The material that second work-function layer 113 is is TiAl.
Step 6: as shown in Figure 1 C, forming the metal material layer 114 of metal gate 114.
Step 7: as shown in figure iD, being carried out to the metal material layer 114 using chemical mechanical milling tech flat
Change to be formed and removes the metal gate that the metal material layer 114 in region forms by being filled in the dummy poly grid 106
114;The HKMG of the PMOS includes by the gate dielectric layer, first work-function layer 112, second work-function layer 113
The structure being formed by stacking with the metal gate 114;The HKMG of the NMOS includes by the gate dielectric layer, second work function
The structure that layer 113 and the metal gate 114 are formed by stacking.
In general, the metal material layer of the metal gate 114 is Al.
Present invention method:
As shown in Fig. 2, being the flow chart of the manufacturing method of MOS transistor of the embodiment of the present invention with HKMG;Such as Fig. 3 A
Shown in Fig. 3 H, the structural representation of device in each step of manufacturing method for the MOS transistor with HKMG that is the embodiment of the present invention
The manufacturing method of figure, MOS transistor of the embodiment of the present invention with HKMG includes the following steps:
Step 1: as shown in Figure 3A, MOS transistor includes NMOS and PMOS, and pseudo- grid knot is formed on 1 surface of semiconductor substrate
Structure, the source-drain area 9 of NMOS, the source-drain area 8 of PMOS, side wall 7, contact hole etching stop-layer 10 and interlayer film 11, the puppet grid knot
Structure is formed by stacking by gate dielectric layer and dummy poly grid 6;The interlayer film 11 is carried out using chemical mechanical milling tech flat
Change, the chemical mechanical milling tech exposes the surface of the dummy poly grid 6.
In the embodiment of the present invention, the semiconductor substrate 1 is silicon substrate.
The material of the side wall 7 includes silicon oxide or silicon nitride.
The material of the contact hole etching stop-layer 10 is silicon nitride.
The material of the interlayer film 11 is silica.
The gate dielectric layer includes high dielectric constant layer 5.
The gate dielectric layer further includes boundary layer 5a, and the boundary layer 5a is located at the high dielectric constant layer 5 and semiconductor
Between substrate 1.
The material of the boundary layer 5a includes silica.
The material of the high dielectric constant layer 5 includes silica, silicon nitride, alundum (Al2O3), tantalum pentoxide, oxidation
Yttrium, hafnium silicate oxygen compound, hafnium oxide, lanthana, zirconium dioxide, strontium titanates, zirconium silicate oxygen compound.
It uses on the surface that channel region and the channel region are formed with by 1 surface of the semiconductor substrate that the HKMG is covered
In forming raceway groove, the length of the raceway groove is 28nm or less.Namely the making technology node of the corresponding HKMG of the present invention is 28nm
Below.
The channel region 3 of the PMOS tube is n-type doping, and generally use N traps are formed;The source-drain area 8 of the PMOS is mixed for P+
The source-drain area 8 of the miscellaneous and described PMOS is located at the both sides of the corresponding HKMG.It is formed in the source-drain area 8 of the PMOS embedded
Germanium silicon epitaxial layer, without showing embedded germanium silicon epitaxial layer in Fig. 3 A.Embedded germanium silicon epitaxial layer is typically in pseudo- grid structure
Both sides form groove, and filling germanium silicon epitaxial layer is formed in a groove again later;In general, the two sides of groove are all in " ∑ " shape.
The channel region 4 of the NMOS tube adulterates for p-type, and generally use p-well is formed;The source-drain area 9 of the NMOS is mixed for N+
The source-drain area 9 of the miscellaneous and described NMOS is located at the both sides of the corresponding HKMG.
It is also formed in the semiconductor substrate 1 by shallow trench field oxygen 2.
Step 2: as shown in Figure 3B, carrying out first time photoetching process and forming the first photoetching offset plate figure 201 by the NMOS's
The region of the PMOS is opened in locality protection.
Step 3: as shown in Figure 3 C, the dummy poly grid 6 in the region of the PMOS are removed, later described in removal
First photoetching offset plate figure 201.
Step 4: as shown in Figure 3D, forming the first work-function layer 12, first work-function layer 12 is the work function of PMOS
Layer.
The material that first work-function layer 12 is is TiN.
Step 5: as shown in FIGURE 3 E, carrying out second of photoetching process and forming the second photoetching offset plate figure 202 by the PMOS's
The region of the NMOS is opened in locality protection.
Step 6: as illustrated in Figure 3 F, removes first work-function layer 12 in the region of the NMOS and the puppet is more
Crystal silicon grid 6 remove second photoetching offset plate figure 202 later.
Step 7: as shown in Figure 3 G, forming the second work-function layer 13, second work-function layer 13 is the work function of NMOS
Layer, in the region of the PMOS, second work-function layer 13 is superimposed upon the surface of first work-function layer 12.
The material that second work-function layer 13 is is TiAl.
Step 8: as shown in Figure 3 G, forming the metal material layer 14 of metal gate 14.
Step 9: as shown in figure 3h, being carried out to the metal material layer 14 using chemical mechanical milling tech flat
Change to be formed and removes the metal gate 14 that the metal material layer 14 in region forms by being filled in the dummy poly grid 6;Institute
The HKMG for stating PMOS includes by the gate dielectric layer, first work-function layer 12, second work-function layer 13 and the gold
Belong to the structure that grid 14 are formed by stacking;The HKMG of the NMOS includes by the gate dielectric layer, second work-function layer 13 and institute
State the structure that metal gate 14 is formed by stacking.
The metal material layer of the metal gate 14 is Al.
When being removed to dummy poly grid 6 it is not to carry out region-wide i.e. NMOS area and PMOS in the embodiment of the present invention
The dummy poly grid 6 in region remove simultaneously, but the method for using lithographic definition, and first photoetching opens PMOS area and removes PMOS
The dummy poly grid 6 in region are forming corresponding first work-function layers of PMOS 12 later;Photoetching is used to open NMOS area again later
Domain removes the first work-function layer 12 and dummy poly grid 6 of NMOS area later;Subsequent formation NMOS is further continued for later to correspond to
The second work function and metal gate 14 metal material layer formation and chemical mechanical milling tech technique;As can be seen that
Since the NMOS area of the embodiment of the present invention and the dummy poly grid 6 of PMOS area individually remove, therefore can eliminate
The height of NMOS area and the dummy poly grid 6 of PMOS area Bu Tong caused by non-uniform problem in etching load surface, from
And can prevent during removing dummy poly grid 6 due to etching load is different and caused by 6 top of dummy poly grid connect
The residual of the residual of the material of contact hole etching stop layer 10 and interlayer film 11 such as silicon nitride or silica, can also prevent polysilicon
Residual can finally prevent from generating defect after dummy poly grid 6 etch.
In addition, compared with the existing technology, opening the corresponding photoetching process of photoetching process i.e. step 5 of NMOS area and showing
There is the photoetching process of the first work-function layer 12 of middle removal NMOS area identical, the embodiment of the present invention only needs to increase step opening
The photoetching process of PMOS area can be realized.
The present invention has been described in detail through specific embodiments, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of manufacturing method of the MOS transistor with HKMG, which is characterized in that include the following steps:
Step 1: MOS transistor includes NMOS and PMOS, pseudo- grid structure is formed in semiconductor substrate surface, the source-drain area of NMOS,
The source-drain area of PMOS, side wall, contact hole etching stop-layer and interlayer film, dummy gate structure is by gate dielectric layer and dummy poly grid
It is formed by stacking;The interlayer film is planarized using chemical mechanical milling tech, the chemical mechanical milling tech is by institute
Expose on the surface for stating dummy poly grid;
Step 2: carrying out first time photoetching process forms the first photoetching offset plate figure by the locality protection of the NMOS, it will be described
It opens in the region of PMOS;
Step 3: the dummy poly grid in removing the region of the PMOS, remove first photoetching offset plate figure later;
Step 4: forming the first work-function layer, first work-function layer is the work-function layer of PMOS;
Step 5: carrying out second photoetching process forms the second photoetching offset plate figure by the locality protection of the PMOS, it will be described
It opens in the region of NMOS;
Step 6: first work-function layer in removing the region of the NMOS and the dummy poly grid, remove institute later
State the second photoetching offset plate figure;
Step 7: forming the second work-function layer, second work-function layer is the work-function layer of NMOS, in the region of the PMOS
In, second work-function layer is superimposed upon the surface of first work-function layer;
Step 8: forming the metal material layer of metal gate;
It is formed described in being filled in Step 9: carrying out planarization to the metal material layer using chemical mechanical milling tech
Dummy poly grid remove the metal gate of the metal material layer composition in region;The HKMG of the PMOS includes by the grid
The structure that dielectric layer, first work-function layer, second work-function layer and the metal gate are formed by stacking;The NMOS's
HKMG includes the structure being formed by stacking by the gate dielectric layer, second work-function layer and the metal gate.
2. the manufacturing method of the MOS transistor with HKMG as described in claim 1, it is characterised in that:The semiconductor lining
Bottom is silicon substrate.
3. the manufacturing method of the MOS transistor with HKMG as claimed in claim 2, it is characterised in that:The material of the side wall
Material includes silicon oxide or silicon nitride.
4. the manufacturing method of the MOS transistor with HKMG as claimed in claim 2, it is characterised in that:The contact hole is carved
The material for losing stop-layer is silicon nitride.
5. the manufacturing method of the MOS transistor with HKMG as claimed in claim 2, it is characterised in that:The interlayer film
Material is silica.
6. the manufacturing method of the MOS transistor with HKMG as described in claim 1, it is characterised in that:First work content
The several layers of material for being are TiN, and the material that second work-function layer is is TiAl.
7. the manufacturing method of the MOS transistor with HKMG as described in claim 1, it is characterised in that:The gate dielectric layer
Including high dielectric constant layer.
8. the manufacturing method of the MOS transistor with HKMG as claimed in claim 7, it is characterised in that:The gate dielectric layer
Further include boundary layer, the boundary layer is between the high dielectric constant layer and semiconductor substrate.
9. the manufacturing method of the MOS transistor with HKMG as claimed in claim 8, it is characterised in that:The boundary layer
Material includes silica.
10. the manufacturing method of the MOS transistor with HKMG as claimed in claim 7, it is characterised in that:The high dielectric is normal
Several layers of material includes silica, silicon nitride, alundum (Al2O3), tantalum pentoxide, yttrium oxide, hafnium silicate oxygen compound, and two
Hafnium oxide, lanthana, zirconium dioxide, strontium titanates, zirconium silicate oxygen compound.
11. the manufacturing method of the MOS transistor with HKMG as described in claim 1, it is characterised in that:By the HKMG institutes
The semiconductor substrate surface of covering is formed with channel region and the surface of the channel region is used to form raceway groove, the raceway groove
Length is 28nm or less.
12. the manufacturing method of the MOS transistor with HKMG as claimed in claim 11, it is characterised in that:The PMOS tube
Channel region be n-type doping, the source-drain area of the PMOS be P+ adulterate and the source-drain area of the PMOS be located at it is corresponding described
The both sides of HKMG.
13. the manufacturing method of the MOS transistor with HKMG as claimed in claim 12, it is characterised in that:The PMOS's
Embedded germanium silicon epitaxial layer is formed in source-drain area.
14. the manufacturing method of the MOS transistor with HKMG as claimed in claim 11, it is characterised in that:The NMOS tube
Channel region be p-type doping, the source-drain area of the NMOS be N+ adulterate and the source-drain area of the NMOS be located at it is corresponding described
The both sides of HKMG.
15. the manufacturing method of the MOS transistor with HKMG as described in claim 1, it is characterised in that:The metal gate
Metal material layer is Al.
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| CN109637927A (en) * | 2018-12-12 | 2019-04-16 | 上海华力集成电路制造有限公司 | The manufacturing method of metal gate |
| CN112289747A (en) * | 2020-10-28 | 2021-01-29 | 上海华力集成电路制造有限公司 | Method for manufacturing high dielectric constant metal gate |
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| CN105990114A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Method of forming semiconductor device |
| CN106206441A (en) * | 2016-08-30 | 2016-12-07 | 上海华力微电子有限公司 | The preparation method of metal gates |
| CN108022882A (en) * | 2016-11-04 | 2018-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109637927A (en) * | 2018-12-12 | 2019-04-16 | 上海华力集成电路制造有限公司 | The manufacturing method of metal gate |
| CN109637927B (en) * | 2018-12-12 | 2020-11-24 | 上海华力集成电路制造有限公司 | Method for manufacturing metal grid |
| CN112289747A (en) * | 2020-10-28 | 2021-01-29 | 上海华力集成电路制造有限公司 | Method for manufacturing high dielectric constant metal gate |
| CN112289747B (en) * | 2020-10-28 | 2023-08-11 | 上海华力集成电路制造有限公司 | Method for manufacturing high dielectric constant metal gate |
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