CN108376683B - Method for manufacturing source electrode and semiconductor device - Google Patents

Method for manufacturing source electrode and semiconductor device Download PDF

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CN108376683B
CN108376683B CN201810162039.1A CN201810162039A CN108376683B CN 108376683 B CN108376683 B CN 108376683B CN 201810162039 A CN201810162039 A CN 201810162039A CN 108376683 B CN108376683 B CN 108376683B
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gap
dielectric layer
source electrode
etching
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CN108376683A (en
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罗清威
李赟
周俊
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

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Abstract

The invention relates to a manufacturing method of a source electrode and a semiconductor device, wherein the manufacturing method of the source electrode comprises the steps of forming a plurality of grid electrode structures above a semiconductor substrate, wherein the grid electrode structures are provided with a first gap and a second gap, and the width of the first gap is smaller than that of the second gap in the same direction; sequentially forming a dielectric layer and an etching barrier layer above the grid structure; etching the dielectric layer until the dielectric layer in the first gap is removed, and simultaneously, the second gap is still covered by the dielectric layer; etching the semiconductor substrate in the first gap to form a second groove, and removing the residual etching barrier layer and the residual dielectric layer; and then carrying out ion implantation to form a source electrode in the region of the second groove. The manufacturing method of the source electrode omits a photomask process, thereby being beneficial to reducing the cost. The invention also provides a semiconductor device comprising the source electrode formed by the method.

Description

Method for manufacturing source electrode and semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a source electrode and a semiconductor device.
Background
With the rapid development of the semiconductor industry, in order to achieve the purpose of improving the production efficiency and reducing the production cost, the integration density of integrated circuit chips, i.e., the number of semiconductor devices interconnected on a unit area of the chip, is increased, and the geometric size of the semiconductor devices is reduced, however, the trend also increases the complexity of the manufacturing process of the semiconductor devices, for example, in the manufacturing process of the semiconductor devices including Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), a plurality of mask processes (usually including a series of processes such as exposure, development and etching to pattern a certain functional layer) are usually performed to form components such as gates, sources and drains, although the intended purpose can be achieved, there is still a need for further improvement.
A floating gate type flash memory is a nonvolatile memory, and generally has a floating gate tunneling oxide (FLOTOX) structure including a gate dielectric layer, a floating gate, and a control gate, wherein the control gate controls storage and release of electrons in the floating gate by coupling. In the current floating gate type flash memory, a photomask process is used to form a groove on the substrate of the source region, and then ion implantation is performed in the groove to form the source electrode, which is high in cost.
Disclosure of Invention
The invention aims to solve the technical problem of higher cost caused by the special photomask process required for manufacturing the source electrode of the existing floating gate type flash memory.
In order to solve the above problems, the present invention provides a method for manufacturing a source electrode, comprising the following steps:
forming a plurality of gate structures over a semiconductor substrate, the plurality of gate structures having a first gap and a second gap, the first gap having a width smaller than a width of the second gap in a same direction; forming a dielectric layer above the gate structure, wherein the upper surface of the dielectric layer, which is positioned in the second gap, is a concave surface, and a region surrounded by the concave surface is defined as a first groove; forming an etching barrier layer to enable the etching barrier layer to fill the first groove; etching the dielectric layer until the dielectric layer in the first gap is removed, and simultaneously the bottom surface of the second gap is still covered by the dielectric layer; etching the semiconductor substrate positioned in the first gap to form a second groove; removing the residual etching barrier layer and the dielectric layer; and carrying out ion implantation to form a source electrode in the region of the second groove.
Optionally, the step of forming an etching blocking layer to fill the first groove with the etching blocking layer further includes: and enabling the upper surface of the etching barrier layer in the first groove to be flush with the upper surface of the dielectric layer outside the first groove.
Optionally, before forming the dielectric layer over the gate structure, the method for manufacturing the source further includes: forming a protective layer covering the plurality of gate structures.
Optionally, an isolation structure is formed in the semiconductor substrate, and the second groove penetrates through the isolation structure.
Optionally, the thickness of the dielectric layer is greater than half of the width of the first gap, and is less than half of the width of the second gap in the same direction.
Optionally, the material of the etching barrier layer includes an anti-reflection coating.
Optionally, the material of the etching barrier layer includes silicon oxide.
Optionally, the step of etching the semiconductor substrate located in the first gap to form a second groove further includes: and removing the residual etching barrier layer.
Optionally, the gate structure comprises a floating gate.
In addition, the invention also provides a semiconductor device which comprises a grid structure, a source electrode and a drain electrode, wherein the manufacturing of the source electrode comprises the method.
According to the manufacturing method of the source electrode, a photomask is not needed, the second groove is formed in the semiconductor substrate of the first gap between the grid electrode structures, and the source electrode is formed in the area of the second groove through ion implantation, so that a photomask process is omitted, and cost reduction is facilitated.
The semiconductor device provided by the invention has the advantages that the manufacture of the source electrode comprises the manufacture method of the source electrode, and the manufacture method has similar advantages.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a source according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor device after a gate structure is formed by using the method for manufacturing a source according to the embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a semiconductor device after a dielectric layer is formed by using the method for manufacturing a source according to the embodiment of the invention.
Fig. 4a and 4b are schematic cross-sectional views of a semiconductor device after forming an etching barrier layer by using the method for manufacturing a source electrode according to the embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of a semiconductor device after removing the dielectric layer in the first gap by using the method for manufacturing a source according to the embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a semiconductor device after forming a second recess by using the method for forming a source electrode according to the embodiment of the invention.
Fig. 7 is a schematic cross-sectional view of a semiconductor device after removing the remaining etching stop layer and the dielectric layer by using the method for manufacturing a source electrode according to the embodiment of the invention.
Description of reference numerals:
100-a semiconductor substrate; 200-a semiconductor device; 210-a gate structure; 211-a first gate structure; 212-a second gate structure; 213-a third gate structure; 201-an inter-electrode dielectric layer; 202-control gate; 110-an isolation structure; 220-a dielectric layer; 220 a-concave surface; 221-a protective layer; 230-etching the barrier layer; 10-a first gap; 20-a second gap; 30-a first groove; 40-second groove.
Detailed Description
The method for fabricating the source electrode and the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. For purposes of clarity, the drawings will not identify the same elements as each other in every drawing.
The terms "first," "second," and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a source according to an embodiment of the invention. Referring to fig. 1, the method for manufacturing a source electrode of the present embodiment includes the following steps:
s1: forming a plurality of gate structures over a semiconductor substrate, the plurality of gate structures having a first gap and a second gap, the first gap having a width smaller than a width of the second gap in a same direction;
s2: forming a dielectric layer above the gate structure, wherein the upper surface of the dielectric layer, which is positioned in the second gap, is a concave surface, and a region surrounded by the concave surface is defined as a first groove;
s3: forming an etching barrier layer to enable the etching barrier layer to fill the first groove;
s4: etching the dielectric layer until the dielectric layer in the first gap is removed, and simultaneously the bottom surface of the second gap is still covered by the dielectric layer;
s5: etching the semiconductor substrate positioned in the first gap to form a second groove;
s6: removing the residual etching barrier layer and the dielectric layer;
s7: and carrying out ion implantation to form a source electrode in the region of the second groove.
Therefore, according to the manufacturing method of the source electrode, a photomask is not used, the second groove is formed in the semiconductor substrate of the first gap between the grid electrode structures, and the second groove is used as the source electrode of the semiconductor device through ion implantation, so that a photomask process is omitted, and the cost is reduced.
Fig. 2 to 7 are schematic cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process of the method for manufacturing the source electrode. Next, a method for manufacturing a source and a semiconductor device according to the present embodiment will be described with reference to fig. 2 to 7.
It should be noted that the materials, thicknesses and formation manners of the above-mentioned and later-mentioned layers are only examples of the embodiments of the present invention, and different materials, thicknesses and formation manners may be adopted in different cases, which should not be construed as limiting the present invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor device after a gate structure is formed by using the method for manufacturing a source according to the present embodiment. Referring to fig. 2, step S1 is performed to form a plurality of gate structures 210 over the semiconductor substrate 100, wherein the plurality of gate structures 210 have a first gap 10 and a second gap 20, and a width D1 of the first gap 10 is smaller than a width D2 of the second gap 20 in the same direction (the term "width" herein refers to a distance between two ends of the corresponding structure parallel to the surface of the semiconductor substrate 100).
The semiconductor substrate 100 may be made of silicon, germanium, silicon carbide, or the like, silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or may be made of another material such as a group iii or v compound such as gallium arsenide. In other embodiments, the semiconductor substrate 100 may include a doped epitaxial layer, and the semiconductor substrate 100 may further implant a certain doped particle according to design requirements to change electrical parameters, in this embodiment, the semiconductor substrate 100 is an undoped or lightly p-type doped semiconductor substrate including silicon.
The semiconductor substrate 100 may include various doped regions depending on the design requirements of the semiconductor device 200. Further, in the present embodiment, an isolation structure 110 is formed in the semiconductor substrate 100 to isolate the regions and/or the semiconductor device 200. The isolation structure 110 is, for example, a Shallow Trench Isolation (STI), and the isolation structure 110 includes silicon oxide or other suitable material as an isolation medium. Fabrication of isolation structures 110 may be performed by those skilled in the art, and as one example, forming STI includes forming an opening in a silicon substrate by a photolithography and etching process, and filling the opening with one or more isolation dielectrics.
The semiconductor device 200 includes a gate structure 210, and further, the semiconductor device 200 may further include a memory cell and/or a logic circuit, in this embodiment, the semiconductor device 200 includes a floating gate type flash memory, and for the floating gate type flash memory, the gate structure 210 may be a stacked gate structure including a floating gate, an inter-electrode dielectric layer and a control gate. The semiconductor device 200 may further include a source and a drain, and the present embodiment takes a floating gate flash memory as an example, and mainly describes a method for forming the source. In other embodiments, other components may be added to the semiconductor device 200, and some of the components described below may be replaced or eliminated.
A plurality of gate structures 210 may be formed on the semiconductor substrate 100 by deposition, photolithographic patterning, etching processes, or a combination thereof, as an example, the gate structures 210 include a first gate structure 211, a second gate structure 212, and a third gate structure 213. In the cross-sectional structures shown in fig. 2 to 7, the semiconductor substrate 100 includes an isolation structure 110, a gate structure 210 formed above the isolation structure 110 includes an inter-electrode dielectric layer 201 and a control gate 202, the inter-electrode dielectric layer 201 may include an oxide layer and/or a nitride layer, the inter-electrode dielectric layer 201 may include an oxide-nitride-oxide (ONO) structure, and the material of the control gate 202 includes polysilicon, for example. It will be understood by those skilled in the art that a gate dielectric layer and a floating gate (not shown) are also formed on the semiconductor substrate 100, and the gate dielectric layer includes a dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, a high-k dielectric material, other dielectric materials, or a combination thereof. The floating gate is formed over a gate dielectric layer, and an inter-electrode dielectric layer 201 covers the floating gate to isolate the floating gate from the control gate 202. The gate structure 210 of the present invention is not limited thereto and the gate structure 210 may include other components for the semiconductor device 200 including a non-floating gate type flash memory.
The distances between the first gate structure 211, the second gate structure 212 and the third gate structure 213 may be different according to the design and functional requirements of the semiconductor device 200, in this embodiment, a first gap 10 is provided between the first gate structure 211 and the second gate structure 212, a second gap 20 is provided between the second gate structure 212 and the third gate structure 213, a width D1 of the first gap 10 is smaller than a width D2 of the second gap 20 in the same direction, a source region of the semiconductor device 200 is disposed in the first gap 10, and a drain region of the semiconductor device 200 is disposed in the second gap 20.
Fig. 3 is a schematic cross-sectional view of a semiconductor device after a dielectric layer is formed by using the method for manufacturing a source according to the embodiment of the invention. Referring to fig. 3, step S2 is performed to form a dielectric layer 220 over the gate structure 210, where the upper surface of the dielectric layer 220 located in the second gap 20 is a concave surface 220a, and the area surrounded by the concave surface 220a is defined as the first recess 30.
Specifically, the dielectric layer 220 covers the gate structure 210, the first gap 10 and the second gap 20 over the semiconductor substrate 100, and the dielectric layer 220 is formed by Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), high density plasma CVD (hdpcvd), metal organic CVD (mocvd), plasma enhanced CVD (pecvd) or other suitable deposition processes. Preferably, the dielectric layer 220 is deposited conformally (conformal coating) on the semiconductor substrate 100 with the gate structure 210. The material of dielectric layer 220 is preferably selected to be higher than the isolation dielectric etch in isolation structure 110 so that the subsequent etching of dielectric layer 220 has less impact on isolation structure 110. As an example, the material of isolation structure 110 (i.e., the isolation dielectric) includes silicon oxide, and the material of dielectric layer 220 includes silicon nitride.
The thickness of the dielectric layer 220 may be adjusted according to the dimensions of the gate structure 210, the first gap 10 and the second gap 20, so that the upper surface of the dielectric layer 220 located in the second gap 20 is a concave surface 220a, preferably, the dielectric layer 220 fills the first gap 10 at this time, that is, the upper surface of the dielectric layer 220 located in the first gap 10 is a plane or a convex surface, and for convenience, the area surrounded by the concave surface 220a is defined as the first groove 30.
Further, in order to fill the first gap 10 and form the first groove 30 above the second gap 20, the thickness of the dielectric layer 220 is preferably greater than half of the width D1 of the first gap 10 and less than half of the width D2 of the second gap 20.
In the present embodiment, before forming the dielectric layer 220, in order to better control the etching endpoint and protect the gate structures 210 when the dielectric layer 220 is subsequently etched, a protection layer 221 is formed over the semiconductor substrate 100, and the protection layer 221 covers the plurality of gate structures 210. The protective layer 221 includes, for example, 50 to
Figure BDA0001583305350000071
Thick silicon oxide. The protective layer 221 may be selected from the same material as the isolation structure 110, so that the protective layer 221 in the same region may be removed at the same time when the isolation structure 110 is subsequently etched. In other embodiments, the protection layer 221 may also be selected from other materials having a higher etching selectivity with respect to the dielectric layer 220. In another embodiment, the protective layer 221 may not be formed.
Fig. 4a and 4b are schematic cross-sectional views of a semiconductor device after forming an etching barrier layer by using the method for manufacturing a source electrode according to the embodiment of the invention. Referring to fig. 4a and 4b, step S3 is performed to form the etch stop layer 230, so that the etch stop layer 230 fills the first recess 30.
The etch stop layer 230 is used to fill the first recess 30 to protect the underlying dielectric layer 220, and the etch stop layer 230 and the dielectric layer 220 are preferably etched with a higher material selectivity to protect the underlying dielectric layer 220 during a subsequent etching process for the dielectric layer 220. In this embodiment, the material of the etching stop layer 230 includes silicon oxide, and the forming method of the etching stop layer 230 includes chemical vapor deposition, physical vapor deposition, atomic layer deposition, high density plasma CVD, metal organic CVD, plasma enhanced CVD, or other suitable deposition processes. The etch stop layer 230 may cover the surface of the dielectric layer 220 outside the first recess 30 (as shown in fig. 4 a), or may be formed by, for example, dry etching, wet etching, or Chemical Mechanical Polishing (CMP) process so that only the etch stop layer 230 in the first recess 30 remains (as shown in fig. 4 b).
In another embodiment, etch stop layer 230 comprises an anti-reflective coating (BARC) or other photoresist or mask layer with a higher etch selectivity than dielectric layer 220, which may be film-formed using, for example, a spin-on process and fills first recess 30, and then only etch stop layer 230 within first recess 30 may remain, for example, by an ashing process.
Preferably, in step S3, the upper surface of the etching stop layer 230 in the first groove 30 may be made flush with the upper surface of the dielectric layer 220 outside the first groove 30 by, for example, dry etching, wet etching or a CMP process (as shown in fig. 4 b), so as to reduce the etching time in step S4 and improve the etching region selection effect.
Fig. 5 is a schematic cross-sectional view of a semiconductor device after removing the dielectric layer in the first gap by using the method for manufacturing a source according to the embodiment of the invention. Referring to fig. 5, step S4 is performed to etch the dielectric layer 220 until the dielectric layer 220 in the first gap 10 is removed while the bottom surface of the second gap 20 is still covered by the dielectric layer 220.
Through steps S1 to S3, the dielectric layer 220 covers the bottom surfaces of the first gap 10 and the second gap 20, and the middle region of the upper surface of the dielectric layer 220 located in the second gap 20 is covered with the etch stop layer 230, that is, the area of the upper surface of the exposed dielectric layer 220 above the first gap 10 is larger than the area of the upper surface of the exposed dielectric layer 220 above the second gap 20, so that the etch rate of the exposed dielectric layer 220 above the first gap 10 is larger than the etch rate of the exposed dielectric layer 220 above the second gap 20 through the selection and adjustment of the etching process, and the dielectric layer 220 in the first gap 10 can be removed first in the etching process of step S4.
Specifically, an applicable etching process is wet etching, in which an etching solution includes, for example, phosphoric acid (mainly, the dielectric layer 220 includes silicon nitride in this embodiment), and since the area of the upper surface of the dielectric layer 220 in the first gap 10 is larger than the area of the upper surface of the dielectric layer 220 not covered by the etching stop layer 230 in the second gap 20, the etching solution is consumed more quickly, so that the etching rate of the dielectric layer 220 in the first gap 10 is higher, and the dielectric layer 220 in the first gap 10 is removed first.
Another etch process that may be implemented is dry etching, which may be performed using techniques including, for example, HBr, Cl2、SF6、O2、N2、NF3、Ar、He、CF4、CH2F2One or more of the group as an etching gas etches the dielectric layer 220. The dry etching has an etching selectivity caused by a microscopic loading effect (microscopic loading) or an aspect ratio dependent loading effect (ARDE), and since the area of the upper surface of the dielectric layer 220 above the first gap 10 is large (i.e., a pattern sparse region) and the area of the upper surface of the dielectric layer 220 above the second gap 20, which is not covered by the etching stopper layer 230, is small (i.e., a pattern dense region), the etching rate of the dielectric layer 220 in the first gap 10 is large, and the dielectric layer 220 in the first gap 10 is removed first.
Step S4 may be performed to selectively etch dielectric layer 220 without the need for a mask. In this embodiment, the protection layer 221 is formed below the dielectric layer 220, so that when the dielectric layer 220 is etched in step S4, an etching blocking effect can be achieved, and the influence on the gate structure 210 is reduced. After the dielectric layer 220 in the first gap 10 is removed by etching, the surface of the semiconductor substrate 100 in the first gap 10 is covered with the protection layer 221. In another embodiment, the dielectric layer 220 is formed directly on the semiconductor substrate 100 and the gate structure 210, and then the semiconductor substrate 100 in the first gap 10 is exposed through step S4. After the dielectric layer 220 in the first gap 10 is removed, the etching of the dielectric layer 220 is stopped, and the remaining dielectric layer 220 in the second gap 20 still covers the bottom surface of the second gap 20 (i.e., the protective layer 221 or the semiconductor substrate 100 at the bottom surface of the second gap 20 is not exposed).
Fig. 6 is a schematic cross-sectional view of a semiconductor device after forming a second recess by using the method for forming a source electrode according to the embodiment of the invention. Referring to fig. 6, step S5 is performed to etch the semiconductor substrate 100 of the first gap 10 to form a second groove 40.
After step S4 is completed, the first gap 10 exposes the protection layer 221 or the isolation structure 110 of the semiconductor substrate 100 (i.e., the situation where the protection layer 221 is not formed under the dielectric layer 220). In the present embodiment, the passivation layer 221 is exposed in the first gap 10, and the isolation structure 110 formed in the semiconductor substrate 100 is under the passivation layer 221, at this time, the semiconductor substrate 100 (or the passivation layer 221) of the second gap 20 is still covered by the remaining dielectric layer 220, and the upper surface of the remaining dielectric layer 220 is covered by the etching stop layer 230.
In this embodiment, the materials of the protection layer 221 and the isolation structure 110 both include silicon oxide, and the material of the dielectric layer 220 includes silicon nitride, so that the exposed isolation structure 110 in the first gap 10 can be etched by using an etching process with a large etching selection ratio for silicon oxide and silicon nitride to form the second groove 40, in other embodiments, the protection layer 221 in the first gap 10 can be removed first, and then the isolation medium of the isolation structure 110 corresponding to the first gap 10 can be etched to form the second groove 40.
An anisotropic dry etch process is preferably used to vertically etch the isolation dielectric in the corresponding regions to form the second recesses 40 in a self-aligned manner. The second recess 40 may penetrate the isolation structure 110, i.e., the etching process of step S5, until the silicon-containing semiconductor substrate of the semiconductor base 100 is exposed. The region of the second recess 40 may serve as a source region of the semiconductor device 200 in this embodiment.
In this embodiment, the material of the etching stop layer 230 includes silicon oxide, that is, includes the same material as the isolation structure 110 and the protection layer 221, and therefore, the etching stop layer 230 may be removed in step S6; in other embodiments, however, the material of the etch stop layer 230 is different from the material of the isolation structure 110 and the protection layer 221, and the etch stop layer 230 above the second gap 20 still remains after step S5, and can be removed by the subsequent steps.
Fig. 7 is a schematic cross-sectional view illustrating the removal of the remaining etching stop layer and the dielectric layer by using the method for manufacturing a source electrode according to the embodiment of the invention. Referring to fig. 7, step S6 is performed to remove the remaining etch stop layer 230 and the dielectric layer 220.
In some embodiments, the etching stop layer 230 includes a photoresist material of an anti-reflective coating (BARC) or other etching processes resistant to the dielectric layer 220, and the etching stop layer 230 is not removed during the etching of the isolation structure 110, so that the photoresist material may be removed by, for example, ashing after the second recess 40 is formed, but is not limited thereto, and the remaining etching stop layer 230 may select different etching processes according to different constituent materials, so as to achieve the purpose of removing the remaining etching stop layer 230.
After forming the second recess 40 and removing the remaining etch stop layer 230, the second gap 20 is covered with the remaining dielectric layer 220 to be removed. The remaining dielectric layer 220 may be removed using a wet etch, a dry etch, or the like. The present embodiment removes the remaining dielectric layer 220 using a wet etch including a phosphoric acid etch solution. But not limited thereto, different etching processes may be selected for the remaining dielectric layer 220 according to different constituent materials, so as to achieve the purpose of removing the remaining dielectric layer 220.
After removing the remaining etch stop layer 230 and the dielectric layer 220, step S7 may be performed to perform ion implantation to form a source electrode in the region of the second recess 40.
Step S7 may be to perform ion implantation in the second recess 40 at an angle perpendicular to the surface of the semiconductor substrate 100 or at an angle oblique to the normal of the surface of the semiconductor substrate 100 to form a source of the semiconductor device 200 in the region of the second recess 40. The ion implantation may further include a region of the second gap 20 that is exposed to form a drain of the semiconductor device 200. In this embodiment, the ion-implanted ions include n-type ions, such As one or a combination of arsenic (As), phosphorus, or antimony (Sb). In further embodiments, the ions of the ion implantation process may also include p-type ions. After ion implantation is completed, the doping concentration of the ions may be adjusted using an annealing process. The method of performing ion implantation on the second recess 40 to form the source may be performed by those skilled in the art with reference to the prior art, and will not be described herein.
The method for manufacturing the source electrode of this embodiment may further include filling another dielectric material (e.g., silicon oxide) in the ion-implanted second recess 40 to space the gate structures 210.
Through steps S1 to S7, in this embodiment, without using a photomask, the gate structures 210, the dielectric layer 220 (the upper surface of which forms the first groove 30 above the second gap 20 between the gate structures 210) are formed on the semiconductor substrate 100, the first groove 30 is filled with the etching stop layer 230, the dielectric layer 220 is etched until the dielectric layer 220 in the first gap 10 between the gate structures 210 is removed (at this time, the bottom surface of the second gap 20 is still covered by the dielectric layer 220), the semiconductor substrate 100 in the first gap 10 is etched to form the second groove 40, the remaining etching stop layer 230 and the dielectric layer 220 are removed, and ion implantation is performed to form the source in the region of the second groove 40. The manufacturing method of the source electrode omits a photomask process, thereby being beneficial to reducing the cost.
The present embodiment further includes a semiconductor device 200, as shown in fig. 7, the semiconductor device 200 includes a gate structure 210, a source and a drain, wherein the source is formed after ion implantation is performed in a region of the second recess 40, the second recess 40 is located in the isolation structure 110 (e.g. STI) in the semiconductor substrate 100, and the manufacturing of the source includes the manufacturing method of the source according to the present embodiment. In addition, the drain may be formed after ion implantation is performed on the second gap 20 after the remaining dielectric layer 220 is removed.
Further, in the present embodiment, the gate structure 210 includes a gate dielectric layer, a floating gate, an inter-electrode dielectric layer 201 and a control gate 202 formed on the semiconductor substrate 100. Thus, the semiconductor device 200 may have the structure and function of a floating gate type flash memory. Without limitation, the semiconductor device 200 may also be other four-terminal devices including a gate, a source, a drain, and a substrate (bulk), for example, the semiconductor device 200 may include one or more of an n-channel field effect transistor (NFET), a p-channel field effect transistor (PFET), a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a complementary metal oxide semiconductor transistor (CMOS), a high voltage transistor, and a high frequency transistor. Semiconductor device 200 may also include other suitable elements and combinations.
In the semiconductor device 200 described in this embodiment, the manufacturing process of the source includes the manufacturing method of the source described in this embodiment, and a photomask is not required, thereby being beneficial to reducing the cost.
It should be noted that the embodiments in the present specification are described in a progressive manner, and each part is mainly described as different from the previous part, and the same and similar parts may be referred to each other. For the semiconductor device disclosed in the embodiment, since the method corresponds to the method for manufacturing the source disclosed in the embodiment, the description is relatively simple, and for the relevant points, reference may be made to the description of the method for manufacturing the source.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the technical solutions of the present invention.

Claims (10)

1. A method for manufacturing a source electrode is characterized by comprising the following steps:
forming a plurality of gate structures over a semiconductor substrate, the plurality of gate structures having a first gap and a second gap, the first gap having a width smaller than a width of the second gap in a same direction;
forming a dielectric layer above the gate structure, wherein the upper surface of the dielectric layer, which is positioned in the second gap, is a concave surface, and a region surrounded by the concave surface is defined as a first groove;
forming an etching barrier layer to enable the etching barrier layer to fill the first groove;
etching the dielectric layer until the dielectric layer in the first gap is removed, and simultaneously the bottom surface of the second gap is still covered by the dielectric layer;
etching the semiconductor substrate positioned in the first gap to form a second groove;
removing the residual etching barrier layer and the dielectric layer; and
and carrying out ion implantation to form a source electrode in the region of the second groove.
2. The method for manufacturing a source electrode according to claim 1, wherein the step of forming an etching barrier layer so that the etching barrier layer fills the first recess further comprises: and enabling the upper surface of the etching barrier layer in the first groove to be flush with the upper surface of the dielectric layer outside the first groove.
3. The method of claim 1, wherein prior to forming a dielectric layer over the gate structure, the method further comprises: forming a protective layer covering the plurality of gate structures.
4. The method for manufacturing a source electrode according to claim 1, wherein an isolation structure is formed in the semiconductor substrate, and the second groove penetrates through the isolation structure.
5. The method for manufacturing the source electrode according to claim 1, wherein the thickness of the dielectric layer is larger than a half of the width of the first gap and smaller than a half of the width of the second gap in the same direction.
6. A method for forming a source electrode according to any of claims 1 to 5 wherein the material of the etch stop layer comprises an anti-reflective coating.
7. The method for manufacturing a source electrode according to any one of claims 1 to 5, wherein the material of the etching barrier layer comprises silicon oxide.
8. The method for fabricating a source electrode according to claim 7, wherein the step of etching the semiconductor substrate located in the first gap to form a second recess further comprises: and removing the residual etching barrier layer.
9. The method for manufacturing the source electrode according to any one of claims 1 to 5, wherein the gate structure comprises a floating gate.
10. A semiconductor device comprising a gate structure, a source electrode and a drain electrode, wherein the side surfaces of the gate structure are covered with a protective layer, and wherein the source electrode is manufactured by the method for manufacturing the source electrode according to claim 3.
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US6075267A (en) * 1996-02-28 2000-06-13 Ricoh Company, Ltd. Split-gate non-volatile semiconductor memory device
CN1689160A (en) * 2002-08-30 2005-10-26 富士通株式会社 Semiconductor storage device and its manufacturing method
US7550807B2 (en) * 2005-05-10 2009-06-23 Sharp Kabushiki Kaisha Semiconductor memory
CN105336781A (en) * 2014-08-07 2016-02-17 中芯国际集成电路制造(上海)有限公司 Source-drain structure and manufacturing method therefor
CN106653759A (en) * 2016-12-23 2017-05-10 武汉新芯集成电路制造有限公司 Flash memory structure and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075267A (en) * 1996-02-28 2000-06-13 Ricoh Company, Ltd. Split-gate non-volatile semiconductor memory device
CN1689160A (en) * 2002-08-30 2005-10-26 富士通株式会社 Semiconductor storage device and its manufacturing method
US7550807B2 (en) * 2005-05-10 2009-06-23 Sharp Kabushiki Kaisha Semiconductor memory
CN105336781A (en) * 2014-08-07 2016-02-17 中芯国际集成电路制造(上海)有限公司 Source-drain structure and manufacturing method therefor
CN106653759A (en) * 2016-12-23 2017-05-10 武汉新芯集成电路制造有限公司 Flash memory structure and manufacturing method thereof

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