CN108447524A - A method of for detecting external memory interface failure - Google Patents
A method of for detecting external memory interface failure Download PDFInfo
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- CN108447524A CN108447524A CN201810236368.6A CN201810236368A CN108447524A CN 108447524 A CN108447524 A CN 108447524A CN 201810236368 A CN201810236368 A CN 201810236368A CN 108447524 A CN108447524 A CN 108447524A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The present invention provides a kind of methods for detecting external memory interface failure, and data line is drawn high, is dragged down and detection in parallel, error checking is carried out to address wire, pass through the differentiation detection to address wire and data line, the hardware fault that external memory can be detected, be determined entirely by out comprehensively external interface memory address wire and/or data line whether failure, specially which signal breaks down, and specific failure cause, save cumbersome hardware detection.
Description
Technical field
The invention belongs to circuit signal detection fields, are related to a kind of method for detecting external memory interface failure.
Background technology
External memory interface is mainly used to same parallel storage connection, these memory packets as external memory interface
SDRAM, SBSRAM, Flash, SRAM memory etc. are included, external memory interface can also be attached with external parallel equipment,
These equipment include parallel A/D, D/A converter, the special chip with asynchronous parallel interface, and can pass through external memory
The connections such as interface same FPGA, CPLD.Most common purposes is to connect FLASH and SRAM simultaneously.For product, we are usually
All preferentially select external memory for BGA package, due to its inexpensive, small radiated noise, save space, rapid heat dissipation is more stable
It is firm, keep the integration density of plank high.When external memory breaks down, usually we take the means of hardware to carry out
It checks, but when for BGA package, takes hardware means just very bad operation, it is time-consuming and laborious.
What the detection method of some present external portion's memories had hardware also has software, they are only limited to detection address wire
Or mistake occurs for data line, does not have specific to which type of failure of which signal.
Invention content
The present invention proposes a kind of method for detecting external memory interface failure, can with more convenient and quicker detect
The reason of failure.
A method of for detecting external memory interface failure, it is characterised in that：
Step 1, the data that certain amount range is first write to memory；
Step 2 reads data, and the data read are compared with write-in data, calculate the write-in correct number of data；
Step 3, when be successfully written data number be equal to step 1 in write-in number when, indicate memory interface it is normal, terminate
Test, and when the number for being successfully written data is not equal to the write-in number in step 1, it was demonstrated that data success is not written, into
Enter step 4；
Step 4, data ray examination are that data are written to first address, are drawn high, are dragged down or inspection in parallel to data line；
Step 5, when data line is all pulled low, be determined as data line failure, terminate detection, when drawing high and drag down data/address bus
Sum when being 0xFFFF, be determined as data line mistake, and whether mistake is unknown to address wire, terminates detection；When data line is complete
When portion is wrong, terminate detection, without address ray examination, remaining situation enters step 6 into row address line inspection；
Step 6, assert address if address wire error value is not zero with data line error value into row address line error checking
Line is wrong with data line, and terminates to check, otherwise, enters step 7；
Step 7, if determining at this time, data line error value is 0, it is determined that it is wrong for only address wire, terminate to check, otherwise, then
It is wrong to be determined as only data line, terminates to check；
Preferably, the checking step of address wire is operated according to following in the step 5：First address is for asynchronous memory
0, it has 20 bit address lines, if wherein a bit address line is unrecognized, except data phase is written in the identical address in the other positions of this
Together, it is 1 that old place location ray examination thinking, which is first, 20 bit address line, other positions be 0, take its data see whether the number with first address
It is all mutually that address wire first is unrecognized according to identical, next checks second, second 1, other positions are 0, with such
It pushes away, checks whether 20 bit address lines are correct, the memory of remaining type carries out similar operations according to this step；
Preferably, check process data line is drawn high, dragged down：
Test initial address is assigned to pointer pnStartAddr by step 11；
Step 12, write-in data 0xFFFF；
If step 13 defines read latch, into line delay, otherwise directly read；
Exclusive or result, is assigned to the data line value being pulled low by step 14, the data bit exclusive or that data will be written and read；
Step 15, write-in data 0x0；
If step 16 defines read latch, into line delay, otherwise directly read；
The data read are assigned to the data line value being raised by step 17；
Step 18 will be drawn high and is added with the data line value dragged down；
Preferably, check process in parallel is carried out to data line：
Step 21, data line parallel connection array first address be assigned to pointer pnDataErrParallel；
Step 22, setting i=0；
Step 23 judges whether i current values are less than board level test bus data length, if it is not, then directly terminate, if so, into
Enter step 24；
Step 24 judges whether i be raised, drag down or inspected is parallel connection, if so, checking next bit, i values add 1, return
To step 23, if it is not, then entering step 25；
Step 25 is assigned to first address by i for 1 resin；
Step 26, data to be written are added with the data bit being raised, and are assigned to temporary variable nTempj；
If step 27 defines read latch, into line delay, otherwise directly read；
Step 28, the data read and temporary variable nTempj exclusive or obtain being that the data line value in parallel with i is assigned to variable
nTempx；
Step 29 carries out variable nTempx to determine whether 0, if zero, then checks that next bit, i values add 1, return to step 23,
If not zero, then variable nTempx is added with i, obtains parallel value and be assigned to data line parallel connection array；
Step 30, pointer pnDataErrParallel add 1；Data value in parallel is assigned to nDataErr.
Preferably, to address wire error checking flow：
0xFFFF is written in step 41, first address；
If step 42 defines read latch, into line delay, otherwise directly read；Step 43, setting i=0；
Step 44 judges whether i is less than board level test bus address digit, if it is not, then terminating to check；If so, entering step
45；
Step 45, address 0x1 deviate i；
Step 46 judges whether the data that initial address and offset address store are identical, if so, assert i position datawires address
Mistake, address error value adds offset address, and enters step 47, if it is not, being then directly entered step 47；
Step 47, i=i+1, subsequently into step 44；
Preferably, the data line failure in step 5, failure cause are that data line drags down or chip selection signal, writes enabled letter entirely
Number, output enable signal failure in one or more.
For the prior art, the present invention provides a kind of method for detecting external memory interface failure, Neng Goujian
Survey external memory hardware fault, be determined entirely by out comprehensively external interface memory address wire and/or data line whether
Failure, specially which signal break down and specific failure cause, saves cumbersome hardware detection, is effectively promoted
Working efficiency reduces testing cost, and makes fault detect more intelligent, convenient, fast.
Description of the drawings：
Fig. 1 is a kind of method flow diagram for detecting external memory interface failure of the present invention；
Fig. 2 is that the data line of the present invention draws high the flow chart for dragging down inspection；
Fig. 3 is the flow chart of the data line parallel connection inspection of the present invention；
Fig. 4 is the address wire malfunction routine flow chart of the present invention；
Specific embodiment：
The invention will be further described in the following with reference to the drawings and specific embodiments.
A method of for detecting external memory interface failure, specifically comprise the following steps：
A certain range is write to memory by step 1, elder generation（For example write 100）Data；
Step 2 reads data, and the data read are compared with write-in data, calculate the write-in correct number of data；
Step 3, when be successfully written data number be equal to step 1 in write-in number when, indicate memory interface it is normal, terminate
Test, and when the number for being successfully written data is not equal to the write-in number in step 1, it was demonstrated that data success is not written, into
Enter step 4；
Step 4, data ray examination are that data are written to first address, are drawn high, are dragged down or inspection in parallel to data line；
Step 5, when data line is all pulled low, be determined as data line failure, terminate detection, failure cause may be several at this time
Dragged down entirely according to line or chip selection signal, write enable signal, output enable signal failure, when the sum for drawing high and dragging down data/address bus
For 0xFFFF when, be determined as data line mistake, and whether mistake is unknown to address wire, terminates detection；When data line is all wrong
It mistakes, terminates detection, without address ray examination, remaining situation enters step 6 into row address line inspection；
It can be according to following operation to the checking step of address wire in the step：First address is 0 for asynchronous memory, it has
20 bit address lines, if wherein a bit address line is unrecognized, except the identical address write-in data in the other positions of this are identical, old place
Location ray examination thinking is that first, 20 bit address line is 1, and whether other positions are 0, take its data to see identical as the data of first address,
It is all mutually that address wire first is unrecognized, next checks that second, second 1, other positions are 0, and so on, it checks
Whether 20 bit address lines are correct, and the memory of remaining type carries out similar operations according to this step；
Step 6, assert address if address wire error value is not zero with data line error value into row address line error checking
Line is wrong with data line, and terminates to check, otherwise, enters step 7；
Step 7, if determining at this time, data line error value is 0, it is determined that it is wrong for only address wire, terminate to check, otherwise, then
It is wrong to be determined as only data line, terminates to check；
By the above method, all kinds of failures of external memory interface can be detected and be investigated, and determine external storage
The failure cause of device interface, for example, data line drag down entirely be possible to other signals line it is faulty, failure when data line is drawn high entirely, number
According to line mistake, certain position datawire is drawn high or is dragged down or parallel connection is broken down, address wire mistake, the unrecognized event of certain bit address line
Barrier etc., does not enumerate, but by above method step, can be determined entirely by out external interface memory comprehensively one by one herein
Address wire and/or data line whether failure, specially which signal breaks down and specific failure cause.
The check process drawn high, dragged down to data line referred in above-mentioned steps 4 is as shown in Figure 2：
Test initial address is assigned to pointer pnStartAddr by step 11；
Step 12, write-in data 0xFFFF；
If step 13 defines read latch, into line delay, otherwise directly read；
Exclusive or result, is assigned to the data line value being pulled low by step 14, the data bit exclusive or that data will be written and read；
Step 15, write-in data 0x0；
If step 16 defines read latch, into line delay, otherwise directly read；
The data read are assigned to the data line value being raised by step 17；
Step 18 will be drawn high and is added with the data line value dragged down；
The check process that parallel connection is carried out to data line referred in above-mentioned steps 4 is as shown in Figure 3：
Step 21, data line parallel connection array first address be assigned to pointer pnDataErrParallel；
Step 22, setting i=0；
Step 23 judges whether i current values are less than board level test bus data length, if it is not, then directly terminate, if so, into
Enter step 24；
Step 24, judge i whether be raised, drag down or inspected for parallel connection, then check that next bit, i values add 1, return to step
Rapid 23, if it is not, then entering step 25；
Step 25 is assigned to first address by i for 1 resin；
Step 26, data to be written are added with the data bit being raised, and are assigned to temporary variable nTempj；
If step 27 defines read latch, into line delay, otherwise directly read；
Step 28, the data read and temporary variable nTempj exclusive or obtain being that the data line value in parallel with i is assigned to variable
nTempx；
Step 29 carries out variable nTempx to determine whether 0, if zero, then checks that next bit, i values add 1, return to step 23,
If not zero, then variable nTempx is added with i, obtains parallel value and be assigned to data line parallel connection array；
Step 30, pointer pnDataErrParallel add 1；Data value in parallel is assigned to nDataErr.
What is referred in above-mentioned steps 6 is as shown in Figure 4 to address wire error checking flow：
0xFFFF is written in step 41, first address；
If step 42 defines read latch, into line delay, otherwise directly read；
Step 43, setting i=0；
Step 44 judges whether i is less than board level test bus address digit, if it is not, then terminating to check；If so, entering step
45；
Step 45, address 0x1 deviate i；
Step 46 judges whether the data that initial address and offset address store are identical, if so, assert i position datawires address
Mistake, address error value adds offset address, and enters step 47, if it is not, being then directly entered step 47；
Step 47, i=i+1, subsequently into step 44；
It is important to note that it is above-mentioned provide data line is drawn high, is dragged down or the flow checked in parallel and right
The flow of address wire error checking other can also equally can determine the testing process of mistake to substitute using this field, such as
Enumerate detection or parallel detection etc. mode, it is preferred to use the above-mentioned flow provided, can ensure detection efficiency and
The accuracy of detection.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So attached claim is intended to be construed to include preferred
Embodiment and all change and modification for falling into the scope of the invention.
Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art
God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to include these modifications and variations.
Claims (6)
1. a kind of method for detecting external memory interface failure, it is characterised in that：
Step 1, the data that certain amount range is first write to memory；
Step 2 reads data, and the data read are compared with write-in data, calculate the write-in correct number of data；
Step 3, when be successfully written data number be equal to step 1 in write-in number when, indicate memory interface it is normal, terminate
Test, and when the number for being successfully written data is not equal to the write-in number in step 1, it was demonstrated that data success is not written, into
Enter step 4；
Step 4, data ray examination are that data are written to first address, are drawn high, are dragged down or inspection in parallel to data line；
Step 5, when data line is all pulled low, be determined as data line failure, terminate detection, when drawing high and drag down data/address bus
Sum when being 0xFFFF, be determined as data line mistake, and whether mistake is unknown to address wire, terminates detection；When data line is complete
When portion is wrong, terminate detection, without address ray examination, remaining situation enters step 6 into row address line inspection；
Step 6, assert address if address wire error value is not zero with data line error value into row address line error checking
Line is wrong with data line, and terminates to check, otherwise, enters step 7；
Step 7, if determining at this time, data line error value is 0, it is determined that it is wrong for only address wire, terminate to check, otherwise, then
It is wrong to be determined as only data line, terminates to check.
2. a kind of method for detecting external memory interface failure according to claim 1, it is characterised in that：The step
To the checking step of address wire according to following operation in rapid 5：First address is 0 for asynchronous memory, it has 20 bit address lines,
If wherein a bit address line is unrecognized, except the identical address write-in data in the other positions of this are identical, old place location ray examination is thought
Road is that first, 20 bit address line is 1, and whether other positions are 0, take its data to see identical as the data of first address, be all mutually address
First, line is unrecognized, next checks that second, second 1, other positions are 0, and so on, check 20 bit address lines
Whether correct, the memory of remaining type carries out similar operations according to this step.
3. a kind of method for detecting external memory interface failure according to claim 1, it is characterised in that：To data
The check process that line is drawn high, dragged down：
Test initial address is assigned to pointer pnStartAddr by step 11；
Step 12, write-in data 0xFFFF；
If step 13 defines read latch, into line delay, otherwise directly read；
Exclusive or result, is assigned to the data line value being pulled low by step 14, the data bit exclusive or that data will be written and read；
Step 15, write-in data 0x0；
If step 16 defines read latch, into line delay, otherwise directly read；
The data read are assigned to the data line value being raised by step 17；
Step 18 will be drawn high and is added with the data line value dragged down.
4. a kind of method for detecting external memory interface failure according to claim 1, it is characterised in that：To data
Line carries out check process in parallel：
Step 21, data line parallel connection array first address be assigned to pointer pnDataErrParallel；
Step 22, setting i=0；
Step 23 judges whether i current values are less than board level test bus data length, if it is not, then directly terminate, if so, into
Enter step 24；
Step 24 judges whether i be raised, drag down or inspected is parallel connection, if so, checking next bit, i values add 1, return
To step 23, if it is not, then entering step 25；
Step 25 is assigned to first address by i for 1 resin；
Step 26, data to be written are added with the data bit being raised, and are assigned to temporary variable nTempj；
If step 27 defines read latch, into line delay, otherwise directly read；
Step 28, the data read and temporary variable nTempj exclusive or obtain being that the data line value in parallel with i is assigned to variable
nTempx；
Step 29 carries out variable nTempx to determine whether 0, if zero, then checks that next bit, i values add 1, return to step 23,
If not zero, then variable nTempx is added with i, obtains parallel value and be assigned to data line parallel connection array；
Step 30, pointer pnDataErrParallel add 1；Data value in parallel is assigned to nDataErr.
5. a kind of method for detecting external memory interface failure according to claim 1, it is characterised in that：To address
Line error checking flow：
0xFFFF is written in step 41, first address；
If step 42 defines read latch, into line delay, otherwise directly read；Step 43, setting i=0；
Step 44 judges whether i is less than board level test bus address digit, if it is not, then terminating to check；If so, entering step
45；
Step 45, address 0x1 deviate i；
Step 46 judges whether the data that initial address and offset address store are identical, if so, assert i position datawires address
Mistake, address error value adds offset address, and enters step 47, if it is not, being then directly entered step 47；
Step 47, i=i+1, subsequently into step 44.
6. a kind of method for detecting external memory interface failure according to claim 1, it is characterised in that：Step 5
In data line failure, failure cause be data line drag down entirely or chip selection signal, write enable signal, output enable signal therefore
One or more in barrier.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151103A (en) * | 2020-09-17 | 2020-12-29 | 深圳市宏旺微电子有限公司 | DRAM fault detection method and device based on March algorithm |
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Application publication date: 20180824 |