CN1427420A - RAM high speed test control circuit and its testing method - Google Patents
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Abstract
A control circuit for high-speed test of RAM is disclosed, which is based on hardware logic for correct location of failure and high test efficiency. Its test method includes such steps as setting up the state of test command register, choosing test type, strobing test register, testing data lines by comparison, testing address lines by comparison, step test of memory units, and analyzing error type by reading state registers.
Description
Technical field
The present invention relates to the storer detection technique, particularly realize RAM (random access memory) high speed test method and test control circuit thereof with hardware logic.
Background technology
In communication products and computer application system, random access memory (RAM) is the core cell that is used for depositing raw data, intermediate treatment result and other information.Can storer realize normal read/write operation, and in the storage/access process data distortion does not take place, very important for the normal reliable work that guarantees total system.For this reason, necessary before product export and system storer is carried out comprehensive testing and diagnosing before starting working.
Along with the development of communication and computer hardware technique, system is increasing to the capacity requirement of storer.Simultaneously along with the develop rapidly of semiconductor technology, the raising of silicon chip integrated level, the memory capacity that can realize on the silicon chip of unit area is also in rapid increase.Therefore, how to realize that the high speed to high capacity RAM, the test of high coverage rate become more and more important.
The test of RAM mainly comprises the production Equipment Test of RAM production test, band RAM product and the power-on self-test of band RAM equipment etc.There is following shortcoming in existing measuring technology:
1) test speed is slow, substantially all be adopt testing software by cpu i/f to RAM is tested.The capacity of present storer becomes increasing, if finish test by software, the test duration will be very long, and during to the test of RAM, test speed can't satisfy demand on the speed fully in RAM production test or some product.
2) existing measuring technology is not detailed to RAM failure problems location, is not easy to the statistical study of maintenance failure location or RAM fault type information.
Summary of the invention
In view of existing measuring technology above shortcomings, the present invention proposes and a kind ofly realize RAM high speed test method and test control circuit thereof, with the production test of satisfying high capacity RAM and the requirement of application testing with hardware logic.
RAM high speed test control circuit of the present invention comprises: cpu interface circuit, RAM read-write control interface, test result status register, test command register and testing circuit.
Cpu interface circuit is used to be provided with the state of test command register, the corresponding test result register of gating, the information of read test result phase register record.
RAM reads and writes control interface, is used to connect tested RAM, the control read/write data.
The test result status register, it is connected with cpu interface circuit, comprises test state register, data line test result status register, address wire test result status register and storage unit test result status register.
The test command register contains test enable register and content measurement mask register, receives the command selection test-types (being the test of data line or address wire or storage unit) of cpu interface circuit.
The testing circuit, contain data line test, address wire test and storage unit test module, be connected with the test result status register with RAM read-write control interface respectively, finish tested RAM data line, address wire and storage unit test according to the test command buffer status.
RAM high speed test method of the present invention is characterized in that taking following steps:
A, the state of test command register is set, selects data line, address wire and storage unit test by cpu interface circuit, and the corresponding test result status register of gating;
B, detection data line, some groups of setting datas are write tested RAM step by step, reading corresponding data in each step compares with the setting data that writes respectively, if relatively make mistakes, put error flag and data line test result status register, withdraw from test, otherwise enter the comparison process of next group data;
C, detection address wire write some groups of particular address data to tested RAM, read the corresponding address data and compare with the particular address data that write respectively, compare and stagger the time, and put error flag and address wire test result status register, withdraw from the address wire test;
The graphic-arts technique that strides d, employing chessboard detects the storage unit of tested RAM, if wrong, send storage unit test result status register appropriate address;
E, read the information of corresponding test result status register record, analysis and judgement ram error type by cpu interface circuit.
The present invention has realized RAM is detected comprehensively efficiently by hardware logic, and test is comprehensive, and test contents comprises address wire interconnecting test on the plate, data line interconnecting test, RAM built-in function test (address decoding, storage unit read-write capability etc.).The testing sequence of its data line, address wire and storage unit test by cpu i/f by software control, can take individual event to test or test by default sequence, the result of test can be read by cpu i/f, or by the status indicator lamp indication, testing efficiency improves greatly than traditional method for testing software.
The present invention can use the RAM production test, the power-on self-test of the production Equipment Test of band RAM product and band RAM equipment etc.Its testing apparatus cost is low, forms simply, is convenient to operation, test flexibly.Can test out various bridge joint short troubles (Short fault) and fixed logic fault (Stuck-at fault), stuck-open fault (Stuck-open fault), state exchange fault (Transition fault), data maintenance fault (Data-maintaining fault), state coupling fault (Coupling fault), multiple Write fault (multiple accessfault) etc. exactly.RAM problem localization of fault is accurate, brings convenience for maintenance and fault type statistics.
The production Equipment Test of the multiple veneer of the present invention on certain communication product, the practical operation situation ideal, its detection speed to high capacity RAM is fast, fault recall rate height, positioning problems is detailed, has good using value.
Description of drawings
Fig. 1 is that RAM of the present invention detects the control circuit entire block diagram;
Fig. 2 is the test state register functional schematic of Fig. 1;
Fig. 3 is RAM data line testing process figure of the present invention;
Fig. 4 is address ram line testing process figure of the present invention;
Fig. 5 is ram memory cell testing process figure of the present invention.
Specific implementation method
The diagnostic procedure of data-carrier store RAM checks its each storage unit to carry out the validity of read/write operation exactly.Test to storer comprises three basic sides: the one, and the test of data line, the 2nd, to the test of address wire and decoding, the 3rd, to the test of storage unit; Detection to RAM is exactly by certain test pattern, and the function of storage unit and address decoding circuitry is carried out rapidly and efficiently inspection.The test of storage unit can the test of cover data line and the mistake of address wire test, increases independent data line, address wire is tested is in order to locate the fault that detailed data line address line is tested.
RAM of the present invention detects control circuit as shown in Figure 1.This circuit comprises: cpu interface circuit, RAM read-write control interface, test command register, testing result status register and testing circuit.Below each several part advanced one one describe.
Can test-types (data line test, address wire test, storage unit test) be set to RAM testing circuit by cpu interface circuit; And can start RAM and detect by writing control word triggering RAM read-write controller to detecting enable register; CPU also can read content in the detected state register by this interface circuit, so that obtain detected state and result, judges and whether detects success or wrong type.
The test command register comprises: test enable register and content measurement mask register.It is connected between cpu interface circuit and the testing circuit, under the default conditions that power on, enables during test to close.Have only and just start test when issuing enable command by cpu i/f.The content measurement mask register is mainly used to be provided with selects to carry out data line test, address wire test, still storage unit test.
The test result status register is connected with cpu interface circuit, and it comprises test state register, data line test result status register, address wire test result status register and storage unit test result status register.
1., test state register
Test state register can be the register of a 5bit, and wherein everybody is defined as detected state respectively, detects end, address wire mistake, data line mistake and storage unit error register.The implication of each bit of register of 5bit as shown in Figure 2.Wherein every bit0--bit4 is defined as detected state respectively, detects end, address wire mistake, data line mistake and storage unit error register.
Detected state: when this position is ' 1 ', the expression external RAM detects and carries out.
Detect and finish:, represent to detect and finish when this position is ' 1 '.
Address wire mistake:, illustrate that address wire has problem when this position is ' 1 '.
Data line mistake:, illustrate that data line has problem when this position is ' 1 '.
Storage unit mistake:, illustrate that storage unit has problem when this position is " 1 ".
During power-up initializing, each bit of detected state whole clear 0; When detecting not discovery mistake of end, detected state is 00010.
2., data line test result status register
Data line test result status register is a same wide register with the data line width.Power on and begin to be defaulted as complete 0 before the test.Test,, then represent this position datawire fault if a certain position is 1.Before beginning test at every turn, this register automatic clear 0.
3., address wire test result status register
Address wire test result status register is a same wide register with the address wire width.Power on and begin to be defaulted as complete 0 before the test.Test,, then represent this bit address line fault if a certain position is 1.Before beginning test at every turn, this register automatic clear 0.
4., storage unit testing result phase register
Storage unit testing result phase register has 2, and its bit wide all equals the width of address wire.One of them is used for noting down the start address of storage unit test failure.Another is used for noting down the number of unit of storage unit test errors.Power on and begin to be defaulted as complete 0 before the test.Before beginning test at every turn, this register automatic clear 0.
The testing circuit, contain data line test, address wire test and storage unit test module, be connected with the test result status register with RAM read-write control interface respectively, finish tested RAM data line, address wire and storage unit test according to the test command buffer status.
The basic function of this processing of circuit requires:
The data line test: the test data line has or not adhesion or is pulled to the fault of a certain fixed level, and requirement can navigate to a certain position fault
The address wire test: the test address line has or not adhesion or is pulled to the fault of a certain fixed level, and requirement can navigate to a certain position fault
Storage unit test: whether the read-write memory function of testing all storage unit is normal, and requirement can be quoted the number of bad element of this RAM or the start address of bad element.
Three test logics of foregoing circuit are uncorrelated mutually, and testing sequence, can be taked to test separately or test by default sequence by software control by cpu i/f.Usually testing sequence is undertaken by data line, address wire, storage unit test, because the data line test is the simplest, this test is found wrong, and all the other two tests just need not.Its typical method of testing is as indicated above, repeats no more.
The testing sequence of data line, address wire and storage unit test can for example be undertaken by address wire, data line, storage unit testing sequence according to the adjustment of test needs, or undertaken by storage unit, address wire, data line testing sequence etc.
Based on the another kind of RAM high speed test method of foregoing circuit, take following steps:
A ', the state of test command register is set, selects address wire, data line and storage unit test by cpu interface circuit, and the corresponding test result status register of gating;
B ', detection address wire write some groups of particular address data to tested RAM, read the corresponding address data and compare with the particular address data that write respectively, compare and stagger the time, and put error flag and address wire test result status register, withdraw from the address wire test;
C ', detection data line, some groups of setting datas are write tested RAM step by step, reading corresponding data in each step compares with the setting data that writes respectively, if relatively make mistakes, put error flag and data line test result status register, withdraw from test, otherwise enter the comparison process of next group data;
The graphic-arts technique that strides d ', employing chessboard detects the storage unit of tested RAM, if wrong, send storage unit test result status register appropriate address;
E ', read the information of corresponding test result status register record, analysis and judgement ram error type by cpu interface circuit.Test when wrong to drive and light pilot lamp and indicate by test state register.
Sometimes also can only carry out wherein test as required, as only wishing to know the quality of this RAM, and need not know when being detailed that data lines mistake or that root address wire mistake, can test by a select storage unit, the test of storage unit also can detect cover data line mistake or address wire fault.
Below be the third RAM high speed test method of the present invention, it takes following steps:
A ", by cpu interface circuit the state of test command register is set, select storage unit test, and gating storage unit test result status register;
B ", adopt the chessboard graphic-arts technique that strides to detect the storage unit of tested RAM, if wrong, send storage unit test result status register appropriate address;
C ", the information by cpu interface circuit reading cells test result status register record, the analysis and judgement ram error.
RAM data line testing process of the present invention as shown in Figure 3.The prerequisite of data line test is that presumptive address line fixing operation address location is correct.Its testing procedure (to the least significant end address function) is as follows:
Write complete 0 read-around ratio;
Write complete 1 read-around ratio;
Write the 1010...1010. read-around ratio;
Write the 0101...0101. read-around ratio;
Walking 0 test of heuristics;
Walking 1 test of heuristics.
Wherein walking 0 algorithm is: the width of supposing test data is N, the lowest order of first test data is that 0 all the other positions are 1 so, be 111...110, the penultimate of second test data is that 0 all the other positions are 1, be 111...101, and the like, be 101...111 until the penult data, last test data is 011...111.0 be displaced to most significant digit successively in the test data like this, also can be displaced to lowest order successively from most significant digit from lowest order.
Walking 1 algorithm wherein: the width of supposing test data is N, the lowest order of first test data is that 1 all the other positions are 0 so, be 000...001, the penultimate of second test data is that 1 all the other positions are 0, be 000...010, and the like, be 010...000 until the penult data, last test data is 100...000.1 be displaced to most significant digit successively in the test data like this, also can be displaced to lowest order successively from most significant digit from lowest order.
Its logic realization (to the least significant end address function) is:
Complete 0 reads and former data XOR, if be not 0, then withdraw from data line test, the end of test (EOT) position 1 in the test state register, simultaneously the XOR result give corresponding data line test result status register, the data line errors present 1 in the test state register.Otherwise enter next step.
Writing complete 1 reads and former data XOR, if be not 0, then withdraw from data line test, the end of test (EOT) position 1 in the test state register, simultaneously the XOR result give corresponding data line test result status register, the data line errors present 1 in the test state register.Otherwise enter next step.
Writing 1010... reads and former data XOR, if be not 0, then withdraw from data line test, the end of test (EOT) position 1 in the test state register, simultaneously the XOR result give corresponding data line test result status register, the data line errors present 1 in the test state register.Otherwise enter next step.
Writing 0101... reads and former data XOR, if be not 0, then withdraw from data line test, the end of test (EOT) position 1 in the test state register, simultaneously the XOR result give corresponding data line test result status register, the data line errors present 1 in the test state register.Otherwise enter next step.
Walking 0--reads and former data XOR, if be not 0, then withdraw from data line test, the end of test (EOT) position 1 in the test state register, simultaneously the XOR result give corresponding data line test result status register, the data line errors present 1 in the test state register.Otherwise enter next step.
Walking 1--reads and former data XOR, if be not 0, then withdraws from the data line test, simultaneously the XOR result give corresponding data line test result status register, the data line errors present 1 in the test state register.Otherwise enter next step.
Withdraw from data line test, the end of test (EOT) position 1 in the test state register.
Address ram line testing process as shown in Figure 4.The prerequisite of address wire test is that the tentation data line is correct.Its testing procedure is as follows:
(1), write operation: 0 address, all ones address, 1010....1010 address, 0101...0101 address, walking 0 algorithm address, walking 1 algorithm address (writing data counts increases progressively).
(2), read operation: 0 address, all ones address, 1010....1010 address, 0101...0101 address, walking 0 algorithm address, walking 1 algorithm address (relatively read with whether identical write data).
Its logic realization is:
(1), write state: finishing, the data of address write: 0 address, all ones address, 1010...1010 address, 0101...0101 address, walking 0 algorithm address, walking 1 algorithm address (it is identical with the address to write data).
(2), read states: finish the data of address read with relatively: 0 address, all ones address, 1010...1010. address, 0101...0101 address, walking 0 algorithm address, walking 1 algorithm address.The data of reading compare staggers the time, and withdraws from read states, simultaneously corresponding address wire test result status register is delivered in this address.
Withdraw from address wire test, the end of test (EOT) position 1 in the test state register.
The ram memory cell testing process as shown in Figure 5.The prerequisite of storage unit test is that tentation data line, address wire are correct.
Its testing procedure is as follows:
Guaranteeing to carry out the storage unit test under the correct situation of address wire, data line.Utilize the chessboard graphic-arts technique that strides that each address is write 0101...0101 continuously by ascending order, the address since 0 sense data relatively, find that wrong mistake withdraws from test and simultaneously corresponding storage unit test result status register delivered in this address, compare OK, this address writes 10100....1010, the address adds 1 read-around ratio simultaneously, carry out top-operation repeatedly, address to the last. then, the address press descending one by one read-around ratio find that wrong mistake withdraws from test and simultaneously 0 corresponding storage unit test result status register, compare OK delivered in this address, this address writes 0101....0101, up to the lowest order address.
Its logic realization is:
(1), writes state continuously: each address is write 0101...0101. continuously by ascending order since 0 address;
(2), read-around ratio is than state 1: the address since 0 sense data relatively, find that wrong mistake withdraws from test and simultaneously corresponding storage unit test result status register delivered in this address, compare OK, this address writes 1010...1010., the address adds 1 read-around ratio simultaneously, carry out top-operation repeatedly, to the last the address.
(3), read-around ratio is than state 2: descending is pressed in the address, and read-around ratio is one by one, find that wrong mistake withdraws from test and simultaneously corresponding storage unit test result status register delivered in this address, compare OK, this address writes 0101....0101, up to the lowest order address.
Withdraw from storage unit test test, the end of test (EOT) position 1 in the test state register.
The present invention can use the RAM production test, the power-on self-test of the production Equipment Test of band RAM product and band RAM equipment etc.The production Equipment Test of the multiple veneer on certain communication product, the practical operation situation ideal, its detection speed to high capacity RAM is fast, fault recall rate height, positioning problems is detailed, has good using value.
Claims (8)
1, a kind of RAM high speed test control circuit is characterized in that comprising:
Cpu interface circuit is used to be provided with the state of test command register, the corresponding test result register of gating, the information of read test result phase register record;
RAM reads and writes control interface, is used to connect tested RAM, the control read/write data;
The test result status register, it is connected with cpu interface circuit, comprises test state register, data line test result status register, address wire test result status register and storage unit testing result phase register;
The test command register contains test enable register and content measurement mask register, receives the command selection test-types of cpu interface circuit;
And testing circuit, contain data line test, address wire test and storage unit test module, be connected with the test result status register with RAM read-write control interface respectively, finish tested RAM data line, address wire and storage unit test according to the test command buffer status.
2, according to the described RAM high speed test control circuit of claim 1, it is characterized in that: in described test result status register, data line test result status register is a same wide register with the data line width; Address wire test result status register is a same wide register with the address wire width; Storage unit testing result phase register contains 2 registers, its bit wide all equals the width of address wire, one of them register is used for noting down the start address of storage unit test failure, and another register is used for noting down the number of unit of storage unit test errors.
3, detect control circuit according to the described RAM of claim 1, it is characterized in that: in the test result status register, described test state register is the register of a 5bit, and wherein everybody is defined as detected state respectively, detects end, address wire mistake, data line mistake and storage unit error register.
4, a kind of RAM high speed test method is characterized in that taking following steps:
A, the state of test command register is set, selects data line, address wire and storage unit test by cpu interface circuit, and the corresponding test result status register of gating;
B, detection data line, some groups of setting datas are write tested RAM step by step, reading corresponding data in each step compares with the setting data that writes respectively, if relatively make mistakes, put error flag and data line test result status register, withdraw from test, otherwise enter the comparison process of next group data;
C, detection address wire write some groups of particular address data to tested RAM, read the corresponding address data and compare with the particular address data that write respectively, compare and stagger the time, and put error flag and address wire test result status register, withdraw from the address wire test;
The graphic-arts technique that strides d, employing chessboard detects the storage unit of tested RAM, if wrong, send storage unit test result status register appropriate address.
E, read the information of corresponding test result status register record, analysis and judgement ram error type by cpu interface circuit.
5, a kind of RAM high speed test method is characterized in that taking following steps:
A ', the state of test command register is set, selects address wire, data line and storage unit test by cpu interface circuit, and the corresponding test result status register of gating;
B ', detection address wire write some groups of particular address data to tested RAM, read the corresponding address data and compare with the particular address data that write respectively, compare and stagger the time, and put error flag and address wire test result status register, withdraw from the address wire test;
C ', detection data line, some groups of setting datas are write tested RAM step by step, reading corresponding data in each step compares with the setting data that writes respectively, if relatively make mistakes, put error flag and data line test result status register, withdraw from test, otherwise enter the comparison process of next group data;
The graphic-arts technique that strides d ', employing chessboard detects the storage unit of tested RAM, if wrong, send storage unit test result status register appropriate address.
E ', read the information of corresponding test result status register record, analysis and judgement ram error type by cpu interface circuit.
6, according to claim 4 or 5 described RAM high speed test methods, it is characterized in that: in detecting data line, described setting data is complete 0, complete 1,1010 ... 1010,0101 ... 0101, walking 0 algorithm data and walking 1 algorithm data.
7, according to claim 4 or 5 described RAM high speed test methods, it is characterized in that: in detecting address wire, described particular address data are all zeros address, all ones address, 1010 ... 1010 addresses, 0101 ... 0101 address, walking 0 algorithm address and walking 1 algorithm address.
8, a kind of RAM high speed test method is characterized in that taking following steps:
A ", by cpu interface circuit the state of test command register is set, select storage unit test, and gating storage unit test result status register;
B ", adopt the chessboard graphic-arts technique that strides to detect the storage unit of tested RAM, if wrong, send storage unit test result status register appropriate address;
C ", the information by cpu interface circuit reading cells test result status register record, the analysis and judgement ram error.
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2001
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