CN1619705A - Testing method of multiport storage - Google Patents
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Abstract
This invention refers to a testing method for multiport memory, which contains: (1),testing the periphery interconnection line of every port in turn, making fault diagnosis if it is occurred, if no fault occurred executing following steps, (2), testing memory array of multiport memory through one port of it, reporting the fault occurring address. if the fault exists in internal storage unit, if no fault occurred executing following steps, (3), testing address decoder and input/output controller of residual ports in turn, making fault diagnosis if it is occurred, if no fault occurred the test is over. Said method can test the normal fault for data line, address line, control line, arbitrator, address decoder and input/output controller with accuracy fault location.
Description
Technical field
The present invention relates to the measuring technology of electronics or the communications field, specifically refer to a kind of method of testing of multiport memory.
Background technology
Multiport memory has a plurality of independently access ports, and each port has independently control, address, data pin, allows from each end any unit the read-write memory independently. And common be the dual-ported memory (being also referred to as mailbox) that possesses two ports, as shown in Figure 1. Dual-ported memory (mailbox) generally is comprised of following part: address decoder, the i/o controller of storage array, flag moderator and both sides, carry out BUSY holding wire and the INT holding wire of bus arbitration in addition.
The fault of control line mainly comprises fixed logic fault, stuck-open fault and bridge joint short trouble. Because it is less that control line compares, and the fault of control line is very obvious. The fault of control line just can be found when data wire and address wire are carried out basic test, so can generally separately control line not tested.
The fault of data wire, address wire and control line also all is the fault of peripheral interconnection line, generally all is to set up stuck-at fault model. So the fault of data wire and address wire mainly also is fixed logic fault, stuck-open fault and bridge joint short trouble (Short fault). The bridge joint short trouble comprises again two kinds of 0-dominance short trouble and 1-dominance short troubles.
The reason that the moderator fault produces may be varied, but unification shows as and can't correctly control the read-write operation authority. The moderator fault also is very obvious, and can detect the fault in the moderator in the content measurement afterwards, so generally also can not do special test to the fault of moderator.
The fault of storage array mainly is summed up as six class faults: fixed logic fault, stuck-open fault, state translation exception, data keep fault, state coupling fault and multiple Write fault.
The fault main manifestations of address decoder is not for choosing arbitrary memory cell or choosing selected cell to choose simultaneously other unit. Fault in the decoder can equivalence be the fault in the memory cell array.
The fault of i/o controller mainly contains: one or more fixed logic faults in input, the output lead; One or more stuck-open faults in buffer or the latch; State coupling fault in buffer or the latch between any two. The fault of read-write in the logic circuit also can equivalence be the fault in the memory cell array.
Because to the complete fault of cover data line, address wire, control line and moderator of the complete test of storage display; And the fault of address decoder, i/o controller is equal to again the fault of memory array, so the method that the method for test multiport memory is namely tested multi-port memory array.
And main multiport memory is exactly mailbox, can very naturally promote the use of in the test of multiport memory for the method for testing of mailbox.
Now general method of testing and process are as follows:
1) initializes mailbox;
2) the mailbox left-sided system obtains flag, and wide each the unit identical data of mailbox that writes successively of word on request discharges flag;
3) the mailbox right-sided system obtains flag, reads the data in the mailbox, verification, and the mistake of statistics number then with data-conversion, writes mailbox, discharges flag;
4) the mailbox left-sided system obtains flag, reads the data in the mailbox, verification, and the mistake of statistics number discharges flag.
Last mistake of statistics number if wrong number is 0, then shows and does not find fault, if wrong number is not 0, then there is fault in report.
Method of testing and process for multiport memory also are similarly (explanations as an example of the K port store example):
1) initializes the K port store;
2) the 1st port one side system of K port store obtains flag, and wide each the unit identical data of mailbox that writes successively of word on request discharges flag;
3) the 2nd port one side system of K port store obtains flag, reads the data in the mailbox, verification, and the mistake of statistics number then with data-conversion, writes mailbox, discharges flag;
……
K+1) K port one side system of K port store obtains flag, reads the data in the mailbox, verification, and the mistake of statistics number then with data-conversion, writes mailbox, discharges flag;
K+2) the 1st port one side system of K port store obtains flag, reads the data in the mailbox, verification, and the mistake of statistics number discharges flag.
Last mistake of statistics number if wrong number is 0, then shows and does not find fault, if wrong number is not 0, then there is fault in report.
The shortcoming of prior art: this test is fairly simple, can detect partial fixing logic fault, partial fixing open fault, partial data maintenance fault. Can only cover seldom state translation exception, state coupling fault and multiple Write fault. This method of testing test is very incomplete, and can not be to diagnosing malfunction and location.
Summary of the invention
The present invention proposes a kind of method of testing of multiport memory, the problem of can not complete test when the test multiport memory and can not diagnose and locate to solve method of testing in the prior art.
For addressing the above problem, the invention provides following technical scheme:
A kind of method of testing of multiport memory comprises the following steps:
(1), at first successively test the peripheral interconnection line of each port, if peripheral interconnection line has fault, then carry out fault diagnosis; If peripheral interconnection line is not found fault, then carry out the following step;
(2), by a port of multiport memory the storage array of multiport memory is tested, if there is fault in the memory inside memory cell, the report address of breaking down then; If do not find fault, then carry out the following step;
(3), successively address decoder and the i/o controller of remaining port are tested, if address decoder and i/o controller have fault, then carry out fault diagnosis; If do not find fault, then test finishes.
Wherein, the test of described peripheral interconnection line comprises the following steps:
(11) in two different addresses, with stuck-open fault and the fixed logic fault of one group of complete " 1 " data and one group of complete " 0 " Data Detection data wire;
(12) fix an address, test data adopts respectively " walking 1 matrix " and " walking 0 matrix ", detects the short trouble of data wire;
(13) test address and test data are " walking 1 matrix ", and increase by one group of complete " 0 " address and complete " 0 " data, test one time; Test address and test data are " walking 0 matrix ", and increase by one group of complete " 1 " address and complete " 1 " data, test one time again, detect address wire stuck-open fault, fixed logic fault and bridge joint short trouble.
Described step is tested the storage array of multiport memory in (2), is to adopt a kind of " 01...0101 " and " 10...1010 " staggered data block to test, and specifically comprises the steps:
(21) the address ascending order is write " 01...0101 ";
(22) the address ascending order is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(23) the address ascending order is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(24) the address descending is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(25) the address descending is read " 10...1010 ", and verification writes " 01...0101 " immediately.
Above-mentioned read-write process also can be to carry out according to the address descending; Simultaneously, the order of data writing also can be to write first " 10...1010 ", after write " 01...0101 ".
Address decoder and i/o controller to remaining port in the described step (3) are tested, and specifically comprise:
(31) if data wire more than or equal to address wire, then all address spaces are tested as a monoblock;
(32) if data wire is less than address wire, then according to the number of data wire the address space piecemeal to be tested, each block size is exactly the maximum data that data wire can represent.
In the said method, within each address block, address corresponding to each data is unique, and data corresponding to each address also are unique simultaneously.
Describedly address space is divided into a plurality of address blocks tests, comprising: 0 data writing 0 first address, address 1 data writing 1 ..., until last address of first writes maximum data; The data that write in the second block address are to roll once on the basis of the first block address data writing, namely successively data writing 1,2 ..., maximum data, 0; The data that write in the 3rd block address are to roll once on the basis of the second block address data writing ..., the rest may be inferred, write all address blocks after, read successively from low to high or from high to low by the address and to compare.
Described address space is tested as a monoblock, comprise: number of addresses is high-order as data writing, append to again the low level of data writing according to one or more high positions of the figure place of data wire intercepting number of addresses, the said write data are written in the address location corresponding with described number of addresses, then read verification.
This method of testing of the present invention can detect fixed logic fault, stuck-open fault, state translation exception, the six class most common failures such as data maintenance fault, state coupling fault and multiple Write fault fully, and has covered the fault of data wire, address wire, control line, moderator, address decoder and i/o controller fully. This method of testing test is very complete, and fault location is accurate.
Description of drawings
Fig. 1 is the general structure figure of dual-ported memory.
Fig. 2 A, Fig. 2 B are the flow chart that the present invention detects memory array.
The specific embodiment
The invention provides a kind of method that multiport memory is carried out complete test, at first discuss the method for testing of dual-ported memory, then be generalized in the multiport memory test.
Method of testing and the step of dual-ported memory are as follows:
(1) tests at first successively the peripheral interconnection line (comprising data wire, address wire, control line) at two ends, the read-write control is obtained in the left side, use " three-step approach " test left side peripheral interconnection line, the left side discharges the read-write control, the read-write control is obtained on the right side, uses " three-step approach " test right side peripheral interconnection line.
So-called " three-step approach " is a kind of method of testing for peripheral interconnection line that the present invention proposes, and this method of testing not only can accurately be located fault, and it is dissimilar to distinguish two kinds of bridge joint short trouble. The method of testing of " three-step approach " and step such as following table:
| Testing procedure | Operation | The address | Data | Note | |
| The first | Write | A | 0...000 | A, B compare verification when being any two different address read, test data is one group complete " 0 " and one group complete " 1 ". | |
| Write | B | 1...111 | |||
| | A | 0...000 | |||
| Read | B | 1...111 | |||
| Second step a | | A | 0...001 | A is any fixed address, compares verification when reading. Test data is " walking 1 matrix " (the diagonal of a matrix data is 1, and the data of all the other positions are 0, similar 1 forward or backward walking, therefore named walking 1 matrix). | |
| Read | A | 0...001 | |||
| | A | 0...010 | |||
| | A | 0...010 | |||
| ...... | ...... | ...... | |||
| ...... | ...... | ...... | |||
| Write | A | 1...000 | |||
| Read | A | 1...000 | |||
| Second step b | Write | A | 1...110 | A is any fixed address, compares verification when reading. Test data is " walking 0 matrix " (the diagonal of a matrix data is 0, and the data of all the other positions are 1, similar 0 forward or backward walking, therefore named walking 0 matrix). | |
| Read | A | 1...110 | |||
| Write | A | 1...101 | |||
| Read | A | 1...101 | |||
| ...... | ...... | ...... | |||
| ...... | ...... | ...... | |||
| Write | A | 0...111 | |||
| | A | 0...111 | |||
| The 3rd step a | | 0...001 | 0...001 | Test address and test data are " walking 1 matrix ", increase at last one group of complete " 0 " address and complete " 0 " data again. Compare verification when reading, if finish to find fault at the 3rd step a, carry out first fault diagnosis, location fixed | |
| Write | 0...010 | 0...010 | |||
| ...... | ...... | ...... | |||
| Write | 1...000 | 1...000 | |||
| | 0...000 | 0...000 | |||
| | 0...001 | 0...001 | |||
| | 0...010 | 0...010 |
| ...... | ...... | ...... | ||
| Read | 1...000 | 1...000 | ||
| | 0...000 | 0...000 | ||
| The 3rd step b | Write | 1...110 | 1...110 | Test address and test data are " walking 0 matrix ", increase at last one group of complete " 1 " address and complete " 1 " data again. Compare verification when reading, if finish to find fault at the 3rd step b, carry out first fault diagnosis, location fixed logic 1 fault and 0-dominance short trouble. |
| Write | 1...101 | 1...101 | ||
| ...... | ...... | ...... | ||
| Write | 0...111 | 0...111 | ||
| Write | 1...111 | 1...111 | ||
| Read | 1...110 | 1...110 | ||
| Read | 1...101 | 1...101 | ||
| ...... | ...... | ...... | ||
| Read | 0...111 | 0...111 | ||
| Read | 1...111 | 1...111 |
First step test is used for the test data line and whether has open fault and fixed logic fault, and the second step test is used for the test data line and whether has short trouble, and the 3rd pacing tries out the test address line whether to have open circuit or short trouble. Finish to carry out the data wire fault diagnosis in the second step test, finish to carry out the address alignment fault diagnosis in the 3rd pacing examination.
The fault diagnosis of first step test is fairly simple, does not read full 0 if write full 0, just illustrates that there is the fault of S-A-1 in data wire, and numerical value is that 1 data wire is exactly the fault wire position that S-A-1 occurs. Opposite situation is not read entirely 1 if write complete 1, just illustrates that there is the fault of S-A-0 in data wire, and the data wire of value bit 0 is exactly the linear position data that the S-A-0 fault occurs. Why utilizing the open fault of two different address test data lines, is for the detection of the data latch-up that prevents from may existing on data/address bus impact to the data wire open fault.
The second step test need to be judged the linear position data of short trouble and the short trouble of what type, the below is that of second step test illustrates that (walking that please notes " 0 " and " 1 " in walking 0 and walking 1 algorithm both can be gone to low level from a high position, also can go to a high position from low level), tentation data line b3b
2b
1b
0, test vector r0r
1...r
7。
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| Desired value | b 2Open circuit S-A-0 | b 2And b1Open circuit S-A-0 | b 2And b1Short circuit 0-dominance | b 2And b1Open circuit S-A-1 | b 2And b1Short circuit 1-dominance | b 3And b0Open circuit S-A-0 b2And b1Short circuit 0-dominance | |
| b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | b 3b 2b 1b 0 | |
| r 0 | 1000 | 1000 | 1000 | 1000 | 1110 | 1000 | 0000 |
| r 1 | 0100 | 0000 | 0000 | 0000 | 0110 | 0110 | 0000 |
| r 2 | 0010 | 0010 | 0000 | 0000 | 0110 | 0110 | 0000 |
| r 3 | 0001 | 0001 | 0001 | 0001 | 0111 | 0001 | 0000 |
| r 4 | 0111 | 0011 | 0001 | 0111 | 0111 | 0111 | 0110 |
| r 5 | 1011 | 1011 | 1001 | 1001 | 1111 | 1111 | 0000 |
| r 6 | 1101 | 1001 | 1001 | 1001 | 1111 | 1111 | 0000 |
| r 7 | 1110 | 1010 | 1000 | 1110 | 1110 | 1110 | 0110 |
Note that when the test data line must fix an address and carry out, so no matter what fault is address wire exist, and do not affect the test result of data wire. After the data wire test finishes, just go to do the address wire test.
Diagnostic process to the open fault of data wire and short trouble is as follows:
BEGIN
Each row V of the actual test response matrix V of FORi
IF V
iRespective column T with the Expected Response matrix TiInconsistent
There is fault in report;
IF V
iEach component be fixed as 1
Report that 1 open fault has occured to be fixed as i bar data wire;
ELSE IF V
iEach component be fixed as 0
Report that 0 open fault has occured to be fixed as i bar data wire;
There are a plurality of row in ELSE IF, and its vector equates that its value is the result of the logic OR computing of the Expected Response of these several row
1-dominance short trouble occurs in many data wires of report respective column
There are a plurality of row in ELSE IF, and its vector equates that its value is the result of the logic and operation of the Expected Response of these several row
0-dominance short trouble occurs in many data wires of report respective column
ELSE
The report fault type can't be judged, reports simultaneously which data lines is fault occur on
END IF
END IF
END FOR
There is not fault in IF
Fault is not found in the test of report data line;
END。
After guaranteeing that data wire does not have fault, can carry out the 3rd pacing examination, address wire is tested, the below is that of the 3rd pacing examination illustrates, and supposes that address wire is a3a
2a
1a
0, test data is different, and numerical value equates with the address.
| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| Address a3a 2a 1a 0 | Desired value | a 2Open circuit S-A-0 | a 2And a1Open circuit S-A-0 | a 2And a1Short circuit 0-dominance | a 2And a1Open circuit S-A-1 | a 2And a1Short circuit 1-dominance | a 3And a0Open circuit S-A-0 a2And a1Short circuit 0-dominance |
| 0001 | 0001 | 0001 | 0001 | 0001 | 0001 | 0001 | 0000 |
| 0010 | 0010 | 0010 | 0000 | 0000 | 0000 | 0100 | 0000 |
| 0100 | 0100 | 0000 | 0000 | 0000 | 0000 | 0100 | 0000 |
| 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | 0000 |
| 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 | 0000 |
| 1110 | 1110 | 1110 | 1110 | 1110 | 1110 | 1110 | 1111 |
| 1101 | 1101 | 1101 | 1111 | 1011 | 1111 | 1111 | 1011 |
| 1011 | 1011 | 1111 | 1111 | 1011 | 1111 | 1111 | 1011 |
| 0111 | 0111 | 0111 | 0111 | 0111 | 0111 | 0111 | 1111 |
| 1111 | 1111 | 1111 | 1111 | 1111 | 1111 | 1111 | 1111 |
Diagnosis principle and data wire fault diagnosis to address wire open fault and short trouble are similar, and roughly flow process is as follows:
BEGIN
Analyze first the test response of walking 1
It is in full accord that IF reads the data of data and expectation
Report address wire walking 1 test of heuristics is not found fault;
ELSE
FOR analyzes the value of reading back and inconsistent each address of desired value
The data that the non-all zeros address of IF reads back are full 0
Record, may be fixed logic 0 fault, abort situation is the address wire of the corresponding numeral in this address " 1 "
The data that ELSE IF exists a plurality of addresses to read back equate, and non-full 0
Recording, is 1 dominance short trouble, the address wire short circuit of the different address bit of corresponding these several addresses
ELSE
The report fault type can't be judged, reports simultaneously which address is fault occur on.
END FOR
Analyze first again the test response of walking 0
It is in full accord that IF reads the data of data and expectation
Report address wire walking 0 test of heuristics is not found fault;
ELSE
FOR analyzes the value of reading back and inconsistent each address of desired value
The data bit complete 1 that the non-all ones address of IF reads back
Record, may be fixed logic 1 fault, abort situation is the address wire of the corresponding digital " 0 " in this address
The data that ELSE IF exists a plurality of addresses to read back are equal, and non-complete 1
Recording, is 0 dominance short trouble, the address wire short circuit of the different address bit of corresponding these several addresses
ELSE
The report fault type can't be judged, reports simultaneously which address is fault occur on.
END FOR
At last diagnostic result is carried out analysis-by-synthesis
There is the address wire of fault in FOR
This address wire of IF is judged as 0-dominance short trouble or 1-dominance short trouble
Conclude that then this address wire is 0-dominance short trouble or 1-dominance short trouble
This address wire of ELSE IF is judged as fixed logic 0 fault or fixed logic 1 fault
Conclude that then this address wire is fixed logic 0 fault or fixed logic 1 fault
This address wire of ELSE IF is judged as fixed logic 0 fault or fixed logic 1 fault simultaneously
Conclude that then this address wire is the fixed logic fault
ELSE
This address wire exist can't the failure judgement type fault.
END FOR
END
Suppose that the address wire number is d, the data wire number is n, then need to carry out the inferior operation that reads or writes of 4* (n+d+1) to memory cell altogether. Three-step approach all is 100% to the fault coverage of fixed logic fault (Stuck-at fault), stuck-open fault (Stuck-open fault) and bridge joint short trouble (Short fault), and can carry out accurately fault diagnosis, distinguish dissimilar short troubles.
(2) if there is fault in peripheral interconnection line, then carry out fault diagnosis; If do not find fault, then by a side system of dual-ported memory the storage array of dual-ported memory to be tested, testing algorithm can adopt " nine step checkerboard pattern methods ". (note when storage array is tested, also just address decoder and the i/o controller of this side of dual-ported memory carried out testing completely)
So-called " nine step checkerboard pattern methods ", it is exactly the form that when detecting data cell, adopts checkerboard pattern, when detecting address decoding, adopt the method for testing of nine steps, concrete execution flow process is shown in Fig. 2 A, Fig. 2 B, the characteristics of this method of testing are: the form of the similar checkerboard pattern of test data, namely data " 01...0101 " and " 10...1010 " staggered form; Test is divided into 5 steps, 9 times read-write operations, 1., the address ascending order writes " 01...0101 ", 2., the address ascending order reads " 01...0101 ", verification writes " 10...1010 " immediately, 3., the address ascending order reads " 10...1010 ", verification writes " 01...0101 " immediately, 4., the address descending is read " 01...0101 ", 5., the address descending reads " 10...1010 " verification writes " 10...1010 " immediately,, verification writes " 01...0101 " immediately. Test data in the above step " 01...0101 " and " 10...1010 " can exchange, and do not affect the test effect; In like manner, also may carry out according to the step of address ascending order more first according to the address descending, also do not affect the test effect.
Nine step checkerboard pattern methods all are complete to the test of fixed logic fault, stuck-open fault, state translation exception, state coupling fault and multiple Write fault. This method of testing need to be carried out 5 times write operations and 4 times read operations to memory, comes to read-write operation 9 times, and the test data that adopts is chessboard alternating graph mode, so be referred to as in the present invention nine step checkerboard pattern methods.
(3) if find in the 2nd pacing examination that there is fault in the dual-ported memory internal storage unit, then reports the address of breaking down; If do not find fault, then address decoder and the i/o controller of opposite side to be tested, testing algorithm can adopt " unique address/data method ".
" unique address/data method " that the present invention proposes can partly effectively be tested address decoder and i/o controller. Owing to a side of dual-ported memory has been carried out the test of nine step checkerboard pattern methods, so except storage array has been carried out Complete test, also address decoder and the i/o controller of this side has been carried out Complete test. But address decoder and the i/o controller of an other side are not also tested. If the test of at this moment carrying out opposite side with nine step checkerboard pattern methods again just obviously has some unnecessary. Because need now the just address decoder of test and the fault of i/o controller. So to the test of address decoder and i/o controller, just suitable employing a kind of more fast method of testing---" unique address/data method ".
The step of this method of testing is as follows:
If data wire is less than the situation of address wire, then according to the number of data wire with the address space piecemeal, each block size is exactly the maximum data that data wire can represent, then guarantee within each piece, address corresponding to each data is unique (obviously data corresponding to each address also are unique in each piece), guarantee as far as possible that simultaneously between piece and the piece, test data is removed beyond the high position of increase, the data of corresponding identical address low level are also different.
Concrete method of operating is exactly address 0 data writing 0 at first, address 1 data writing 1 ..., until last address of first writes maximum data. The data scrolling that writes in the second block address once, namely successively data writing 1,2 ..., maximum data, 0. Roll again once in the data that the 3rd block address writes ..., the rest may be inferred. Read successively from low to high by the address at last and compare.
Give one example to illustrate that the tentation data line has 4, address wire is more than 4 situation. Then unique address/data method is carried out read-write operation one time, the data that write and read such as following table:
| Piece number | The address | Data | ||
| The decimal system | Binary system | Binary | Hexadecimal | |
| Block1 | ||||
| 0 | 0000 | 0000 | 0 | |
| 1 | 0001 | 0001 | 1 | |
| 2 | 0010 | 0010 | 2 | |
| ...... | ...... | ...... | ...... | |
| 15 | 1111 | 1111 | F | |
| Block2 | 16 | 10000 | 0001 | 1 |
| 17 | 10001 | 0010 | 2 | |
| ...... | ...... | ...... | ...... | |
| 30 | 11110 | 1111 | F | |
| 31 | 11111 | 0000 | 0 | |
| Block3 | 32 | 100000 | 0010 | 2 |
| 33 | 100001 | 0011 | 3 | |
| ...... | ...... | ...... | ...... | |
| 45 | 101101 | 1111 | F | |
| 46 | 101110 | 0000 | 0 | |
| 47 | 101111 | 0001 | 1 | |
| Block4 | 48 | 110000 | 0010 | 3 |
| 49 | 110001 | 0011 | 4 | |
| ...... | ...... | ...... | ...... | |
| 61 | 111101 | 1111 | 0 | |
| 62 | 111110 | 0000 | 1 | |
| 63 | 111111 | 0001 | 2 | |
| ...... | ...... | ...... | ...... | ...... |
Can find out from above example, within each piece, address corresponding to each data is unique (data corresponding to each address also are unique in each piece certainly), removes simultaneously beyond the high position of increase, and address low level corresponding to the data of different masses also is mutually different. First address " 0000 " corresponding data " 0 " for example; The address high-order " 1 " of increase is removed in second address, and the data that address low level " 0000 " is corresponding are " 1 "; The address high-order " 10 " of increase is removed in the 3rd address, and the data that address low level " 0000 " is corresponding are " 2 "; The address high-order " 11 " of increase is removed in the 4th address, and the data that address low level " 0000 " is corresponding are " 3 " .... After processing like this, when appearring in the high address line, stuck-at fault also can be detected. Be not difficult to find out simultaneously that Block2 and Block4 remove after the address high-order " 1 " of increase, the data block of corresponding address piece is not identical yet yet.
If address wire is less than the situation of data wire, then only need to write one time by the address, read through. The numeral that each address writes obtains like this: number of addresses is high-order as data, and a high position that intercepts again the address appends to the low level of number of addresses as the data that write. Suppose that the address is 3, data wire is 4. The high position of address 001 is 0 so, and the low level that appends to number of addresses obtains 0010, and then the data that write of address 001 are 0010, shown in seeing the following form:
| Address (three) | Data (four) |
| 000 | 0000 |
| 001 | 0010 |
| 010 | 0100 |
| 011 | 0110 |
| 100 | 1001 |
| 101 | 1011 |
| 110 | 1101 |
| 111 | 1111 |
The address is 3 for another example, and data are 5 situation, and then the data that write of address 010 are 01001, and the data that address 101 writes are 10101. If address wire is far smaller than data wire, then need repeatedly to intercept, be 3 such as the address, data are 8, and then address 010 data writing is 01001001, and the data that address 101 writes are 10110110.
Unique address/data method can compare to the fault of address decoder and i/o controller completely test, and it only need to carry out a write operation and a read operation, is a kind of quite effectively method of testing.
(4) if the 3rd step was found fault, report that then there are fault in the address decoder of this side or i/o controller; Otherwise all test events are finished, and the report dual-ported memory is normal.
If the various piece of K port store is compared completely test, then testing procedure is as follows:
(1) test at first successively the peripheral interconnection line of each port, specific operation process and dual-ported memory test class are seemingly.
(2) if peripheral interconnection line has fault, then carry out fault diagnosis; If do not find fault. Then by a side system of K port store the storage array of K port store is tested, testing algorithm can adopt nine step checkerboard pattern methods. Attention has also just been carried out completely test to the address decoder of this side of K port store and i/o controller when storage array is tested.
(3) there is fault if K port store internal storage unit is found in the 2nd pacing examination, then reports the address of breaking down; If do not find fault, then successively address decoder and the i/o controller of remaining port partly to be tested, testing algorithm adopts unique address/data method.
(4) if fault is found in the 3rd pacing examination, report that then there are fault in the address decoder of all the other multiports or i/o controller; Otherwise all test events are finished, and the report multiport memory is all normal.
Claims (10)
1, a kind of method of testing of multiport memory is characterized in that, the method comprises the following steps:
(1), successively test the peripheral interconnection line of each port, if peripheral interconnection line has fault, then carry out fault diagnosis; If peripheral interconnection line is not found fault, then carry out the following step;
(2), by a port of multiport memory the storage array of multiport memory is tested, if there is fault in the memory inside memory cell, the report address of breaking down then; If do not find fault, then carry out the following step;
(3), successively address decoder and the i/o controller of remaining port are tested, if address decoder and i/o controller have fault, then carry out fault diagnosis; If do not find fault, then test finishes.
2, the method for testing of multiport memory as claimed in claim 1 is characterized in that: to the test of peripheral interconnection line, comprise the following steps: in the described step (1)
(11) in two different addresses, with stuck-open fault and the fixed logic fault of one group of complete " 1 " data and one group of complete " 0 " Data Detection data wire;
(12) fix an address, test data adopts respectively " walking 1 matrix " and " walking 0 matrix ", detects the short trouble of data wire;
(13) test address and test data are " walking 1 matrix ", and increase by one group of complete " 0 " address and complete " 0 " data, test one time; Test address and test data are " walking 0 matrix ", and increase by one group of complete " 1 " address and complete " 1 " data, test one time again, detect address wire stuck-open fault, fixed logic fault and bridge joint short trouble.
3, the method for testing of multiport memory as claimed in claim 1 or 2, it is characterized in that: described step is tested the storage array of multiport memory in (2), be to adopt a kind of " 01...0101 " and " 10...1010 " staggered data block to test, specifically comprise the steps:
(21), the address ascending order is write " 01...0101 ";
(22), the address ascending order reads " 01...0101 ", verification writes " 10...1010 " immediately;
(23), the address ascending order reads " 10...1010 ", verification writes " 01...0101 " immediately;
(24), the address descending reads " 01...0101 ", verification writes " 10...1010 " immediately;
(25), the address descending reads " 10...1010 ", verification writes " 01...0101 " immediately.
4, the method for testing of multiport memory as claimed in claim 1 or 2, it is characterized in that: described step is tested the storage array of multiport memory in (2), be to adopt a kind of " 01...0101 " and " 10...1010 " staggered data block to test, specifically comprise the steps:
(21) the address descending is write " 01...0101 ";
(22) the address descending is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(23) the address descending is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(24) the address ascending order is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(25) the address ascending order is read " 10...1010 ", and verification writes " 01...0101 " immediately.
5, the method for testing of multiport memory as claimed in claim 1 or 2, it is characterized in that: described step is tested the storage array of multiport memory in (2), be to adopt a kind of " 01...0101 " and " 10...1010 " staggered data block to test, specifically comprise step:
(21) the address ascending order is write " 10...1010 ";
(22) the address ascending order is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(23) the address ascending order is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(24) the address descending is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(25) the address descending is read " 01...0101 ", and verification writes " 10...1010 " immediately.
6, the method for testing of multiport memory as claimed in claim 1 or 2, it is characterized in that: described step is tested the storage array of multiport memory in (2), be to adopt a kind of " 01...0101 " and " 10...1010 " staggered data block to test, specifically comprise the steps:
(21) the address descending is write " 10...1010 ";
(22) the address descending is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(23) the address descending is read " 01...0101 ", and verification writes " 10...1010 " immediately;
(24) the address ascending order is read " 10...1010 ", and verification writes " 01...0101 " immediately;
(25) the address ascending order is read " 01...0101 ", and verification writes " 10...1010 " immediately.
7, the method for testing of multiport memory as claimed in claim 1 or 2 is characterized in that: address decoder and i/o controller to remaining port in the described step (3) are tested, and specifically comprise:
(31) if data wire more than or equal to address wire, then all address spaces are tested as a monoblock;
(32) if data wire is less than address wire, then according to the number of data wire the address space piecemeal to be tested, each block size is exactly the maximum data that data wire can represent.
8, the method for testing of multiport memory as claimed in claim 7 is characterized in that: within each address block, address corresponding to each data is unique, and corresponding data also are unique in each address simultaneously.
9, such as the method for testing of claim 7 or 8 described multiport memories, it is characterized in that: describedly address space is divided into a plurality of address blocks tests, comprise: 0 data writing 0 first address, address 1 data writing 1, ..., until last address of first writes maximum data; The data that write in the second block address are to roll once on the basis of the first block address data writing, namely successively data writing 1,2 ..., maximum data, 0; The data that write in the 3rd block address are to roll once on the basis of the second block address data writing ..., the rest may be inferred, write all address blocks after, read successively from low to high or from high to low by the address and to compare.
10, such as the method for testing of claim 7 or 8 described multiport memories, it is characterized in that: described address space is tested as a monoblock, comprise: number of addresses is high-order as data writing, append to again the low level of data writing according to one or more high positions of the figure place of data wire intercepting number of addresses, the said write data are written in the address location corresponding with described number of addresses, then read verification.
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| US5481671A (en) * | 1992-02-03 | 1996-01-02 | Advantest Corporation | Memory testing device for multiported DRAMs |
| JPH0773699A (en) * | 1993-09-02 | 1995-03-17 | Sony Corp | Test circuit for embedded dualport memory |
| JP2905394B2 (en) * | 1994-05-18 | 1999-06-14 | 川崎製鉄株式会社 | Test method for dual port RAM |
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