CN108376701B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN108376701B
CN108376701B CN201711444099.4A CN201711444099A CN108376701B CN 108376701 B CN108376701 B CN 108376701B CN 201711444099 A CN201711444099 A CN 201711444099A CN 108376701 B CN108376701 B CN 108376701B
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insulating film
region
semiconductor substrate
outer edge
tapered portion
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CN108376701A (zh
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阿形泰典
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Abstract

本发明期望调整电位梯度的变化，以便不会因电阻膜的电场而在位于电阻膜下的半导体基板产生雪崩。本发明提供半导体装置，该半导体装置具备半导体基板，半导体基板具有：边缘终端部，其包含外缘区域，所述外缘区域在半导体基板的表面的端部设置于预定的深度范围且是杂质区域；以及有源部，其包含阱区，所述阱区在半导体基板的表面的比外缘区域靠内侧的位置设置于预定的深度范围且是导电型与半导体基板的漂移区的导电型不同的杂质区域，半导体装置还具备：绝缘膜，其在半导体基板的表面上，至少设置于外缘区域与阱区之间，且具有锥形部；以及电阻膜，其设置于绝缘膜上，将外缘区域与阱区电连接，绝缘膜的锥形部的锥角为60度以下。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
以往，作为耐压结构，已知有电阻膜以及导电性场板(例如，参照专利文献1以及专利文献2)。
[现有技术文献]
[专利文献]
专利文献1：日本专利第3117023号公报
专利文献2：日本专利第2712098号公报
发明内容
技术问题
在将基区与阻止区电连接的电阻膜，相应于基区与阻止区的电位差而形成电位梯度。相应于该电位梯度，在电阻膜可形成电场。期望调整电位梯度的变化，以便不会因电阻膜的电场而在位于电阻膜下的半导体基板产生雪崩。
技术方案
在本发明的第一方式中，提供半导体装置。半导体装置可以具备半导体基板、绝缘膜和电阻膜。半导体基板可以具有边缘终端部和有源部。边缘终端部可以包含外缘区域。外缘区域可以在半导体基板的表面的端部设置于预定的深度范围。外缘区域可以是杂质区域。有源部可以包含阱区。阱区可以在半导体基板的表面的比外缘区域靠内侧的位置设置于预定的深度范围。阱区可以是导电型与半导体基板的漂移区的导电型不同的杂质区域。绝缘膜可以在半导体基板的表面上，至少设置于外缘区域与阱区之间。绝缘膜可以具有锥形部。绝缘膜的锥形部的锥角可以为60度以下。电阻膜可以设置于绝缘膜上。电阻膜可以将外缘区域与阱区电连接。
半导体基板的表面上的绝缘膜的厚度可以为0.5μm以上。
锥形部的上端以及下端在与半导体基板的表面平行的方向，可以与有源部的阱区的外侧端部分隔一段距离，所述距离为阱区的外侧端部与外缘区域的内侧端部的间隔的四分之一以上。
锥形部的上端在与半导体基板的表面平行的方向，可以比有源部的阱区的外侧端部与外缘区域的内侧端部之间的中间位置接近于外缘区域。
此外，锥形部的下端在与半导体基板的表面平行的方向，可以比有源部的阱区的外侧端部与外缘区域的内侧端部之间的中间位置接近于外缘区域。
绝缘膜可以具有第一绝缘膜和第二绝缘膜。第一绝缘膜可以具有锥形部。第二绝缘膜可以位于第一绝缘膜与半导体基板的表面之间。
绝缘膜的内侧端部与阱区的外侧端部相比更向内侧方向延伸，并且绝缘膜的外侧端部与外缘区域的内侧端部相比更向外侧方向延伸。
应予说明，上述的发明内容并未列举出本发明的全部必要特征。此外，这些特征组的子组合也可另外成为发明。
附图说明
图1是表示第一实施方式的半导体装置100的概要的图。
图2的(a)是表示图1中的A-A’截面的图。图2的(b)是表示电阻膜40中的电位V以及电场E的概要的图。
图3的(a)-(c)是边缘终端部90中的绝缘膜30的放大图。
图4是表示半导体装置100中的锥角θ与耐压的关系的图。
图5是表示第二实施方式的A-A’截面的图。
图6是表示第三实施方式的A-A’截面的图。
符号说明
10…半导体基板，12…表面，14…背面，16…漂移区，18…集电区，20…阱区，22…外侧端部，24…弯曲区域，30…绝缘膜，32…第一绝缘膜，34…第二绝缘膜，36…锥形部，37…上端，38…下端，39…中点，40…电阻膜，50…外缘区域，52…外侧端部，54…内侧端部，60…表面电极，62…外侧端部，64…内侧端部，70…背面电极，80…有源部，90…边缘终端部，100…半导体装置。
具体实施方式
以下，通过发明的实施方式来说明本发明，但是以下的实施方式并非要限定权利要求所涉及的发明。此外，实施方式中说明的特征的全部组合并不一定是发明的解决方案所必须的。
图1是表示第一实施方式的半导体装置100的上表面的概要的图。本例的半导体装置100具备半导体基板10，半导体基板10包括有源部80和边缘终端部90。半导体基板10也可以称为半导体芯片。本例的半导体基板10是硅基板。
有源部80可以是在将半导体装置100控制为导通状态的情况下流通电流的区域。有源部80可以包含IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)和MOSFET(Metal Oxide Semiconductor Field Effect Transistor，金属氧化物半导体场效应晶体管)等晶体管以及FWD(Free Wheeling Diode，续流二极管)等二极管。
本例的有源部80具有IGBT。但是，有源部80也可以是MOSFET或FWD。此外，有源部80也可以是将IGBT与FWD一体形成而成的RC‐IGBT(Reverse Conducting‐IGBT，逆导型IGBT)。此外，有源部80既可以具有MOSFET和FWD，也可以具有IGBT、MOSFET和FWD。
边缘终端部90可以设置为俯视时包围矩形形状的有源部80的四周。边缘终端部90可以具有缓和半导体基板10的上表面附近的电场集中的功能。边缘终端部90可以具有保护环、场板、降低表面电场部、沟道阻挡部以及将这些部件组合而成的结构中的一个以上。
俯视时，本例的半导体基板10具有平行于X轴以及Y轴的四边。X轴与Y轴是相互正交的轴。应予说明，X轴方向以及Y轴方向也是与半导体基板10的表面平行的方向。此外，将与X轴以及Y轴正交的轴设为Z轴。X轴方向、Y轴方向以及Z轴方向形成所谓的右手系。
在本说明书中，有时将Z轴的正方向称为上，将Z轴的负方向称为下。此外，有时将Z轴的负方向称为半导体基板10的深度方向。上以及下不过是方便于确定基板、区域、层以及膜等的相对的位置关系的表达。例如，Z轴方向并不一定指重力方向或垂直于地面的方向。
图2的(a)是表示图1中的A-A’截面的图。A-A’截面是平行于穿过边缘终端部90的XZ平面的截面。半导体基板10在Z轴的正方向的端部具有表面(正面)12，在Z轴的负方向的端部具有背面14。本例的半导体基板10在第一导电型的半导体基板的表面侧至少形成有第二导电型的阱区20。具体地，半导体基板10具有在表面12露出的N型的漂移区16、P型的阱区20以及N型的外缘区域50、在背面14露出的N+型的集电区18。本例的阱区20是第二导电型区域的例子，是导电型与半导体基板10的漂移区16不同的杂质区域。本例的漂移区16以及阱区20分别从表面12设置到预定的深度。应予说明，漂移区16的深度位置与阱区20的深度位置可以不同。
应予说明，在本例中，第一导电型是N型，第二导电型是P型，但是在其他的例子中，第一导电型也可以是P型，第二导电型也可以是N型。N或P分别指电子或空穴为多数载流子的情况。关于在N或P的右侧记载的+或-，+指载流子浓度比没有记载该+的情况的载流子浓度高，-指载流子浓度比没有记载该-的情况的载流子浓度低。
本例的有源部80包含P型的杂质区域即阱区20。阱区20设置于表面12的预定的深度范围。阱区20与设置于边缘终端部90的外缘区域50相比设置于靠内侧的位置。在本例中，设阱区20的外侧端部22为有源部80与边缘终端部90的边界。
由于本例的有源部80具有IGBT，所以阱区20可以是IGBT的P型基区。但是，在其他的例子中，阱区20既可以是MOSFET的P型基区，也可以是FWD的P型体区。
在本说明书中，将从有源部80朝向边缘终端部90的方向称为外侧方向，将从边缘终端部90朝向有源部80的方向称为内侧方向。外侧方向以及内侧方向可以在X轴的负方向以及Y轴的正、负方向上也同样地进行规定。
本例的边缘终端部90包含作为沟道阻止区发挥功能的外缘区域50。外缘区域50可以具有停止耗尽层的扩展的功能，以使从阱区20向外侧方向扩展的耗尽层不会到达半导体基板10的外侧方向的端部。外缘区域50设置于半导体基板10的在XY平面中的矩形的外周。本例的外缘区域50在表面12的端部设置于预定的深度范围。外缘区域50可以设置于从表面12起数μm的深度范围。本例的外缘区域50是具有比漂移区16高的N型杂质浓度的杂质区域。应予说明，在其他的例子中，外缘区域50也可以是P+型的杂质区域。
外缘区域50的外侧端部52可以与半导体基板10的外侧端部一致。此外，将外缘区域50的内侧方向的端部设为内侧端部54。在本例中，从外缘区域50的外侧端部52到内侧端部54的距离为约20μm。在本例中，外缘区域50与阱区20可以分隔预定的距离。在本例中，外缘区域50的内侧端部54与阱区20的外侧端部22的距离为约200μm。
本例的半导体装置100还具备绝缘膜30、电阻膜40、表面电极60和背面电极70。绝缘膜30具有第一绝缘膜32和第二绝缘膜34。在本例中，第一绝缘膜32具有锥形部36。在本例中，锥形部36的锥角θ是将锥形部36的上端37与下端38连结的直线与半导体基板10的表面12所成的角度。第二绝缘膜34在第一绝缘膜32的锥形部36的正下方具有锥形部。第二绝缘膜34的锥形部的锥角可以反映于第一绝缘膜32的锥形部36的锥角θ。第二绝缘膜34设置于比第一绝缘膜32狭小的范围。第二绝缘膜34的内侧端部可以终止在第一绝缘膜32的锥形部36的正下方。本例的第二绝缘膜34位于第一绝缘膜32与半导体基板10的表面12之间。
绝缘膜30可以具有比电阻膜40高的电阻。换言之，第二绝缘膜34可以不成为阱区20与外缘区域50之间的导通路径。第一绝缘膜32以及第二绝缘膜34可以都是氧化硅膜。在本例中，第一绝缘膜32是二氧化硅(SiO2)膜、PSG膜、BSG膜或BPSG膜，第二绝缘膜34是二氧化硅膜。
绝缘膜30可以在表面12上至少连续设置于外缘区域50与阱区20之间。在本例中，第二绝缘膜34的内侧端部位于阱区20的外侧端部22的外侧，第一绝缘膜32的内侧端部与阱区20的外侧端部22相比更向内侧方向延伸。此外，在本例中，第一绝缘膜32以及第二绝缘膜34的外侧端部的X轴方向的位置相同(即，齐平)，并且与外缘区域50的内侧端部54相比更向外侧方向延伸。在本例中，由于绝缘膜30的内侧端部与阱区20的外侧端部22相比更向内侧方向延伸，并且绝缘膜30的外侧端部与外缘区域50的内侧端部54相比更向外侧方向延伸，所以能够通过绝缘膜30将阱区20与外缘区域50间的表面12切实地绝缘。
本例的绝缘膜30由于具有锥形部36，所以与以往的平坦的绝缘膜不同。由于具有锥形部36，绝缘膜30包括仅具有第一绝缘膜32的厚度的区域以及具有第一绝缘膜32和第二绝缘膜34的厚度的区域。
绝缘膜30的厚度的差异也可以在形成保护环时被利用。例如，以贯穿第一绝缘膜32的厚度，但不贯穿第一绝缘膜32和第二绝缘膜34的厚度的方式，调整用于形成保护环的离子类的注入能量。应予说明，在本例中，形成保护环并不是必须的要素。在不形成保护环的情况下，也有时在能够以与形成保护环的情况相同的制造工序形成绝缘膜30上有价值。例如，有时从维持半导体装置100的工作可靠性以及成品率的观点出发，期望无论有无保护环都不改变绝缘膜30的制造工序。
电阻膜40可以连续设置于绝缘膜30上。本例的电阻膜40与位于锥形部36的内侧的第一绝缘膜32的上部、第一绝缘膜32的锥形部36和位于锥形部36的外侧的第一绝缘膜32的上部分别直接接触。电阻膜40可以在锥形部36上充分地减薄到改变其延伸方向的程度，以反映锥形部36的锥角θ。电阻膜40可以具有与第一绝缘膜32大致同等的厚度。电阻膜40可以具有0.5μm以上且1.5μm以下的厚度。本例的电阻膜40具有0.8μm的厚度。
本例的电阻膜40的内侧端部的X轴方向的位置与第一绝缘膜32的内侧端部的X轴方向的位置相同。此外，本例的电阻膜40的外侧端部的X轴方向的位置与第一绝缘膜32以及第二绝缘膜34的外侧端部的X轴方向的位置相同。
电阻膜40可以是具有几MΩ的电阻的膜。应予说明，M是表示10的6次方的国际单位制(SI)的冠词。本例的电阻膜40是氮化硅膜。本例的氮化硅膜可以是非晶膜，也可以是单晶膜或多晶膜。应予说明，电阻膜40并不限定于氮化硅膜，也可以是由具有几MΩ的电阻的其他材料构成的电阻膜。
在有源部80设置表面电极60。有源部80的表面电极60至少直接接触于阱区20中在表面12露出的部分和电阻膜40。在本例中，有源部80的表面电极60的外侧端部62位于比阱区20的外侧端部22靠内侧方向的位置。
表面电极60还设置于边缘终端部90。边缘终端部90的表面电极60至少直接接触于外缘区域50中在表面12露出的部分和电阻膜40。在本例中，边缘终端部90的表面电极60的内侧端部64位于比外缘区域50的内侧端部54靠内侧方向的位置。
有源部80的表面电极60与边缘终端部90的表面电极60可以在电阻膜40上不连续。在本例中，在有源部80的表面电极60的外侧端部62与边缘终端部90的表面电极60的内侧端部64之间不存在表面电极60。因此，阱区20与外缘区域50介由有源部80的表面电极60、电阻膜40和边缘终端部90的表面电极60相互电连接。
有源部80的表面电极60可以视为从外侧端部62起在内侧方向是相同电位(例如，接地电位)。此外，边缘终端部90中的表面电极60可以视为从内侧端部64起到外侧端部52是相同电位(例如，与背面电极70相同的电位)。
有源部80的表面电极60与边缘终端部90的表面电极60可以以相同的工艺同时地形成。表面电极60可以是铝膜或铝-硅合金膜。在本例中，有源部80的表面电极60是发射极。
本例的背面电极70是被施加几百V～一千几百V的电压的集电极。边缘终端部90的表面电极60介由半导体基板10的外侧端部可具有与背面电极70相同的电位。由此，从有源部80的表面电极60的外侧端部62到边缘终端部90的表面电极60的内侧端部64形成电位梯度。
图2的(b)是表示电阻膜40中的电位V以及电场E的概要的图。横轴是X轴方向的长度[μm]，纵轴的左侧是电位V，纵轴的右侧是电场E。X轴方向的0点设为有源部80的表面电极60的外侧端部62。此外，X轴方向的右端设为边缘终端部90的表面电极60的内侧端部64。应予说明，在图2的(b)中，以X轴为横轴进行讨论，但是在以Y轴为横轴的情况下相同的讨论也成立。
剖视时，在电阻膜40的外形近似于线状的情况下，电阻膜40按单位长度可以具有固定的电阻值。因此，从有源部80到边缘终端部90，电阻膜40的电位可以以固定的倾度变化。但是，锥形部36上的电阻膜40除了沿X轴方向延伸之外，还沿Z轴方向延伸。因此，电位V在X轴方向上的变化(倾度)在锥形部36处与除锥形部36以外的区域相比变大。
这样，由于电阻膜40的电位V在X轴方向的倾度在锥形部36处发生变化，所以电阻膜40的电场E在锥形部36处不连续。在本例中，电阻膜40的电场E在锥形部36处具有向上凸的矩形波形状。因此，在锥形部36正下方的半导体基板10的表面12附近，电场E变得比除锥形部36以外的正下方的电场强。这样，在锥形部36正下方，电场可局部地集中。
硅基板虽然还取决于所掺杂的杂质密度，但具有0.25[MV/cm]到0.3[MV/cm]左右的击穿电场强度。电阻膜40由于在边缘终端部90中具有使耗尽层扩展的功能所以有用，但是若电阻膜40的电场E超过半导体基板10的击穿电场强度，则在表面12附近可发生雪崩击穿。
若发生雪崩击穿，则半导体装置100无法维持最初的耐压。这样，因锥形部36的形状，半导体基板10的耐压可降低。锥形部36的锥角越大，锥形部36正下方的电场E越强。本申请的发明人发现，在绝缘膜30的锥形部36的锥角为60度以下的情况下，与大于60度的情况相比，能够抑制耐压降低，详情后述。
应予说明，在一例中，锥形部36的上端37以及下端38在平行于半导体基板10的表面12的方向，与有源部80的阱区20的外侧端部22分隔如下距离，即该距离为阱区20的外侧端部22与外缘区域50的内侧端部54的间隔的四分之一以上。由此，能够有效地抑制耐压的降低，详情后述。
图3的(a)-(c)是边缘终端部90中的绝缘膜30的放大图。应予说明，以易于观察图面为目的，省略了对绝缘膜30标注的阴影线。图3的(a)是锥形部36具有直线状的倾度的情况。例如，在通过干法蚀刻形成锥形部36的情况下，锥形部36倾向于具有直线状的倾度。在图3的(a)中，将连结锥形部36的上端37与下端38的直线与半导体基板10的表面12所成的角度设为锥形部36的锥角θ。
应予说明，在边缘终端部90，有时表面12可以视为平坦的面。在表面12平坦的情况下，在表面12上直接接触而设置的第二绝缘膜34的上表面也可视为平坦的面。应予说明，在本例中，考虑后述的第一绝缘膜32的厚度，所谓表面12平坦，设为边缘终端部90中的最大高度与最小高度之差为0.2μm以下。在此情况下，锥形部36的锥角θ也可以定义为连结上端37与下端38的直线与第二绝缘膜34的上表面所成的角度。
第一绝缘膜32的厚度h根本上是半导体基板10的表面12上或第二绝缘膜34上的第一绝缘膜32的厚度，但是也可以通过下端38的高度位置与上端37的高度位置之差来规定。第一绝缘膜32的厚度h可以为0.5μm以上。例如，第一绝缘膜32的厚度h是0.8μm以上且1.0μm以下的预定的厚度。在第一实施方式中，第一绝缘膜32以及第二绝缘膜34的厚度分别为1.0μm。
在第一绝缘膜32具有0.5μm以上的厚度h的情况下，在锥角θ的控制与锥形部36正下方的电场强度的抑制之间可以产生相关性。例如，如果厚度h为0.5μm以上，则通过减小锥角θ，能够降低锥形部36正下方的电场强度。在第一实施方式中，由于第一绝缘膜32的厚度h为0.5μm以上，所以通过使锥角θ为60度以下，能够有效地抑制锥形部36正下方的电场强度。
应予说明，如果厚度h为0.5μm以上，则无论厚度h为0.5μm还是1μm，在锥角θ的控制与锥形部36正下方的电场强度的抑制之间都产生同样的相关性。与之相反，在第一绝缘膜32的厚度h小于0.5μm的情况下，无论使锥角θ为60度以下还是为60度以上，都在与电场强度的抑制之间基本不产生相关性。
图3的(b)是锥形部36为平滑的曲面状的情况。即，是下述情况：锥形部36的下部平滑地连接于半导体基板10的表面12，锥形部36的上部平滑地连接于第二绝缘膜34的上部的情况。例如，在通过湿法蚀刻形成锥形部36的情况下，锥形部36有成为平滑的曲面状的倾向。
在图3的(b)中，也可以将连结锥形部36的上端37与下端38的直线与半导体基板10的表面12所成的角度设为锥形部36的锥角θ。此外，如上所述，在第二绝缘膜34的上表面平坦的情况下，锥形部36的锥角θ也可以定义为连结上端37与下端38的直线与第二绝缘膜34的上表面所成的角度。
图3的(c)与图3的(b)同样，是锥形部36为平滑的曲面状的情况。但是，图3的(c)是上端37位于比图3的(b)靠外侧方向的位置且锥形部36的表面比图3的(b)平坦的例子。
在图3的(c)的例子中，也可以将锥形部36在上端37的高度位置与下端38的高度位置的中点39(即，h/2的高度位置)处的切线与半导体基板10的表面12所成的角度设为锥形部36的锥角θ。应予说明，如上所述，在第二绝缘膜34的上表面平坦的情况下，锥形部36的锥角θ也可以定义为锥形部36在中点39处的切线与第二绝缘膜34的上表面所成的角度。
应予说明，图3的(a)-(c)并不意味着锥角θ可以任意地规定。图3的(a)-(c)是例示存在多种恰当地评价锥形部36的倾斜度的方法的图。
图4是表示半导体装置100中的锥角θ与耐压的关系的图。横轴是锥形部36的锥角θ的角度[度]。纵轴是对半导体装置100施加反向偏压的情况下的耐压[V]。在图4中，是对与多个不同的锥角θ分别对应的耐压进行测定而得到的实验结果。
在锥角θ大于60度的情况下，有耐压小于550[V]的半导体装置100。这样，在锥角θ大于60度的情况下，耐压降低显著。因此，优选锥角θ设为60度以下。
此外，在锥角θ大于50度的情况下，有耐压小于900[V]的半导体装置100。为了防止这样的耐压的降低，锥角θ可以设为50度以下。
在锥角θ为48度以下的情况下，未观察到耐压显著地降低。即，在锥角θ为48度以下的情况下，能够维持额定耐压。在锥角θ为48度以下的情况下，可认为防止耐压降低的效果特别高。因此，锥角θ可以设为48度以下，可以设为45度以下，也可以设为40度以下。
图5是表示第二实施方式的A-A’截面的图。本例的锥形部36具有与第一实施方式相同的形状，但是位于比第一实施方式靠外侧方向的位置。更具体地，锥形部36的上端37在与X轴方向平行的方向，比中间位置LM接近于外缘区域50。此外，锥形部36的下端38比中间位置LM接近于阱区20。该点与第一实施方式不同。其他方面与第一实施方式相同。应予说明，所谓中间位置LM，是阱区20的外侧端部22与外缘区域50的内侧端部54之间的中间的位置。
阱区20的外侧端部22的附近的弯曲区域24有时成为从背面14向表面12流通的电流集中的区域。例如，在阱区20的弯曲区域24为FWD的P型体区的外侧方向的端部附近的区域的情况下，若对半导体装置100施加反向偏压，则电流在弯曲区域24集中。在本例中，通过使锥形部36与阱区20分离，能够使电流集中的弯曲区域24与电场强的锥形部36在与X轴方向平行的方向分离。由此，相比于锥形部36的上端37以及下端38以阱区20的外侧端部22与外缘区域50的内侧端部54的间隔的四分之一的距离与外侧端部22分隔的情况，能够更有效地抑制耐压的降低。
图6是表示第三实施方式的A-A’截面的图。在本例中，除了锥形部36的上端37之外，锥形部36的下端38也在与X轴方向平行的方向，比中间位置LM接近于外缘区域50。由此，与第一实施方式以及第二实施方式相比，由于能够进一步使锥形部36与阱区20分离，所以能够进一步有效地抑制耐压的降低。
以上，利用实施方式说明了本发明，但本发明的技术范围不限定于上述实施方式中记载的范围。本领域技术人员可以明了对上述实施方式可以进行多种变更或改进。根据权利要求书的记载可以明了，进行了该各种变更或改进所得的方式也可以包括在本发明的技术范围内。
应该注意的是，只要权利要求书、说明书和附图中所示的装置、***、程序和方法中的工作、顺序、步骤和阶段等各处理的执行顺序并未特别明确为“在…之前”、“先于…”等，另外，只要不在后续处理中使用之前处理的结果，就可以按任意顺序实现。即使为了方便起见，对权利要求书、说明书和附图中的工作流程使用“首先”、“接下来”等进行了说明，也不表示一定要按照该顺序实施。

Claims (8)

1.一种半导体装置，具备半导体基板，其特征在于，
所述半导体基板具有：
边缘终端部，其包含外缘区域，所述外缘区域在所述半导体基板的表面的端部设置于预定的深度范围且是杂质区域；以及
有源部，其包含阱区，所述阱区在所述半导体基板的所述表面的比所述外缘区域靠内侧的位置设置于预定的深度范围且是导电型与所述半导体基板的漂移区的导电型不同的杂质区域，
所述半导体装置还具备：
绝缘膜，其在所述半导体基板的所述表面上，至少设置于所述外缘区域与所述阱区之间，且具有锥形部；以及
电阻膜，其设置于所述绝缘膜上，将所述外缘区域与所述阱区电连接，
所述绝缘膜的所述锥形部的锥角为60度以下。
2.根据权利要求1所述的半导体装置，其特征在于，
所述半导体基板的所述表面上的所述绝缘膜的厚度为0.5μm以上。
3.根据权利要求1所述的半导体装置，其特征在于，
所述锥形部的上端以及下端在与所述半导体基板的所述表面平行的方向，与所述有源部的所述阱区的外侧端部分隔一段距离，所述距离为所述阱区的外侧端部与所述外缘区域的内侧端部的间隔的四分之一以上。
4.根据权利要求2所述的半导体装置，其特征在于，
所述锥形部的上端以及下端在与所述半导体基板的所述表面平行的方向，与所述有源部的所述阱区的外侧端部分隔一段距离，所述距离为所述阱区的外侧端部与所述外缘区域的内侧端部的间隔的四分之一以上。
5.根据权利要求1-4中任一项所述的半导体装置，其特征在于，
所述锥形部的上端在与所述半导体基板的所述表面平行的方向，比所述有源部的所述阱区的外侧端部与所述外缘区域的内侧端部之间的中间位置接近于所述外缘区域。
6.根据权利要求1-4中任一项所述的半导体装置，其特征在于，
所述锥形部的下端在与所述半导体基板的所述表面平行的方向，比所述有源部的所述阱区的外侧端部与所述外缘区域的内侧端部之间的中间位置接近于所述外缘区域。
7.根据权利要求1-4中任一项所述的半导体装置，其特征在于，
所述绝缘膜包含具有所述锥形部的第一绝缘膜和位于所述第一绝缘膜与所述半导体基板的所述表面之间的第二绝缘膜。
8.根据权利要求1-4中任一项所述的半导体装置，其特征在于，
所述绝缘膜的内侧端部与所述阱区的外侧端部相比更向内侧方向延伸，并且所述绝缘膜的外侧端部与所述外缘区域的内侧端部相比更向外侧方向延伸。
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