CN108281395A - 一种贴片型irm高屏蔽结构及其制作工艺 - Google Patents

一种贴片型irm高屏蔽结构及其制作工艺 Download PDF

Info

Publication number
CN108281395A
CN108281395A CN201810158883.7A CN201810158883A CN108281395A CN 108281395 A CN108281395 A CN 108281395A CN 201810158883 A CN201810158883 A CN 201810158883A CN 108281395 A CN108281395 A CN 108281395A
Authority
CN
China
Prior art keywords
pcb board
chips
chip
patch
copper post
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810158883.7A
Other languages
English (en)
Inventor
窦鑫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Thunder Photoelectric Technology Co Ltd
Original Assignee
Suzhou Thunder Photoelectric Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Thunder Photoelectric Technology Co Ltd filed Critical Suzhou Thunder Photoelectric Technology Co Ltd
Priority to CN201810158883.7A priority Critical patent/CN108281395A/zh
Publication of CN108281395A publication Critical patent/CN108281395A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/296Organo-silicon compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/165Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本发明属于红外信号接收技术领域,具体涉及一种贴片型IRM高屏蔽结构,包括PCB板,PCB板上贯穿有若干个导通孔,各导通孔中均塞有铜柱;PCB板的正面上设有PD晶片,且反面上设有IC芯片;各铜柱的一端均通过焊线连接至PD晶片上,各铜柱的另一端均通过焊线连接至IC芯片上;PCB板的两面上均固化有封装胶,PD晶片和IC芯片内置于PCB板两侧的封装胶内。本发明的有益效果是:在阻隔光干扰的同时,节省了内屏蔽罩或外屏蔽罩的物料及工艺成本;制作工艺简单化,相对于插件类产品和贴片类支架式产品减少了数道工序,减少了具有废水废气污染的高成本的电镀锡制程;相对于贴片类PCB产品减少了外屏蔽罩的组装难度和人工费用。

Description

一种贴片型IRM高屏蔽结构及其制作工艺
技术领域
本发明属于红外信号接收技术领域,具体涉及一种贴片型IRM高屏蔽结构及其制作工艺。
背景技术
IRM为红外接收模组,其内部有一个感光PD晶片,串联一个处理放大IC芯片,能接收940nm的红外光,并对用红外光做载波的信号进行处理、整波、解码、放大,并将光信号转化成电参数型号,因处理放大IC芯片也会受到外界自然光中的其他光线干扰,所以将封装胶体用处黑色环氧胶,黑色色剂成分能过滤掉可见光,及一部分红外光,最多860nm以下的红外光,但是因过滤红光光线通过率在80%左右,所以还是有阳光中的高波长光谱,或节能灯,白炽灯中的高波长光谱能进入IRM模组内,干扰IC芯片,影响IRM的解码,放大,处理电信号能力,存在杂波现象,或遥控接收距离大幅度降低。
目前市场上主要生产的IRM主要分为两个大类:插件类和贴片类。插件类IRM采用铁支架折弯内屏蔽罩封装结构,如中国发明公开号CN102290411A所示的一种抗光干扰红外线接收模组。贴片类又分支架式和PCB两类,贴片类支架式铜或铁支架也是折弯内屏蔽罩结构;而贴片类PCB结构的IRM,是采用外置铁壳做屏蔽罩设计,上述三种封装都存在生产工艺复杂,良率低,成本高的问题。
首先,具有支架折弯结构的IRM因设备限制,产品的密度一般为20PCS连体,最多40PCS左右连体,生产效率极低。
单条生产线UPH仅5~10K/h,且支架生产工艺多,包括固晶、焊线、弯屏蔽罩、封胶、除胶、激光打码、打水刀(或喷砂)、电镀、切中筋、切底筋、测试、全切角和包装,需要13到工序,尤其是电镀锡属于重污染行业,目前环保要求越来越高,电镀厂逐渐减少,后期成本会增加,而且一道工序出错都会影响整体良率。
贴片类支架式封装跟上述封装生产工艺相同,仅仅在密度上提高了一些,但最多密度也就在80~120pcs之间,所提升的效率也是非常少的,但是支架的成本上浮2~3倍,总体成本比插件类IRM还要高。
贴片类PCB封装在成品封装上工艺减少了固晶、焊线、封胶、切割、测试、装铁壳(有人工及自动,但是效率都很低)和编带,共7道工序,但是装外置铁壳需要额外成本,切需要烙铁焊接铁壳与IRM产品,防止脱落,同时焊接中的高温(380℃左右)接触时间需要控制在10s以内,进一步提高的生产难度。
发明内容
本发明的目的是克服现有技术存在的缺陷,提供一种在阻隔光干扰的同时,节省了内屏蔽罩或外屏蔽罩的物料及工艺成本;制作工艺简单化,相对于插件类产品和贴片类支架式产品减少了数道工序,减少了具有废水废气污染的高成本的电镀锡制程;相对于贴片类PCB产品减少了外屏蔽罩的组装难度和人工费用的贴片型IRM高屏蔽结构及其制作工艺。
本发明解决其技术问题所采用的技术方案是:一种贴片型IRM高屏蔽结构,其包括PCB板,PCB板上贯穿有若干个导通孔,各导通孔中均塞有铜柱,PCB板两面上的电路通过铜柱导通;PCB板的正面上设有PD晶片,且反面上设有IC芯片;各铜柱的一端均通过焊线连接至PD晶片上,各铜柱的另一端均通过焊线连接至IC芯片上;PCB板的两面上均固化有封装胶,PD晶片和IC芯片一一对应地内置于PCB板两侧的封装胶内。
本发明将IC芯片放置于PD晶片的背面,在减少光干扰的同时取消内屏蔽罩和外部铁壳,降低了原物料成本,且大幅度提升生产效率,PCB板的拼板密度可达1500~2000pcs连体,在降低封装胶体用量的前提下提升了生产效率,降低成本。
本发明通过PCB板的正反两面固晶焊线,压模封胶,将PD晶片和IC芯片分开,同时因PCB板的正反两面有双层铜箔金属层,在阻隔光干扰的同时,节省了内屏蔽罩或外屏蔽罩的物料及工艺成本;结构简单,制作方便。
具体地,PD晶片和IC芯片均通过固晶胶粘接于PCB板上,方便焊线连接各个元器件。
作为优选,封装胶为环氧树脂或硅树脂,固化成型效果好。
作为优选,PCB板为两侧面上均复合铜板的BT树脂板。本发明的特殊工艺在于PCB板的特殊设计,即采用将PCB板钻孔后塞铜柱,从而导通正背面的线路层,同时选用0.4mm的BT树脂板,整体厚度0.5mm,最终封装成品的整体厚度在2.0~3.0mm,远低于行业4.5~6.5mm厚度水平,使产品更具轻薄化,加大了应用范围。
生产中,由于PCB板的基板采用0.4mm厚度的BT树脂板,电镀后整体厚度达0.5mm左右,使得PCB板的硬度非常高,因此,可以在固晶焊线等制程中采用固定压住PCB板的两边,使中间部分悬空,从而可以进行正反两边固晶焊线,生产方便,提高了效率。
此外,本发明的贴片型IRM高屏蔽结构的制作工艺,其包括如下步骤:
a、准备原材料:在PCB板上钻若干个导通孔,各导通孔中均塞入铜柱,且铜柱将PCB板上下两面的电路导通;
b、固晶:将PD晶片通过固晶胶粘接在PCB板的正面;
c、烘烤:通过烘烤将PD晶片固定在PCB板上;
d、再固晶:将IC芯片通过固晶胶粘接在PCB板的反面,并再次烘烤,将IC芯片固定在PCB板上;
d、焊接:在PCB板的正面上,铜柱的一端均通过焊线连接至PD晶片上;在PCB板的反面上,铜柱的另一端均通过焊线连接至IC芯片上;
e、压模:通过模具将装胶压模成型在PCB板的两侧;
f、烘烤:将封装胶烘烤固化;
g、切割:将烘烤固化后的切割成设计尺寸。
本发明的贴片型IRM高屏蔽结构的制作工艺简单化,相对于插件类产品和贴片类支架式产品减少了数道工序,尤其是高成本的电镀锡制程,减少了废水废气污染;相对于贴片类PCB产品减少了外屏蔽罩的组装难度和人工费用。
本发明的一种贴片型IRM高屏蔽结构及其制作工艺的有益效果是:
1.本发明通过PCB板的正反两面固晶焊线,压模封胶,将PD晶片和IC芯片分开,同时因PCB板的正反两面有双层铜箔金属层,在阻隔光干扰的同时,节省了内屏蔽罩或外屏蔽罩的物料及工艺成本;结构简单,制作方便;
2.本发明的贴片型IRM高屏蔽结构的制作工艺简单化,相对于插件类产品和贴片类支架式产品减少了数道工序,减少了具有废水废气污染的高成本的电镀锡制程;相对于贴片类PCB产品减少了外屏蔽罩的组装难度和人工费用。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明。
图1是本发明的一种贴片型IRM高屏蔽结构的内部结构图。
其中:1.PCB板;2.铜柱;3.PD晶片;4.IC芯片;5.焊线;6.封装胶。
具体实施方式
现在结合附图对本发明作进一步详细的说明。这些附图均为简化的示意图,仅以示意方式说明本发明的基本结构,因此其仅显示与本发明有关的构成。
如图1所示的本发明的一种贴片型IRM高屏蔽结构的具体实施例,其包括PCB板1,PCB板1上贯穿有若干个导通孔,各导通孔中均塞有铜柱2,PCB板1两面上的电路通过铜柱2导通;PCB板1的正面上设有PD晶片3,且反面上设有IC芯片4;各铜柱2的一端均通过焊线5连接至PD晶片3上,各铜柱2的另一端均通过焊线5连接至IC芯片4上;PCB板1的两面上均固化有封装胶6,PD晶片3和IC芯片4一一对应地内置于PCB板1两侧的封装胶6内。
本实施例将IC芯片4放置于PD晶片3的背面,在减少光干扰的同时取消内屏蔽罩和外部铁壳,降低了原物料成本,且大幅度提升生产效率,PCB板1的拼板密度可达1500~2000pcs连体,在降低封装胶体用量的前提下提升了生产效率,降低成本。
本实施例通过PCB板1的正反两面固晶焊线,压模封胶,将PD晶片3和IC芯片4分开,同时因PCB板1的正反两面有双层铜箔金属层,在阻隔光干扰的同时,节省了内屏蔽罩或外屏蔽罩的物料及工艺成本;结构简单,制作方便。
具体地,PD晶片3和IC芯片4均通过固晶胶粘接于PCB板1上,方便焊线5连接各个元器件。
作为优选,封装胶6为环氧树脂或硅树脂,固化成型效果好。
作为优选,PCB板1为两侧面上均复合铜板的BT树脂板。本实施例的特殊工艺在于PCB板1的特殊设计,即采用将PCB板1钻孔后塞铜柱2,从而导通正背面的线路层,同时选用0.4mm的BT树脂板,整体厚度0.5mm,最终封装成品的整体厚度在2.0~3.0mm,远低于行业4.5~6.5mm厚度水平,使产品更具轻薄化,加大了应用范围。
生产中,由于PCB板1的基板采用0.4mm厚度的BT树脂板,电镀后整体厚度达0.5mm左右,使得PCB板1的硬度非常高,因此,可以在固晶焊线等制程中采用固定压住PCB板1的两边,使中间部分悬空,从而可以进行正反两边固晶焊线,生产方便,提高了效率。
此外,本实施例的贴片型IRM高屏蔽结构的制作工艺,其包括如下步骤:
a、准备原材料:在PCB板1上钻若干个导通孔,各导通孔中均塞入铜柱2,且铜柱2将PCB板1上下两面的电路导通;
b、固晶:将PD晶片3通过固晶胶粘接在PCB板1的正面;
c、烘烤:通过烘烤将PD晶片3固定在PCB板1上;
d、再固晶:将IC芯片4通过固晶胶粘接在PCB板1的反面,并再次烘烤,将IC芯片4固定在PCB板1上;
d、焊接:在PCB板1的正面上,铜柱2的一端均通过焊线5连接至PD晶片3上;在PCB板1的反面上,铜柱2的另一端均通过焊线5连接至IC芯片4上;
e、压模:通过模具将装胶压模成型在PCB板1的两侧;
f、烘烤:将封装胶6烘烤固化;
g、切割:将烘烤固化后的切割成设计尺寸。
本实施例的贴片型IRM高屏蔽结构的制作工艺简单化,相对于插件类产品和贴片类支架式产品减少了数道工序,减少了废水废气污染的高成本的电镀锡制程;相对于贴片类PCB产品减少了外屏蔽罩的组装难度和人工费用。
应当理解,以上所描述的具体实施例仅用于解释本发明,并不用于限定本发明。由本发明的精神所引伸出的显而易见的变化或变动仍处于本发明的保护范围之中。

Claims (5)

1.一种贴片型IRM高屏蔽结构,其特征在于:包括PCB板(1),所述PCB板(1)上贯穿有若干个导通孔,各导通孔中均塞有铜柱(2),所述PCB板(1)两面上的电路通过铜柱(2)导通;所述PCB板(1)的正面上设有PD晶片(3),且反面上设有IC芯片(4);各铜柱(2)的一端均通过焊线(5)连接至PD晶片(3)上,各铜柱(2)的另一端均通过焊线(5)连接至IC芯片(4)上;所述PCB板(1)的两面上均固化有封装胶(6),所述PD晶片(3)和IC芯片(4)一一对应地内置于PCB板(1)两侧的封装胶(6)内。
2.根据权利要求1所述的一种贴片型IRM高屏蔽结构,其特征在于:所述PD晶片(3)和IC芯片(4)均通过固晶胶粘接于PCB板(1)上。
3.根据权利要求1所述的一种贴片型IRM高屏蔽结构,其特征在于:所述封装胶(6)为环氧树脂或硅树脂。
4.根据权利要求1或2所述的一种贴片型IRM高屏蔽结构,其特征在于:所述PCB板(1)为两侧面上均复合铜板的BT树脂板。
5.一种根据权利要求1-3中任一项所述的贴片型IRM高屏蔽结构的制作工艺,其特征在于,包括如下步骤:
a、准备原材料:在PCB板(1)上钻若干个导通孔,各导通孔中均塞入铜柱(2),且铜柱(2)将PCB板(1)上下两面的电路导通;
b、固晶:将PD晶片(3)通过固晶胶粘接在PCB板(1)的正面;
c、烘烤:通过烘烤将PD晶片(3)固定在PCB板(1)上;
d、再固晶:将IC芯片(4)通过固晶胶粘接在PCB板(1)的反面,并再次烘烤,将IC芯片(4)固定在PCB板(1)上;
d、焊接:在PCB板(1)的正面上,铜柱(2)的一端均通过焊线(5)连接至PD晶片(3)上;在PCB板(1)的反面上,铜柱(2)的另一端均通过焊线(5)连接至IC芯片(4)上;
e、压模:通过模具将装胶压模成型在PCB板(1)的两侧;
f、烘烤:将封装胶(6)烘烤固化;
g、切割:将烘烤固化后的切割成设计尺寸。
CN201810158883.7A 2018-02-26 2018-02-26 一种贴片型irm高屏蔽结构及其制作工艺 Pending CN108281395A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810158883.7A CN108281395A (zh) 2018-02-26 2018-02-26 一种贴片型irm高屏蔽结构及其制作工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810158883.7A CN108281395A (zh) 2018-02-26 2018-02-26 一种贴片型irm高屏蔽结构及其制作工艺

Publications (1)

Publication Number Publication Date
CN108281395A true CN108281395A (zh) 2018-07-13

Family

ID=62808580

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810158883.7A Pending CN108281395A (zh) 2018-02-26 2018-02-26 一种贴片型irm高屏蔽结构及其制作工艺

Country Status (1)

Country Link
CN (1) CN108281395A (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110849482A (zh) * 2019-11-20 2020-02-28 常熟市华通电子有限公司 一种具有引脚插件结构的传感器贴片封装工艺
CN111653557A (zh) * 2020-06-11 2020-09-11 广西永裕半导体科技有限公司 一种贴片型红外接收传感器
CN114340200A (zh) * 2021-12-30 2022-04-12 广东长兴半导体科技有限公司 一种废存储ic重复利用方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10233471A (ja) * 1997-02-19 1998-09-02 Citizen Electron Co Ltd 赤外線データ通信モジュール及びその製造方法
JP2001168122A (ja) * 1999-12-03 2001-06-22 Matsushita Electronics Industry Corp 電子部品実装モジュールの製造方法および電子部品実装モジュール
JP2003304004A (ja) * 2002-04-11 2003-10-24 Citizen Electronics Co Ltd 光伝送チップ及び取付構造
CN207852652U (zh) * 2018-02-26 2018-09-11 苏州雷霆光电科技有限公司 一种贴片型irm高屏蔽结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10233471A (ja) * 1997-02-19 1998-09-02 Citizen Electron Co Ltd 赤外線データ通信モジュール及びその製造方法
JP2001168122A (ja) * 1999-12-03 2001-06-22 Matsushita Electronics Industry Corp 電子部品実装モジュールの製造方法および電子部品実装モジュール
JP2003304004A (ja) * 2002-04-11 2003-10-24 Citizen Electronics Co Ltd 光伝送チップ及び取付構造
CN207852652U (zh) * 2018-02-26 2018-09-11 苏州雷霆光电科技有限公司 一种贴片型irm高屏蔽结构

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110849482A (zh) * 2019-11-20 2020-02-28 常熟市华通电子有限公司 一种具有引脚插件结构的传感器贴片封装工艺
CN110849482B (zh) * 2019-11-20 2021-07-09 常熟市华通电子有限公司 一种具有引脚插件结构的传感器贴片封装工艺
CN111653557A (zh) * 2020-06-11 2020-09-11 广西永裕半导体科技有限公司 一种贴片型红外接收传感器
CN114340200A (zh) * 2021-12-30 2022-04-12 广东长兴半导体科技有限公司 一种废存储ic重复利用方法

Similar Documents

Publication Publication Date Title
CN108281395A (zh) 一种贴片型irm高屏蔽结构及其制作工艺
CN101562191B (zh) 带腔体的光电封装件及其生产方法
CN102916112A (zh) 一种大功率led器件及其制造方法
CN211654858U (zh) 一种晶片封装用的围坝陶瓷基板和晶片封装结构
CN108461459A (zh) 一种负极对接双向整流二极管及其制造工艺
CN102646646A (zh) 具有非对称凸柱/基座/凸柱散热座的半导体芯片组体
CN103682030B (zh) Led、led装置及led制作工艺
CN100530636C (zh) 三维多芯片封装模块和制作方法
CN207852652U (zh) 一种贴片型irm高屏蔽结构
CN102231372B (zh) 多圈排列无载体ic芯片封装件及其生产方法
CN205670539U (zh) 一种有机基板高密度集成的三维微波电路结构
CN102231376B (zh) 多圈排列无载体双ic芯片封装件及其生产方法
CN212277197U (zh) 一种射频前端器件的阻焊结构
CN112259667A (zh) 一种led器件及其封装方法
CN106356437B (zh) 一种白光led封装器件及其制备方法
CN108417555A (zh) 一种防电磁干扰的射频模块结构及实现方法
CN205039178U (zh) 一种芯片级led光源模组
CN102800664B (zh) 一种用于促进植物生长的led单灯及其生产工艺
CN101593746B (zh) 一种芯片封装结构
CN209298175U (zh) 一种cob光源器件
CN102290504A (zh) 基于高导热基板倒装焊技术的cob封装led模块和生产方法
CN112259664A (zh) 一种集成ir光源器件及其封装方法
CN111785822A (zh) 一种led倒装芯片封装器件及其封装工艺
CN206022425U (zh) 高光效发光二极管倒装芯片封装结构
CN201378591Y (zh) 表贴型金属墙陶瓷基板外壳

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination