CN108197063B - Fpga的spi接口主动串行配置方法及装置 - Google Patents
Fpga的spi接口主动串行配置方法及装置 Download PDFInfo
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- CN108197063B CN108197063B CN201711469458.1A CN201711469458A CN108197063B CN 108197063 B CN108197063 B CN 108197063B CN 201711469458 A CN201711469458 A CN 201711469458A CN 108197063 B CN108197063 B CN 108197063B
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 230000002093 peripheral effect Effects 0.000 title description 6
- 238000007689 inspection Methods 0.000 claims description 11
- 230000000977 initiatory effect Effects 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000002618 waking effect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 1
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- 230000006870 function Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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CN201711469458.1A CN108197063B (zh) | 2017-12-29 | 2017-12-29 | Fpga的spi接口主动串行配置方法及装置 |
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CN201711469458.1A CN108197063B (zh) | 2017-12-29 | 2017-12-29 | Fpga的spi接口主动串行配置方法及装置 |
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CN108197063A CN108197063A (zh) | 2018-06-22 |
CN108197063B true CN108197063B (zh) | 2021-01-22 |
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Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111324191B (zh) * | 2020-02-14 | 2022-05-31 | 深圳市紫光同创电子有限公司 | 一种sram模块的电源管理***及电源管理方法、fpga芯片 |
CN116610631B (zh) * | 2023-07-21 | 2023-09-26 | 西安智多晶微电子有限公司 | 支持多片SPI Flash访问的FPGA启动配置方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1928824A (zh) * | 2006-09-20 | 2007-03-14 | 华为技术有限公司 | 一种加载fpga目标程序的方法及*** |
US7397274B1 (en) * | 2005-04-07 | 2008-07-08 | Lattice Semiconductor Corporation | In-system programming of a non-compliant device using multiple interfaces of a PLD |
CN102087606A (zh) * | 2011-02-16 | 2011-06-08 | 电子科技大学 | 一种fpga配置文件更新装置 |
CN102609286A (zh) * | 2012-02-10 | 2012-07-25 | 株洲南车时代电气股份有限公司 | 一种基于处理器控制的fpga配置程序远程更新***及其方法 |
CN103885921A (zh) * | 2014-04-22 | 2014-06-25 | 国家电网公司 | Flash存储器、fpga芯片以及fpga芯片的配置方法 |
CN105446783A (zh) * | 2015-12-25 | 2016-03-30 | 浙江大学 | 一种皮卫星dsp程序快速加载方法 |
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2017
- 2017-12-29 CN CN201711469458.1A patent/CN108197063B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7397274B1 (en) * | 2005-04-07 | 2008-07-08 | Lattice Semiconductor Corporation | In-system programming of a non-compliant device using multiple interfaces of a PLD |
CN1928824A (zh) * | 2006-09-20 | 2007-03-14 | 华为技术有限公司 | 一种加载fpga目标程序的方法及*** |
CN102087606A (zh) * | 2011-02-16 | 2011-06-08 | 电子科技大学 | 一种fpga配置文件更新装置 |
CN102609286A (zh) * | 2012-02-10 | 2012-07-25 | 株洲南车时代电气股份有限公司 | 一种基于处理器控制的fpga配置程序远程更新***及其方法 |
CN103885921A (zh) * | 2014-04-22 | 2014-06-25 | 国家电网公司 | Flash存储器、fpga芯片以及fpga芯片的配置方法 |
CN105446783A (zh) * | 2015-12-25 | 2016-03-30 | 浙江大学 | 一种皮卫星dsp程序快速加载方法 |
Non-Patent Citations (1)
Title |
---|
"基于SPI FLASH的FPGA多重配置";李平 等;《现代电子技术》;20131115;第36卷(第22期);第1-2节 * |
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CN108197063A (zh) | 2018-06-22 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Active serial configuration method and device of SPI interface of FPGA Effective date of registration: 20220329 Granted publication date: 20210122 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2022610000115 |
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Date of cancellation: 20230328 Granted publication date: 20210122 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2022610000115 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Active Serial Configuration Method and Device for SPI Interface of FPGA Effective date of registration: 20230331 Granted publication date: 20210122 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2023610000233 |
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PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20210122 Pledgee: Pudong Development Bank of Shanghai Limited by Share Ltd. Xi'an branch Pledgor: XI'AN INTELLIGENCE SILICON TECHNOLOGY, Inc. Registration number: Y2023610000233 |