CN108155152B

CN108155152B - Conductor structure, array of capacitors structure and preparation method

Info

Publication number: CN108155152B
Application number: CN201711373297.6A
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2017-12-19
Filing date: 2017-12-19
Publication date: 2019-09-06
Anticipated expiration: 2037-12-19
Also published as: CN108155152A

Abstract

The present invention provides a kind of conductor structure based on polysilicon processing procedure, array of capacitors structure and preparation method, and conductor structure preparation includes: to provide a substrate, and cave structure is formed in substrate；In forming conductor filled structure in cave structure, the material source for forming conductor filled structure includes at least silicon source and ge source, nucleus of the germanium atom in ge source as silicon atom aggregation growth in silicon source, to increase the silicon grain size number in conductor filled structure.Through the above scheme; the invention proposes the modes of manufacture macromeritic polysilicon; introduce the nucleus element as silicon crystal grain aggregation growth; such as germanium; assemble silicon atom and then increases grain size number; influence of the crystal boundary trap to carrier can be reduced and then increase conductivity by increasing polysilicon crystal granularity; the present invention also passes through the setting of protective layer; prevent influence of the germanium in conductor filled structure to processing procedure; reach effective connection between conductor filled structure and other structures layer, further improves the electric property of conductor filled structure.

Description

Conductor structure, array of capacitors structure and preparation method

Technical field

The invention belongs to semiconductor devices and manufacturing fields, more particularly to a kind of conductor knot based on polysilicon processing procedure Structure, array of capacitors structure and preparation method.

Background technique

Dynamic RAM (Dynamic Random Access Memory, referred to as: DRAM) is commonly used in computer Semiconductor storage unit, be made of many duplicate storage units.Each storage unit generally includes capacitor and transistor； The grid of transistor is connected with wordline, drain be connected with bit line, source electrode is connected with capacitor；Voltage signal in wordline can be controlled Transistor processed opens or closes, and then reads the data information of storage in the capacitor by bit line, or will by bit line Data information is written in capacitor and is stored.Currently, DRAM is all made of stacking-type in the DRAM processing procedure of 20nm once Capacitor structure, capacitor (Capacitor) are the cylindrical shapes of vertical high-aspect-ratio to increase surface area.

Currently, polysilicon process is one of the technique for being widely used to semiconductor at present, wherein the crystal grain of polysilicon Degree (grain size) is one of the important parameter for influencing element function.In general, can with pressure by reaction temperature is changed Directly to adjust grain size number, however, these process conditions may also can the element to preceding processing procedure electrically have an impact, with Size is miniature and the reinforcing of performance, and the technique of polysilicon must be optimized to meet newest technique requirement.Meanwhile at present Manufacturing process in, DOPOS doped polycrystalline silicon is frequently used in the isostructural production of conducting wire, polysilicon crystal granularity (grain Size) if smaller, it is higher to represent grain boundary density (grain boundary density), will receive crystalline substance when carrier is in transmitting The influence of boundary's trap (grain boundary trap) and reduce conductivity.

Therefore, how a kind of conductor structure based on polysilicon processing procedure, array of capacitors structure and respective preparation are provided Method, to solve conductance caused by the limitation and polysilicon crystal undersized of improvement polysilicon crystal granularity in the prior art The problem of rate increases is necessary.

Summary of the invention

In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of leading based on polysilicon processing procedure Body structure, array of capacitors structure and respective preparation method improve polysilicon crystal granularity for solving in the prior art The problems such as conductivity caused by limitation and polysilicon crystal undersized increases.

In order to achieve the above objects and other related objects, the present invention provides a kind of conductor structure based on polysilicon processing procedure Preparation method includes the following steps:

1) substrate is provided, forms cave structure in Yu Suoshu substrate；And

2) conductor filled structure is formed in Yu Suoshu cave structure, and forms the material source of the conductor filled structure at least Include silicon source and ge source, wherein nucleus of the germanium atom as silicon atom aggregation growth in the silicon source in the ge source, to increase Silicon grain size number in the conductor filled structure formed greatly.

As a preferred solution of the present invention, in step 2), the conductor filled structure include filling perforation conductive layer and Gap storehouse, wherein the gap storehouse is made of the gap between the polysilicon of the filling perforation conductive layer, and the filling perforation conductive layer packet Cover the gap storehouse.

As a preferred solution of the present invention, the filling perforation conductive layer is filled in the cave structure and also extends and covers Cover the upper surface of the substrate around the cave structure, the gap position in storehouse is described in as defined by the cave structure In filling perforation conductive layer.

As a preferred solution of the present invention, the thickness that the filling perforation conductive layer is located at the upper surface of substrate part is situated between Between 120~800 angstroms.

As a preferred solution of the present invention, the upper surface that the filling perforation conductive layer corresponds to gap silo roof end has There are the high point formed by polycrystalline and low spot, and the high point is higher by 80~300 angstroms of the low spot.

As a preferred solution of the present invention, in conductor filled structure described in step 2) silicon grain size number between 50~ Between 1500 angstroms.

As a preferred solution of the present invention, in the conductor filled structure weight percent of germanium between 10%~ Between 80%.

As a preferred solution of the present invention, formed the temperature of the conductor filled structure between 350~450 DEG C it Between, the pressure of the conductor filled structure is formed between 250~900 millitorrs.

The present invention also provides a kind of preparation methods of capacitor arrangement array, include the following steps:

1) semi-conductive substrate is provided, the semiconductor substrate includes that several capacitors being located in memory array structure connect Node is touched, and in forming the sacrificial layer and supporting layer being alternately superimposed in the semiconductor substrate；

2) in the Patterned masking layer for forming the window with array arrangement in the structure that step 1) obtains, and based on described Patterned masking layer etches the sacrificial layer and the supporting layer, to form capacitor corresponding with window hole, the capacitor Hole appears the capacitance contact node；

3) bottom in Yu Suoshu capacitor hole and side wall form lower electrode layer, and remove the sacrificial layer, under appearing described The outer surface of electrode layer；

4) inner surface of Yu Suoshu lower electrode layer and the outer surface appeared form capacitor dielectric layer, and are situated between in the capacitor The surface of matter layer forms upper electrode layer；

5) surface of Yu Suoshu upper electrode layer forms conductor filled structure, and the conductor filled structure filling is in the lower electricity Pole layer inner wall between and the outer surface of the adjacent lower electrode layer between gap and extend over the upper electrode layer, In, the material source for forming the conductor filled structure includes at least silicon source and ge source, described in the germanium atom conduct in the ge source The nucleus of silicon atom aggregation growth in silicon source, to increase silicon grain size number in the conductor filled structure formed；And

6) top electrode coating is formed in the conductor filled body structure surface.

As a preferred solution of the present invention, in step 5), the conductor filled structure include filling perforation conductive layer and Gap storehouse, wherein the gap storehouse is by the gap between the polysilicon of the filling perforation conductive layer of capacitor hole institute characterizing portion It constitutes, and the filling perforation conductive layer coats the gap storehouse.

As a preferred solution of the present invention, the upper surface of the filling perforation conductive layer is compared to the lower electrode layer top The upper surface of the upper electrode layer of top is higher by 120~800 angstroms.

As a preferred solution of the present invention, the filling perforation conductive layer correspond to gap silo roof end upper surface with And at least one of both upper surfaces of the filling perforation conductive layer have the high point formed by polycrystalline and low spot, and institute It states high point and is higher by 80~300 angstroms of the low spot.

As a preferred solution of the present invention, in step 5), the weight percent of germanium is situated between in the conductor filled structure Between 10%~80%.

As a preferred solution of the present invention, in step 5), silicon grain size number is between 50 in the conductor filled structure Between~1500 angstroms；The temperature of the conductor filled structure is formed between 350~450 DEG C, forms the conductor filled knot The pressure of structure is between 250~900 millitorrs.

As a preferred solution of the present invention, in step 1), the quantity of the supporting layer is three layers, including top layer support Layer, middle support layer and base layer support layer, the quantity of the sacrificial layer are two layers, including be located at the top support layer with it is described First sacrificial layer and the second sacrifice between the base layer support layer and the middle support layer between middle support layer Layer；In step 3), the step of removing the sacrificial layer, includes:

The first opening is formed in Yu Suoshu top support layer, 3-1) to expose first sacrifice for being located at its lower surface Layer；

3-2) based on first opening, first sacrificial layer is removed using wet-etching technology；

The second opening is formed in Yu Suoshu middle support layer, 3-3) to expose second sacrifice for being located at its lower surface Layer；

3-4) based on second opening, second sacrificial layer is removed using wet-etching technology

As a preferred solution of the present invention, step 3-1) in, one it is described first opening only with a capacitor Hole is overlapping or first opening is overlapping with multiple capacitor holes simultaneously；Step 3-3) in, one described second is opened Mouth is only overlapped with a capacitor hole or second opening is overlapping with multiple capacitor holes simultaneously.

It as a preferred solution of the present invention, further include being doped to the conductor filled structure in step 5) Step, any one of doped chemical in boron, phosphorus and arsenic；It further include in the top electrode coating after step 6) Surface forms the step of oxide layer.

As a preferred solution of the present invention, it is further comprised the steps of: between step 5) and step 6) in described conductor filled Body structure surface formed a protective layer, it is described it is protective layer used in prevent the germanium in the conductor filled structure to the shadow of follow-up process It rings, wherein the material of the protective layer includes boron doped polysilicon.

As a preferred solution of the present invention, the conductor filled structure is made in same reaction chamber with the protective layer It is standby；The ge source gas for forming the conductor filled structure includes GeH₄And Ge₂H₆At least one of, it is formed described conductor filled The silicon source gas of structure includes SiH₄、Si₂H₆And SiH₆At least one of Cl；The silicon source gas for forming the protective layer includes SiH₄、Si₂H₆And SiH₆At least one of Cl, the boron source gas for forming the protective layer includes BCl₃And B₂H₆In at least one Kind；Wherein, the temperature of the protective layer is formed between 300~500 DEG C, and pressure is formed between 200~900 millitorrs The protective layer thickness between 400~1500 angstroms.

The present invention also provides a kind of conductor structures based on polysilicon processing procedure, comprising:

Substrate is formed with cave structure in the substrate；And

Conductor filled structure in the cave structure, and forms the material source of the conductor filled structure at least Include silicon source and ge source, wherein nucleus of the germanium atom as silicon atom aggregation growth in the silicon source in the ge source, to increase Silicon grain size number in the big conductor filled structure.

As a preferred solution of the present invention, the conductor filled structure includes filling perforation conductive layer and gap storehouse, wherein The gap storehouse is made of the gap between the polysilicon of the filling perforation conductive layer, and the filling perforation conductive layer coats the gap Storehouse.

As a preferred solution of the present invention, the filling perforation conductive layer is filled in the groove structure and also extends and covers Cover the upper surface of the substrate around the groove structure, the gap position in storehouse is described in as defined by the groove structure In filling perforation conductive layer；The filling perforation conductive layer is located at the thickness of the upper surface of substrate part between 120~800 angstroms.

As a preferred solution of the present invention, also there is doped chemical, the doping member in the conductor filled structure Any one formation of element in boron, phosphorus and arsenic.

As a preferred solution of the present invention, the weight percent of the germanium in the conductor filled structure between 10%~ Between 80%；The upper surface that the filling perforation conductive layer corresponds to gap silo roof end, which has, is accumulated the high point formed by silicon crystal grain With low spot, the high point is higher by 80~300 angstroms of the low spot；Silicon grain size number is between 50~1500 in the conductor filled structure Between angstrom.

The present invention also provides a kind of array of capacitors structures, comprising:

Semiconductor substrate, the semiconductor substrate include that several are located at the capacitance contact node in memory array structure；

Lower electrode layer is engaged on the capacitance contact node, and the cross sectional shape of the lower electrode layer includes U-shaped；

Capacitor dielectric layer is covered in inner surface and the outer surface of the lower electrode layer；

Upper electrode layer is covered in the surface of the capacitor dielectric layer；

Conductor filled structure, is filled between the inner sidewall of the lower electrode layer and the outer surface of the adjacent lower electrode layer Between gap and extend over the upper electrode layer, wherein the material source for forming the conductor filled structure includes at least silicon Source and ge source, the germanium atom in the ge source is used for the nucleus as silicon atom aggregation growth in the silicon source, described in increase Silicon grain size number in conductor filled structure；And

Top electrode coating is covered in the surface of the conductor filled structure.

As a preferred solution of the present invention, the conductor filled structure includes filling perforation conductive layer and gap storehouse, wherein The gap storehouse is made of the gap between the polysilicon of the filling perforation conductive layer of capacitor hole institute characterizing portion, and described Filling perforation conductive layer coats the gap storehouse.

As a preferred solution of the present invention, the upper surface of the filling perforation conductive layer is compared to the lower electrode layer top The upper surface of the upper electrode layer of top is higher by 120~800 angstroms；The filling perforation conductive layer is revealed in the surface in the gap storehouse And at least one of both upper surfaces of the filling perforation conductive layer have the high point formed and low spot are accumulated by silicon crystal grain, and The high point is higher by 80~300 angstroms of the low spot.

As a preferred solution of the present invention, the weight percent of the germanium in the conductor filled structure between 10%~ Between 80%；The silicon grain size number of the conductor filled structure is between 50~1500 angstroms.

As a preferred solution of the present invention, also there is doped chemical, the doping member in the conductor filled structure Any one of element in boron, phosphorus and arsenic；The top electrode cover surface is also formed with oxide layer.

As a preferred solution of the present invention, it is also formed between the conductor filled structure and the top electrode coating Matcoveredn, it is described protective layer used in preventing influence of the germanium in the conductor filled structure to follow-up process, wherein the guarantor The material of sheath includes boron doped polysilicon.

As described above, the conductor structure of the invention based on polysilicon processing procedure, array of capacitors structure and respective preparation Method has the advantages that

In conductor structure and preparation of the invention, manufacture big crystal grain (large grain size) DOPOS doped polycrystalline silicon is proposed Mode, introduce as silicon crystal grain aggregation growth nucleus element, such as Germanium, germanium atom is mixed in polysilicon to be helped Help polysilicon grain to grow up, germanium atom can achieve the effect of similar silicon wafer core in doped polysilicon, make silicon atom assemble into And grain size number is increased, crystal boundary trap (grain boundary trap) can be reduced to carrier by increasing polysilicon crystal granularity (carrier) influence increases conductivity in turn, i.e. reduction grain boundary density, promotes electric conductivity.Aforesaid way can be applied to various With on the conducting wire of polysilicon processing procedure, such as capacitor arrangement, in addition, the present invention also passes through the setting of protective layer, to realize anti- Only influence of the germanium in conductor filled structure to processing procedure, and reached effectively connecting between conductor filled structure and other structures layer It connects, and by the introducing of doped chemical etc., further improves the electric property of conductor filled structure.

Detailed description of the invention

Fig. 1 is shown as the preparation technology flow chart of the conductor structure provided by the invention based on polysilicon processing procedure.

Fig. 2 is shown as providing the structural schematic diagram of substrate in the preparation of conductor structure of the invention.

Fig. 3 is shown as forming the schematic diagram of cave structure in the preparation of conductor structure of the invention in the substrate.

Fig. 4 is shown as forming the schematic diagram of conductor filled structure in the preparation of conductor structure of the invention.

Fig. 5 is shown as the preparation technology flow chart of array of capacitors structure provided by the invention.

Fig. 6 is shown as providing the structural schematic diagram of semiconductor substrate in array of capacitors structure preparation of the invention.

Fig. 7 is shown as forming showing for the sacrificial layer and supporting layer being alternately superimposed in array of capacitors structure preparation of the invention It is intended to.

Fig. 8 is shown as forming the structural schematic diagram of Patterned masking layer in array of capacitors structure preparation of the invention.

Fig. 9 is shown as forming the structural schematic diagram in capacitor hole in array of capacitors structure preparation of the invention.

Figure 10 is shown as forming the structural schematic diagram of lower electrode layer in array of capacitors structure preparation of the invention.

Figure 11 is shown as forming the top view of the first opening in array of capacitors structure preparation of the invention.

Figure 12 is shown as forming the cross section structure schematic diagram of the first opening in array of capacitors structure preparation of the invention.

Figure 13 is shown as removing the structural schematic diagram after the first sacrificial layer in Figure 11 at the section A-A '.

Figure 14 is shown as the section A-A ' in Figure 11 and forms the structural schematic diagram after the second opening.

Figure 15 is shown as removing the structural schematic diagram after the second sacrificial layer in Figure 11 at the section A-A '.

Figure 16 is shown as forming the structural schematic diagram of capacitor dielectric layer in array of capacitors structure preparation of the invention.

Figure 17 is shown as forming the structural schematic diagram of upper electrode layer in array of capacitors structure preparation of the invention.

Figure 18 is shown as forming the structural schematic diagram of conductor filled structure in array of capacitors structure preparation of the invention.

Figure 19 is shown as the partial enlargement diagram of A dotted line frame in Figure 18.

Figure 20 is shown as the partial enlargement diagram of B dotted line frame in Figure 18.

Figure 21 is shown as forming the structural schematic diagram of protective layer in array of capacitors structure preparation of the invention.

Figure 22 is shown as forming the structural schematic diagram of top electrode coating in array of capacitors structure preparation of the invention.

Figure 23 is shown as the structural schematic diagram in the section A-B in Figure 22.

Figure 24 is shown as the partial enlarged view at the dotted line frame in Figure 22.

Figure 25 is shown as forming the structural schematic diagram of oxide layer in array of capacitors structure preparation of the invention.

Component label instructions

100 semiconductor substrates

101 capacitance contact nodes

102 base layer support layers

103 second sacrificial layers

104 middle support layers

105 first sacrificial layers

106 top support layers

107 Patterned masking layers

108 windows

109 capacitor holes

110 lower electrode layers

111 openings

1111 first openings

1112 second openings

112 capacitor dielectric layers

113 upper electrode layers

114 filling perforation conductive layers

115 gaps storehouse

116 conductor filled structures

117 protective layers

118 top electrode coatings

119 oxide layers

200 substrates

201 cave structures

202 conductor filled structures

203 filling perforation conductive layers

204 gaps storehouse

S1~S6 step 1)~step 6)

Specific embodiment

Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from Various modifications or alterations are carried out under spirit of the invention.

Fig. 1 is please referred to Figure 25.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its Assembly layout form may also be increasingly complex.

Embodiment one:

As shown in figures 1-4, the present invention provides a kind of preparation method of conductor structure based on polysilicon processing procedure, including such as Lower step:

Firstly, carrying out step 1) shown in S1 as shown in figure 1 and Fig. 2~3, providing a substrate 200, Yu Suoshu substrate 200 Middle formation cave structure 201.

Specifically, this step, which provides, is subsequently formed the structure basis of conductor filled structure, wherein the substrate 200 can be with For single material layer, such as silicon material layer, silicon-on-insulator material layer, germanium material layer and insulating medium layer (such as silicon oxide layer) Deng for opening up groove wherein and forming conductor filled structure as metal contact wires, certainly, the substrate 200 be can also be Any semiconductor laminated structure needs to open up depression wherein and is used to prepare conductor filled structure, to realize conductive or connection Effect, with actual production research and development demand setting, be not particularly limited herein.

In addition, cave structure 201 herein is not limited to the U-shaped groove structure in diagram, arbitrary tool can also be There are the structure of opening, bottom and side wall, such as inverted trapezoidal, square trench, as long as can be with deposited conductor interstitital texture, together Sample can be perforative through-hole up and down, and cross sectional shape can be irregular type, such as have curvilinear sidewall, not do herein specific Limitation.

Secondly, carrying out step 2) shown in S2 and Fig. 4 as shown in figure 1, being formed in Yu Suoshu cave structure 201 conductor filled Structure 202, and the material source for forming the conductor filled structure 202 includes at least silicon source and ge source, wherein in the ge source Nucleus of the germanium atom as silicon atom aggregation growth in the silicon source, to increase silicon grain size number in the conductor filled structure.

Specifically, this step is intended to be formed the high conductor filled structure 202 of conductivity, wherein the application passes through in conductor Nucleus element is introduced in the forming process of interstitital texture to act on the nucleus of polysilicon grain aggregation growth, so as to effective Increase polysilicon crystal granularity, germanium (Ge) atom is such as mixed in polysilicon to help polysilicon grain to grow up, and germanium atom exists The effect that can achieve similar silicon wafer core in doped polysilicon assembles silicon atom and then increases grain size number, increases polysilicon Grain size number can reduce influence of the crystal boundary trap (grain boundary trap) to carrier (carrier) and then increase and lead Electric rate, simple process, cost is relatively low, wherein the conductor filled structure 202 of formation is located in the cave structure 201, can To fill the full cave structure, it is located at its side wall and bottom, can also be with the not completely filled cave structure, it certainly can be with The material layer around the cave structure is covered simultaneously.In addition, silicon grain size number is that those of ordinary skill in the art are ripe herein Know, such as can be the size for the silicon crystal grain to be formed, such as is characterized as the diameter of silicon crystal grain.

As an example, the conductor filled structure 202 includes filling perforation conductive layer 203 and gap storehouse 204 in step 2), In, the gap storehouse 204 is made of the gap between the polysilicon of the filling perforation conductive layer 203, and the filling perforation conductive layer 203 Coat the gap storehouse 204.

Specifically, in one example, as shown in figure 4, the conductor filled structure 202 include filling perforation conductive layer 203 and Gap storehouse 204 forms the surface of coarse conductor filled structure under the process conditions of the present embodiment setting, wherein in deposition shape During at the conductor filled structure 202, deposition materials are initially formed along the bottom of cave structure and side wall, due to big Grain size number, opposite deposition materials layer gradually deposit close, opposite surface and surround a gap storehouse 204, and being formed includes filling out The conductor filled structure 202 in hole conductive layer 204 and gap storehouse 204, in addition, the presence in the gap storehouse 204 can also be alleviated Ess-strain between each material layer of the gap storehouse periphery prevents the thermal expansion of each material layer from squeezing etc., to protect whole Body device architecture.

As an example, the filling perforation conductive layer 203 is filled in the cave structure 201 and extends over the depression knot The upper surface of the substrate 200 around structure 201, the gap storehouse 204 are located at the institute as defined by the cave structure 201 It states in filling perforation conductive layer 203.

Specifically, in another example, being also formed with institute on the upper surface of the substrate 200 around the cave structure 201 State conductor filled structure 202, wherein the conductor filled structure 202 includes filling perforation conductive layer 203 and gap storehouse 204, and institute It states gap storehouse 204 to be preferably formed in the filling perforation conductive layer defined by the slot of the cave structure, the institute of upper surface of substrate It states and does not form the gap storehouse in filling perforation conductive layer.

As an example, the filling perforation conductive layer 203 is located at the thickness of the upper surface of substrate part between 120~800 angstroms Between.

As an example, the upper surface that the filling perforation conductive layer 203 corresponds to 204 top of gap storehouse has by polysilicon The high point formed and low spot are accumulated, and the high point is higher by 80~300 angstroms of the low spot, as shown in the D2 in Fig. 4.

As an example, the surface that the filling perforation conductive layer 203 is revealed in the gap storehouse 204, which has, accumulates shape by silicon crystal grain At high point and low spot, and the high point is higher by 80~300 angstroms of the low spot, as shown in the D1 in Fig. 4.

As an example, the silicon grain size number in the conductor filled structure 202 is between 50~1500 angstroms in step 2).

Specifically, controlling it in the thickness of 200 upper surface portion of substrate for the thickness of the filling perforation conductive layer 203 Degree is 120~800 angstroms, wherein grain size number can increase as this position film thickness increases in conductor filled structure 202, but If the too thick flatness that can make surface becomes too poor, follow-up process is influenced, it is therefore preferable that should be with a thickness of 200~600 angstroms, this reality It applies and is selected as 500 angstroms in example, electric property is good so as to obtaining, and is conducive to the conductor filled structure of follow-up process.

Further, using method in this example, the silicon grain size number in the conductor filled structure 202 of formation is about 50~1500 angstroms, it is preferably formed as 500~1000 angstroms of crystal grain, forms about 800 ± 10 angstroms of silicon crystal grain in the present embodiment.

In addition, the exposed position of the conductor filled structure 202, such as filling perforation conductive layer 203 is revealed in this example The surface of the part in the gap storehouse 204, the filling perforation conductive layer 203 are located at the table of the part of the upper surface of the substrate 200 Face can all form the spikes/low- points of crystal grain accumulation as shown in the D3 in Fig. 4, in this example, preferably appear position Highest point is the high point, and the minimum point for appearing position is the low spot, wherein highest and it is minimum be that it is heavy relative to described For long-pending structure, such as the upper surface of the side wall of cave structure, the bottom of cave structure and substrate, wherein the high point is high The difference of the low spot out, as shown in 1~D3 of space D in Fig. 4, high difference is preferably 100~200 angstroms, is selected in this example Be 150 angstroms, so as to facilitate conductor filled structure electric property raising and facilitate the gap storehouse and formed to close Suitable size, equally, the filling perforation conductive layer 203 corresponds to the upper surface on 204 top of gap storehouse also due to big silicon Grain size number forms such structure.

As an example, the weight percent of germanium is between 10%~80% in the conductor filled structure 202.

As an example, the temperature for forming the conductor filled structure 202 forms the conductor between 350~450 DEG C The pressure of interstitital texture 202 is between 250~900 millitorrs.

Specifically, can use chemical vapor deposition process in the formation of the conductor filled structure of the present embodiment, will walk The rapid structure 1) obtained is placed in low-pressure chemical vapor deposition boiler tube；Lead to simultaneously into the low-pressure chemical vapor deposition boiler tube Enter silicon source gas and ge source gas is reacted, in the bottom of the groove structure, side wall or the table also in substrate simultaneously Face forms conductor filled structure, wherein silicon source gas is selected from SiH₄、Si₂H₆、SiH₆At least one of Cl, ge source gas are selected from GeH₄、 Ge₂H₆At least one of, form the temperature of the conductor filled structure 202 preferably at 380 DEG C~420 DEG C, this example In be selected as 400 DEG C, the pressure limit of Corresponding matching includes 250~450mT (millitorr), be selected as 300 ± 10mT in this example, Adjustment reaction temperature and pressure will further adjust the knot in the size of silicon grain size number and gap storehouse in conductor filled structure Structure.

In addition, it should also be noted that, further adjusting the doping ratio of germanium, preferably between 40%~60%, in this way Just the existing crystalline substance provided in deposition process further can be adjusted by the ratio of germanium under conditions of there is only silicon source and ge source The ratio of core, the best proportion from available better silicon atom deposition and germanium atom as nucleus, obtains reasonable silicon Grain size number, in this example, the ratio of germanium is selected as 50%.

Furthermore it is also possible to further include the steps that being doped it while conductor filled structure formation, it is such as logical Enter at least one of boron source gas, phosphorus source gas and arsenic source gas, to advanced optimize the electricity of the conductor filled structure Learn performance.

As shown in figure 4, the present invention also provides a kind of conductor structures based on polysilicon processing procedure, wherein the conductor structure It is preferred that the preparation method using conductor structure provided by the invention is prepared, certainly, can also use in other embodiments Other methods are prepared, it is not limited to which this, the conductor structure includes:

Substrate 200 is formed with cave structure 201 in the substrate；And

Conductor filled structure 202 is located in the cave structure 201, and forms the material of the conductor filled structure 202 Source includes at least silicon source and ge source, wherein crystalline substance of the germanium atom as silicon atom aggregation growth in the silicon source in the ge source Core, to increase the silicon grain size number in the conductor filled structure 202.

Specifically, the substrate 200 can be single material layer, such as silicon material layer, silicon-on-insulator material layer, germanium material The bed of material and insulating medium layer (such as silicon oxide layer) are for opening up groove wherein and forming conductor filled structure as metal Connecting line, certainly, the substrate 200 can also be any semiconductor laminated structure, need to open up groove wherein and are used to prepare Conductor filled structure, with actual production research and development demand setting, does not do specific limit to realize conductive or connection effect herein System.

In addition, cave structure 201 herein is not limited to the U-shaped groove structure in diagram, arbitrary tool can also be There is the structure of opening, bottom and side wall, as long as can equally can be perforative logical up and down with deposited conductor interstitital texture Hole, cross sectional shape can be irregular type, such as have curvilinear sidewall, be not particularly limited herein.

Specifically, the application acts on polysilicon grain aggregation life by introducing nucleus element in the forming process of conducting wire Long nucleus, so as to effectively increase polysilicon crystal granularity, germanium (Ge) atom is such as mixed in polysilicon to help Polysilicon grain growth, germanium atom can achieve the effect of similar silicon wafer core in doped polysilicon, make silicon atom aggregation in turn Grain size number is increased, crystal boundary trap (grain boundary trap) can be reduced to carrier by increasing polysilicon crystal granularity (carrier) influence increases conductivity in turn, and simple process, cost is relatively low.Wherein, the conductor filled structure of formation 202 are located in the cave structure 201, can fill the completely described cave structure, are located at its side wall and bottom, can also be incomplete The cave structure is filled, the material layer around the cave structure can also be covered simultaneously certainly.

As an example, the conductor filled structure 202 includes filling perforation conductive layer 203 and gap storehouse 204, wherein between described Gap storehouse 204 is made of the gap between the polysilicon of the filling perforation conductive layer 203, and the filling perforation conductive layer 203 coat it is described Gap storehouse 204.

As an example, the filling perforation conductive layer 203 is filled in the cave structure 201 and extends over the depression knot The upper surface of the substrate 200 around structure 201, the gap storehouse 204 are located at the institute as defined by the cave structure 201 It states in filling perforation conductive layer 203；The filling perforation conductive layer 203 is located at the thickness of the upper surface of substrate part between 120~800 angstroms Between.

Specifically, in one example, as shown in figure 4, the conductor filled structure 202 include filling perforation conductive layer 203 and Gap storehouse 204 forms the surface of coarse conductor filled structure under the process conditions of the present embodiment setting, wherein in deposition shape During at the conductor filled structure 204, deposition materials are initially formed along the bottom of groove structure and side wall, due to big Grain size number, opposite deposition materials layer gradually deposit close, opposite surface and surround a gap storehouse 204, and being formed includes filling out The conductor filled structure 202 in hole conductive layer 204 and gap storehouse 204, the presence in the gap storehouse 204 can also alleviate it is described between Ess-strain between each material layer of gap storehouse periphery prevents the thermal expansion of each material layer from squeezing etc., to protect integral device Structure.

As an example, the weight percent of the germanium in the conductor filled structure 202 is between 10%~80%.

As an example, the upper surface that the filling perforation conductive layer 203 corresponds to 204 top of gap storehouse has by polysilicon The high point formed and low spot are accumulated, and the high point is higher by 80~300 angstroms of the low spot, as shown in the D1 in Fig. 4.

As an example, the surface that the filling perforation conductive layer 203 is revealed in the gap storehouse 204, which has, accumulates shape by silicon crystal grain At high point and low spot, the high point is higher by 80~300 angstroms of the low spot, as shown in the D1 in Fig. 4；The conductor filled structure 202 silicon grain size number is between 50~1500 angstroms.

Further, using method in this example, the silicon grain size number in the conductor filled structure 202 of formation is about 50~1500 angstroms, it is preferably formed as 500~1000 angstroms of crystal grain.

In addition, the exposed position of the conductor filled structure 202, such as filling perforation conductive layer 203 is revealed in this example The surface of the part in the gap storehouse 204, the filling perforation conductive layer 203 are located at the table of the part of the upper surface of the substrate 200 Face, the spikes/low- points that can all form the accumulation of a crystal grain in this example, preferably appear position as shown in the D3 in Fig. 4 Highest point is the high point, and the minimum point for appearing position is the low spot, wherein highest and it is minimum be that it is heavy relative to described For long-pending structure, such as the upper surface of the side wall of cave structure, the bottom of cave structure and substrate, wherein the high point is high The difference of the low spot out, as shown in 1~D3 of space D in Fig. 4, high difference is preferably 100~200 angstroms, is selected in this example Be 150 ± 10 angstroms, so as to facilitate conductor filled structure electric property raising and facilitate gap storehouse shape At suitable size, equally, the filling perforation conductive layer 203 corresponds to the upper surface on 204 top of gap storehouse also due to big Silicon grain size number form such structure.

As an example, in the conductor filled structure 202 also have doped chemical, the doped chemical be selected from boron, phosphorus and Any one formation in arsenic.

Specifically, boron source gas, phosphorus source gas and arsenic can also be passed through while conductor filled structure formation At least one of source gas, to advanced optimize the electric property of the conductor filled structure.

Embodiment two:

As shown in figure 5, the present invention also provides a kind of preparation methods of capacitor arrangement array, wherein in the present embodiment two Capacitor arrangement array preparation in include embodiment one kind the conductor structure based on polysilicon processing procedure preparation, including step It is rapid:

Below in conjunction with the preparation method of the attached drawing array of capacitors structure that the present invention will be described in detail.

Firstly, as in Fig. 5 S1 and Fig. 6~7 shown in, carry out step 1), provide semi-conductive substrate 100, and in described The sacrificial layer being alternately superimposed on is formed in semiconductor substrate 100, such as 103,105 and supporting layer, such as 102,104,106.

As an example, the semiconductor substrate 100 includes that several are located at the capacitor in memory array structure in step 1) Contact node 101.

Specifically, the substrate 100 further includes semiconductor base (not shown), semiconductor base in a specific structure It is inside provided with active area and wordline, bit line and the capacitance contact node 101, the capacitance contact are provided on semiconductor base Node 101 is electrically connected the transistor source etc. in the memory array structure.

In addition, the capacitance contact node 101 can arrange in six square arrays, the arrangement phase with the capacitor of subsequent production It is corresponding.And be isolated between the capacitance contact node 101 by wall, the material of the wall can be silicon nitride (SiN), silica (SiO₂), aluminium oxide (Al₂O₃) in any one or any two or more combinations, in the present embodiment, The material selection of the wall is SiN.

As an example, the quantity of the supporting layer of formation is greater than the quantity of the sacrificial layer formed in step 1), and The underlying material layers and quilting material layer that the sacrificial layer and the supporting layer are constituted in laminated construction are the supporting layer.

In one example, the quantity of the supporting layer include three layers, including top support layer 106, middle support layer 104 and Base layer support layer 102, the quantity of the sacrificial layer include two layers, including are located at the top support layer 106 and the intermediate branch Support the first sacrificial layer 105 between layer 104 and the between the base layer support layer 102 and the middle support layer 104 Two sacrificial layers 103.

Specifically, can be heavy using atom layer deposition process (Atomic Layer Deposition) or plasma vapor Product technique (Plasma Enhenced Chemical Vapor Deposition) forms each supporting layer and each sacrificial layer, such as The base layer support layer 102, the second part sacrificial layer 103, the middle support layer 104, the second part sacrificial layer 105 and the top support layer 106.

It should be noted that the material of the sacrificial layer includes silica or silicon oxynitride or polysilicon layer, the sacrifice Can include doped with boron or phosphorus, the material of the supporting layer in layer silicon nitride, silicon oxynitride, in aluminium oxide any one or Any two or more combination.The material of the sacrificial layer is different from the material of the supporting layer, and same etching process (such as Same corrosive liquid) in both corrosion rate it is different, be embodied in same etching process (such as same corrosive liquid), it is described Etching (as corroded) rate of sacrificial layer is far longer than the etch rate of the supporting layer, so that when the sacrificial layer is gone completely Except when, the supporting layer is almost fully retained.In the present embodiment, the material of the sacrificial layer is SiO₂, the supporting layer Material be SiN, using wet corrosion technique, the corrosive liquid that the wet etching uses includes hydrofluoric acid solution and hydrofluoric acid ammonia One of aqueous solution.

In addition, except in the case of above-mentioned three enumerated layer supporting layer and two layers of sacrificial layer, the sacrificial layer and supporting layer Quantity can be set according to the required height of subsequent capacitance device, and the quantity of stacking can be for 1~10 time or more It is more, wherein to be advisable with 2~5 times.

Further, the sacrificial layer can be removed during subsequent technique, and the supporting layer is used in subsequent technique Braced frame is used as after the sacrificial layer is removed in the process, it, not only can be with since embodiment adds the braced frames The mechanical strength of structure when greatly improving subsequent production capacitor, more can to avoid when subsequent technique (such as grinding) to capacitor Caused by destroy.In addition, in this example, doped with boron or phosphorus in the sacrificial layer, it is ensured that the uniformity of critical size, And improve the removal rate of the sacrificial layer.

Then, as in Fig. 5 S2 and Fig. 8~9 shown in, carry out step 2), in the structure that step 1) obtains formed have The Patterned masking layer 107 of the window 108 of array arrangement, and based on the Patterned masking layer 107 in the sacrificial layer, such as 103, etching forms capacitor hole 109 corresponding with the window 108 in 105 and supporting layer, such as 102,104,106.

As an example, the capacitor hole 109 formed in step 2) exposes the capacitance contact node 101.

Specifically, realizing the definition to 109 position of capacitor hole by the step, a layer photoresist can be initially formed Layer, as the material layer of the Patterned masking layer 107, certainly, can also form the exposure mask of other materials in other examples Layer (such as silicon nitride hard mask layer), then, using photoetching process by the layer of material (such as photoresist layer) graphically, with To the Patterned masking layer 107 with the window 108, wherein the window 108 can be along the Patterned masking layer 107 surface is arranged in six square arrays, corresponding with the capacitance contact node 101 of lower section.

After the Patterned masking layer 107 is formed, the capacitor hole 109 is formed using it as mask etching, specifically: according to According to the Patterned masking layer 107 using dry etch process, wet-etching technology or dry etch process and wet etching work The technique that skill combines etches the supporting layer and the sacrificial layer, to be formed up and down in the supporting layer and the sacrificial layer The capacitor hole 109 of perforation, the capacitor hole 109 expose the capacitance contact node, as shown in Figure 9.

As an example, the depth-to-width ratio in the capacitor hole is between 5~20, the height model in the capacitor hole in step 2) It is trapped among in 0.5~5 μm.

Specifically, the depth-to-width ratio in the capacitor hole 109 is 5~20, preferably 6~10, it is selected as 8 in this example ± 0.5.The present embodiment can obtain the capacitor hole 109 of larger depth-to-width ratio by the stepped construction of design sacrificial layer and supporting layer, from And the capacitance of unit area is greatly improved, the integrated level and performance of memory device are improved, in this example, the capacitor hole 109 depth is 0.5~5 μm, and preferably 1~4 μm, 3 ± 0.5 μm are selected as in this example.

Continue, as in Fig. 5 S3 and Figure 10~15 shown in, carry out step 3), the bottom in Yu Suoshu capacitor hole 109 and side wall Lower electrode layer 110 is formed, and removes the sacrificial layer, such as 103,105, to appear the outer surface of the lower electrode layer 110.

Specifically, using atom layer deposition process (Atomic Layer Deposition) or plasma vapor deposition work The side wall in the Yu Suoshu capacitor hole 109 skill (Chemical Vapor Deposition) and bottom and the sacrificial layer and institute The upper surface deposition lower electrode material layer of the laminated construction of supporting layer composition is stated, the lower electrode material layer includes metal nitride And one or both of metal silicide is formed by compound, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide (Titanium Silicide), silicon titanium nitride (TiSixNy), it is preferable that this implementation In example, the material of the lower electrode material layer is titanium nitride；Then, then using techniques such as chemical mechanical grinding or etchings remove position The lower electrode material layer in the laminated construction upper surface, the side wall positioned at the capacitor hole 109 of reservation and bottom The lower electrode material layer is the lower electrode layer 110, and the supporting layer is connected with the outer surface of the lower electrode layer.

As an example, a kind of minimizing technology of sacrificial layer is provided, by taking following situations as an example: the quantity of the supporting layer It is three layers, including top support layer, middle support layer and base layer support layer, the quantity of the sacrificial layer is two layers, including is located at Between the top support layer and the middle support layer the first sacrificial layer and be located at the base layer support layer and the centre The second sacrificial layer between supporting layer, in step 3), the step of removing the sacrificial layer, includes:

The first opening 1111 3-1) is formed in Yu Suoshu top support layer 106, as shown in Figure 11 and 12, is located at exposing First sacrificial layer 105 of its lower surface；

3-2) based on first opening 1111, first sacrificial layer 105 is removed using wet etching, such as Figure 13 institute Show；

The second opening 1112, second opening and first opening 3-3) are formed in Yu Suoshu middle support layer 104 The opening 111 during this is constituted, to expose second sacrificial layer 103 for being located at its lower surface, as shown in figure 14；

3-4) based on second opening 1112, second sacrificial layer 103 is removed using wet etching, such as Figure 15 institute Show.

Specifically, when the sacrificial layer and the supporting layer are the material layer of other quantity or more, and so on, By open up opening and wet etching technique remove, in addition, as an example, step 3-2) and step 3-3) between further include In the upper surface depositing support layer material of the top support layer 106 the step of, the top support layer 106 is thickened.This It is since during step 3-2), the top support layer 106 can be removed a part, in order to prevent subsequent corrosion process Described in top support layer 106 cut through, and ensure at the support of upper layer have enough support strengths, need in step 3-2) It is added between step 3-3) in the upper surface depositing support layer material of the top support layer 106 the step of.

As an example, step 3-1) in, first opening 111 is only overlapping with a capacitor hole 109, or One first opening 111 is overlapping with multiple capacitor holes 109 simultaneously (as shown in figure 11, with first opening 1111 and three capacitor holes 109 are overlapping is used as example)；Step 3-3) in, second opening is only and described in one Capacitor hole 109 is overlapping or second opening is overlapping with multiple capacitor holes 109 simultaneously, wherein described second opens Mouth 1112 opens up opening up similar to first opening 1111, and as an example, the preferably second opening 1112 is opened with first About 1111 mouth is correspondingly arranged, and the Figure 11's that can be referred to opens up mode.

Continue, as in Fig. 5 S4 and Figure 16~17 shown in, carry out step 4), the inner surface of Yu Suoshu lower electrode layer 110 with And exposed outer surface forms capacitor dielectric layer 112, and forms top electrode liner layer in the surface of the capacitor dielectric layer 112 113。

Specifically, the material of the capacitor dielectric layer 112 can be selected as high K dielectric material, to improve unit area electricity The capacitance of container comprising one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or above-mentioned material group are in groups Two or more in group are formed by lamination.

In addition, using atom layer deposition process (Atomic Layer Deposition) or plasma vapor deposition technique (Chemical Vapor Deposition) forms the top electrode liner layer 113 for covering 112 outer surface of capacitor dielectric, institute State top electrode liner layer 113 material may include tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon, in p-type polysilicon Two or more in a kind of the formed group of or above-mentioned material are formed by lamination, can also include metal nitride and metallic silicon One or both of compound is formed by compound, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide (Titanium Silicide), silicon titanium nitride (TiSixNy).

Continue, as in Fig. 5 S5 and Figure 18~20 and Figure 23~24 shown in, carry out step 5), Yu Suoshu upper electrode layer 113 Surface form conductor filled structure 116, the conductor filled structure 116 is filled between the inner wall of the lower electrode layer 110 And gap between the outer surface of the adjacent lower electrode layer 110 and extend over the upper electrode layer 113, wherein form institute The material source for stating conductor filled structure 116 includes at least silicon source and ge source, and the germanium atom in the ge source is as in the silicon source The nucleus of silicon atom aggregation growth, to increase the silicon grain size number in the conductor filled structure.

Specifically, the purpose of this step is to prepare the metal connecting structure between capacitor and top electrode coating, i.e., The conductor filled structure, and it is conducive to implementation of the subsequent BEOL processing procedure after capacitor array completion, wherein array is completed Later, entire top electrode is coated with silica and just start from BEOL metal interconnection structure, by the conductor filled of embodiment one kind The preparation process of structure improves capacitor performance for being conducive in the capacitor of the present embodiment two.

In addition, region, the capacitor hole after having formed upper electrode layer 113, inside the capacitor hole 109 There are also certain spaces being not filled by the region between the supporting layer outside 109, and the conductor filled structure 116 is first The filling of this segment space is full, then continue deposition until covering the entire upper electrode layer 113, that is to say, that the conductor 116 at least part of interstitital texture is filled in the gap between the inside of the lower electrode layer 110 (such as U-shaped structure), and by It is formed between being surrounded afterwards positioned at the part of the lower electrode layer inner wall surface capacitor dielectric layer and the part upper electrode layer Gap, in addition, the conductor filled structure 116 some be filled between the adjacent lower electrode layer, and by adjacent The lower electrode layer outer surface partition capacitance dielectric layer and the gap that is surrounded of part upper electrode layer, then continue to sink Product is until cover the entire upper electrode layer 113.

It should also be noted that, this step is intended to be formed the high conductor filled structure 116 of conductivity, wherein the application is logical It crosses and introduces nucleus element in the forming process of conducting wire to act on the nucleus of polysilicon grain aggregation growth, so as to effective Increase polysilicon crystal granularity, germanium (Ge) atom is such as mixed in polysilicon to help polysilicon grain to grow up, and germanium atom exists The effect that can achieve similar silicon wafer core in doped polysilicon assembles silicon atom and then increases grain size number, increases polysilicon Grain size number can reduce influence of the crystal boundary trap (grain boundary trap) to carrier (carrier) and then increase and lead Electric rate, simple process, cost is relatively low.

As an example, the conductor filled structure includes filling perforation conductive layer 114 and gap storehouse 115 in step 5), wherein Gap of the gap storehouse 115 between the polysilicon of the filling perforation conductive layer 114 defined by the capacitor hole 109 is constituted, And the filling perforation conductive layer 114 coats the gap storehouse 115, as shown in figure 18.

Specifically, in one example, the conductor filled structure 116 includes filling perforation conductive layer 114 and gap storehouse 115, Under the process conditions of the present embodiment setting, the surface of coarse conductor filled structure is formed, wherein form the conductor in deposition During interstitital texture 116, the bottom for the groove-like structure that upper electrode layer surface of the deposition materials in capacitor hole is formed and Side wall initially forms, and due to big grain size number, opposite deposition materials layer gradually deposits close, opposite surface and surrounds one Gap storehouse 115 forms the conductor filled structure 116 including filling perforation conductive layer 114 and gap storehouse 115, the gap storehouse 116 In the presence of ess-strain between each material layer that can also alleviate the gap storehouse periphery, prevent the thermal expansion of each material layer from squeezing etc. Deng to protect integral device structure.

In addition, also being formed on the upper surface (upper electrode layer upper surface) of the semiconductor substrate 100 around the capacitor hole 109 There is the conductor filled structure 116, wherein the conductor filled structure 116 includes filling perforation conductive layer 114 and gap storehouse 115, And the gap storehouse 116 is preferably formed in the filling perforation conductive layer defined by the slot of the groove structure, upper surface of substrate The filling perforation conductive layer in do not form the gap storehouse.

As an example, the upper surface of the filling perforation conductive layer 114 is compared to described in 110 over top of lower electrode layer The upper surface of upper electrode layer 113 is higher by 120~800 angstroms.

As an example, upper surface and the filling perforation of the filling perforation conductive layer 114 corresponding to 115 top of gap storehouse At least one of upper surface of conductive layer 114, which has, is accumulated the high point formed and low spot by silicon crystal grain, and the high point is higher by 80~300 angstroms of the low spot, in addition, the surface that the filling perforation conductive layer 114 is revealed in the gap storehouse 115 also has the height Point and the low spot, as shown in FIG. 19 and 20.

As an example, silicon grain size number is between 50~1500 angstroms in the conductor filled structure 116.

Specifically, controlling its semiconductor around capacitor hole 109 for the thickness of the filling perforation conductive layer 114 100 upper surface portion of substrate with a thickness of 120~800 angstroms, wherein grain size number can be with this in conductor filled structure 116 Position film thickness increase and increase, if but the too thick flatness that can make surface become too poor, influence follow-up process, it is therefore preferable that this 500 angstroms are selected as with a thickness of 200~600 angstroms, in the present embodiment, it is good so as to obtain electric property, and be conducive to subsequent The conductor filled structure 116 of processing procedure.Further, the silicon using method in this example, in the conductor filled structure 116 of formation Grain size number is about 50~1500 angstroms, is preferably formed as 500~1000 angstroms of crystal grain.

In addition, the exposed position of the conductor filled structure 116, such as filling perforation conductive layer 114 is revealed in this example The surface of the part in the gap storehouse 115, as shown in figure 19, the filling perforation conductive layer 114 are located at around the capacitor hole 109 The surface of the part of the upper surface of the semiconductor substrate 100, as shown in figure 20 and the filling perforation conductive layer 114 is located at institute The upper surface for stating 115 top of gap storehouse inside capacitor hole 109 can all form the spikes/low- points of crystal grain accumulation, In this example, the highest point for preferably appearing position is the high point, and the minimum point for appearing position is the low spot, wherein most It is high and it is minimum be relative to it is described its deposition structure for, such as the side wall in capacitor hole, the bottom in capacitor hole and semiconductor The upper surface of substrate, wherein the high point is higher by the difference of the low spot, in Figure 19 and Figure 20 space D 1, as described in D2, it is high Difference is preferably 100~200 angstroms, so as to facilitate conductor filled structure electric property raising and facilitate described Gap storehouse forms suitable size.

As an example, in step 5), in the conductor filled structure 116 weight percent of germanium between 10%~80% it Between.

As an example, forming the temperature of the conductor filled structure in step 5) between 350~450 DEG C, forming institute The pressure of conductor filled structure is stated between 250~900 millitorrs.

Specifically, can use chemical vapor deposition process in the formation of the conductor filled structure of the present embodiment, will walk The rapid structure 1) obtained is placed in low-pressure chemical vapor deposition boiler tube；Lead to simultaneously into the low-pressure chemical vapor deposition boiler tube Enter silicon source gas and ge source gas is reacted, in the bottom of the groove structure, side wall or the table also in substrate simultaneously Face forms conductor filled structure, wherein silicon source gas is selected from SiH₄、Si₂H₆、SiH₆At least one of Cl, ge source gas are selected from GeH₄、 Ge₂H₆At least one of, form the temperature of the conductor filled structure 202 preferably at 380 DEG C~420 DEG C, this example In be selected as 400 ± 10 DEG C, the pressure limit of Corresponding matching includes 250~450mT, is selected as 300 ± 10mT in this example, is adjusted Whole reaction temperature and pressure will further adjust the size of silicon grain size number and the structure in gap storehouse in conductor filled structure.

As an example, in the conductor filled structure 116 also have doped chemical, the doped chemical be selected from boron, phosphorus and Any one formation in arsenic.

Finally, carrying out step 6) as shown in the S6 and Figure 22 in Fig. 5, being formed in the surface of the conductor filled structure 116 Top electrode coating 118.

Specifically, the top electrode coating 118 is formed in the surface of the conductor filled structure 116, material includes But it is not limited to tungsten metal, the top electrode coating 118 can be used for the contact point of tungsten plug (W plug).

As shown in figure 21, as an example, being further comprised the steps of: between step 5) and step 6) in the conductor filled structure 116 surfaces form a protective layer 117, and the protective layer 117 is for preventing the germanium in the conductor filled structure 116 to subsequent The influence of processing procedure, wherein the material of the protective layer 117 includes boron doped polysilicon.

Specifically, the protective layer 117 be formed in the conductor filled structure 116 and the top electrode coating 118 it Between, on the one hand, the protective layer 117 can prevent influence of the germanium to follow-up process in the conductor filled structure 116, separately Outside, the protective layer 117 can also increase the adherency between the conductor filled structure 116 and the top electrode coating 118 Property, also, the material of the protective layer 117 is preferably boron doped polysilicon, also advantageously improves the conductor filled structure Electric conductivity between 116 and the top electrode coating 118.

As an example, the conductor filled structure 116 is prepared in same reaction chamber with the protective layer 117；Form institute The ge source gas for stating conductor filled structure 116 includes GeH₄And Ge₂H₆At least one of, form the conductor filled structure 116 Silicon source gas include SiH₄、Si₂H₆And SiH₆At least one of Cl；The silicon source gas for forming the protective layer 117 includes SiH₄、Si₂H₆And SiH₆At least one of Cl, the boron source gas for forming the protective layer 117 includes BCl₃And B₂H₆In extremely Few one kind；Wherein, form the temperature of the protective layer 117 between 300~500 DEG C, pressure between 200~900 millitorrs it Between, the thickness of the protective layer of formation is between 400~1500 angstroms.

Specifically, the temperature for forming the protective layer 117 is preferably 350~450 DEG C, the pressure of the protective layer 117 is formed Power range is selected as 600 ± 20mT between 250~800mT in this example, thickness range is preferably 600~1000 angstroms.

As an example, further including the steps that being doped the conductor filled structure 116 in step 5), doped chemical choosing From any one in boron, phosphorus and arsenic；It further include being formed to aoxidize in 118 surface of top electrode coating after step 6) The step of layer 119, as shown in figure 25.

Specifically, can also the conductor filled structure 116 formation while, be passed through boron source gas, phosphorus source gas with And at least one of arsenic source gas, to advanced optimize the electric property of the conductor filled structure.

In addition, further including the steps that continuously forming oxide layer after the top electrode coating 118 is formed, oxygen is such as formed SiClx layer coats entire top electrode with silica and just starts from BEOL metal interconnection structure.

As shown in Figure 18~25, the present invention also provides a kind of array of capacitors structures, wherein the array of capacitors structure It is preferred that being prepared using preparation method of the invention, certainly, it is not limited to which this, the array of capacitors structure includes:

Semiconductor substrate 100, the semiconductor substrate include that several are located at the capacitance contact section in memory array structure Point 101；

Lower electrode layer 110 is engaged on the capacitance contact node 101, and the cross sectional shape of the lower electrode layer includes U Type；

Capacitor dielectric layer 112 is covered in inner surface and the outer surface of the lower electrode layer 110；

Upper electrode layer 113 is covered in the surface of the capacitor dielectric layer 112；

Conductor filled structure 116, is filled between the inner wall of the lower electrode layer 110 and the adjacent lower electrode layer 110 Outer surface between gap and extend over the upper electrode layer 113, wherein form the material of the conductor filled structure 116 Material source includes at least silicon source and ge source, and the germanium atom in the ge source is used for the crystalline substance as silicon atom aggregation growth in the silicon source Core, to increase the silicon grain size number in the conductor filled structure；And

Top electrode coating 118 is covered in the surface of the upper conductor interstitital texture 116.

Specifically, the conductor filled structure 116 is as the metal connecting structure between capacitor and top electrode coating, And it is conducive to implementation of the subsequent BEOL processing procedure after capacitor array completion, wherein after array is completed, coated with silica Entire top electrode just starts from BEOL metal interconnection structure, and the preparation process of the conductor filled structure of embodiment one kind is used for In the capacitor of the present embodiment two, be conducive to improve capacitor performance.

In addition, region, the capacitor hole after having formed upper electrode layer 113, inside the capacitor hole 109 There are also certain spaces being not filled by the region between the supporting layer outside 109, and the conductor filled structure 116 is first The filling of this segment space is full, then continue deposition until covering the entire upper electrode layer 113.

As an example, the conductor filled structure 116 includes filling perforation conductive layer 114 and gap storehouse 115, wherein between described Gap of the gap storehouse 115 between the polysilicon of the filling perforation conductive layer 114 defined by the capacitor hole 109 is constituted, and described Filling perforation conductive layer 114 coats the gap storehouse 115.

As an example, the upper surface of the filling perforation conductive layer 114 is compared to described in 110 over top of lower electrode layer The upper surface of upper electrode layer 113 is higher by 120~800 angstroms；The filling perforation conductive layer 114 corresponds to 115 top of gap storehouse At least one of upper surface and the upper surface of the filling perforation conductive layer 114 have the high point that is formed by polycrystalline with it is low Point, and the high point is higher by 80~300 angstroms of the low spot, in addition, the filling perforation conductive layer 114 is revealed in the gap storehouse 115 Surface also there is the high point and the low spot.

As an example, the weight percent of the germanium in the conductor filled structure 116 is between 10%~80%；It is described The silicon grain size number of conductor filled structure 116 is between 50~1500 angstroms.

Specifically, controlling its semiconductor around capacitor hole 109 for the thickness of the filling perforation conductive layer 114 100 upper surface portion of substrate with a thickness of 120~800 angstroms, wherein grain size number can be with this in conductor filled structure 116 Position film thickness increase and increase, if but the too thick flatness that can make surface become too poor, influence follow-up process, it is therefore preferable that this 500 ± 20 angstroms are selected as with a thickness of 200~600 angstroms, in the present embodiment, it is good so as to obtain electric property, and be conducive to The conductor filled structure 116 of follow-up process.Further, using method in this example, in the conductor filled structure 116 of formation Silicon grain size number be about 50~1500 angstroms, be preferably formed as 500~1000 angstroms of crystal grain.

In addition, the exposed position of the conductor filled structure 116, such as filling perforation conductive layer 114 is revealed in this example The surface of the part in the gap storehouse 115, as shown in figure 19, the filling perforation conductive layer 114 are located at around the capacitor hole 109 The surface of the part of the upper surface of the semiconductor substrate 100, as shown in figure 20 and the filling perforation conductive layer 114 is located at institute The upper surface for stating 115 top of gap storehouse inside capacitor hole 109 can all form the spikes/low- points of crystal grain accumulation, In this example, the highest point for preferably appearing position is the high point, and the minimum point for appearing position is the low spot, wherein most It is high and it is minimum be relative to it is described its deposition structure for, such as the side wall in capacitor hole, the bottom in capacitor hole and semiconductor The upper surface of substrate, the upper surface that the conductor filled structure 116 corresponds to 115 top of gap storehouse have by polycrystalline silicon stack The high point and low spot that product is formed, and the high point is higher by 80~300 angstroms of the low spot, wherein the high point is higher by the low spot Difference, in Figure 19 and Figure 20 space D 1, as described in D2, high difference is preferably 100~200 angstroms, and 150 are selected as in this example ± 10 angstroms, so as to facilitate conductor filled structure electric property raising and facilitate the gap storehouse and formed properly Size.

In addition, it should also be noted that, further adjusting the doping ratio of germanium, preferably between 40%~60%, in this way Just the existing crystalline substance provided in deposition process further can be adjusted by the ratio of germanium under conditions of there is only silicon source and ge source The ratio of core, the best proportion from available better silicon atom deposition and germanium atom as nucleus, obtains reasonable silicon Grain size number, in this example, the ratio of germanium is selected as 50 ± 5%.

As an example, being also formed with protective layer between the conductor filled structure 116 and the top electrode coating 118 117, the protective layer 117 is used to prevent influence of the germanium to follow-up process in the conductor filled structure 116, wherein described The material of protective layer 117 includes boron doped polysilicon.

As an example, also having doped chemical in the conductor filled structure 116, the doped chemical is selected from boron, phosphorus And any one in arsenic；118 surface of top electrode coating is also formed with oxide layer 119.

Specifically, can also the conductor filled structure 116 formation while, be passed through boron source gas, phosphorus source gas with And at least one of arsenic source gas, to advanced optimize the electric property of the conductor filled structure.In addition, further including in institute The step of continuously forming oxide layer after top electrode coating 118 is formed is stated, silicon oxide layer is such as formed, is coated with silica entire Top electrode just starts from BEOL metal interconnection structure.

In conclusion the present invention provides a kind of conductor structure based on polysilicon processing procedure, array of capacitors structure and preparation Method, conductor structure preparation include: to provide a substrate, form cave structure in Yu Suoshu substrate；And in the cave structure It is interior to form conductor filled structure, and the material source for forming the conductor filled structure includes at least silicon source and ge source, wherein it is described Nucleus of the germanium atom as silicon atom aggregation growth in the silicon source in ge source, to increase the silicon in the conductor filled structure Grain size number.Through the above scheme, conductor filled structure of the invention and preparation in, propose manufacture big crystal grain (large Grain size) DOPOS doped polycrystalline silicon mode, introduce as silicon crystal grain aggregation growth nucleus element, such as Germanium, more Germanium atom is mixed in crystal silicon to help polysilicon grain to grow up, and germanium atom can achieve similar silicon wafer core in doped polysilicon Effect, make silicon atom assemble so that increase grain size number, increase polysilicon crystal granularity can reduce crystal boundary trap (grain Boundary trap) influence to carrier (carrier) and then increase conductivity, i.e. reduction grain boundary density promotes electric conductivity. Aforesaid way can be applied to it is various on the conducting wire of polysilicon processing procedure, such as capacitor arrangement, in addition, the present invention also passes through protective layer Setting, to realize the influence for preventing the germanium in conductor filled structure to processing procedure, and reached conductor filled structure and its Effective connection between his structure sheaf, and by the introducing of doped chemical etc., further improve the electricity of conductor filled structure Performance.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.

The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as At all equivalent modifications or change, should be covered by the claims of the present invention.

Claims

1. a kind of preparation method of the conductor structure based on polysilicon processing procedure, which comprises the steps of:

1) substrate is provided, forms cave structure in Yu Suoshu substrate；And

2) it is passed through silicon source gas simultaneously and ge source gas is reacted in forming conductor filled structure in the cave structure, instead Answering temperature is 380 DEG C~420 DEG C, and the silicon source gas is selected from SiH₄、Si₂H₆And SiH₆At least one of Cl, the ge source gas Body is selected from GeH4 and Ge₂H₆At least one of, wherein the germanium atom in the ge source is assembled as silicon atom in the silicon source The nucleus of growth, to increase silicon grain size number in the conductor filled structure formed, the silicon grain size number is 500~1000 Angstrom；The conductor filled structure includes filling perforation conductive layer and gap storehouse, the gap storehouse by the filling perforation conductive layer polysilicon Between gap constitute, and the filling perforation conductive layer coats the gap storehouse, the weight hundred of the germanium in the conductor filled structure Divide ratio between 40%~60%.

2. the preparation method of the conductor structure according to claim 1 based on polysilicon processing procedure, which is characterized in that described to fill out Hole conductive layer is filled in the cave structure and also extends over the upper surface of the substrate around the cave structure, institute Gap position in storehouse is stated in the filling perforation conductive layer as defined by the cave structure.

3. the preparation method of the conductor structure according to claim 2 based on polysilicon processing procedure, which is characterized in that described to fill out Hole conductive layer is located at the thickness of the upper surface of substrate part between 120~800 angstroms.

4. the preparation method of the conductor structure according to claim 1 based on polysilicon processing procedure, which is characterized in that described to fill out The upper surface that hole conductive layer corresponds to gap silo roof end has the high point formed by polycrystalline and low spot, and the height Point is higher by 80~300 angstroms of the low spot.

5. the preparation method of the conductor structure according to claim 1 based on polysilicon processing procedure, which is characterized in that step 2) In, silicon grain size number is between 50~1500 angstroms in the conductor filled structure.

6. the preparation method of the conductor structure according to claim 1 based on polysilicon processing procedure, which is characterized in that form institute The pressure of conductor filled structure is stated between 250~900 millitorrs.

7. a kind of preparation method of capacitor arrangement array, which comprises the steps of:

1) semi-conductive substrate is provided, the semiconductor substrate includes that several are located at the capacitance contact section in memory array structure Point, and in forming the sacrificial layer and supporting layer being alternately superimposed in the semiconductor substrate；

2) in the Patterned masking layer for forming the window with array arrangement in the structure that step 1) obtains, and based on the figure Change mask layer and etch the sacrificial layer and the supporting layer, to form capacitor corresponding with window hole, the capacitor hole is aobvious Reveal the capacitance contact node；

3) bottom in Yu Suoshu capacitor hole and side wall form lower electrode layer, and remove the sacrificial layer, to appear the lower electrode The outer surface of layer；

4) inner surface of Yu Suoshu lower electrode layer and the outer surface appeared form capacitor dielectric layer, and in the capacitor dielectric layer Surface formed upper electrode layer；

5) it is passed through silicon source gas simultaneously and ge source gas is reacted and forms conductor filled knot with the surface in the upper electrode layer Structure, the conductor filled structure filling is between the inner wall of the lower electrode layer and between the outer surface of the adjacent lower electrode layer Gap and extend over the upper electrode layer, reaction temperature be 380 DEG C~420 DEG C, the silicon source gas be selected from SiH₄、Si₂H₆ And SiH₆At least one of Cl, the ge source gas are selected from GeH₄And Ge₂H₆At least one of, the germanium in the ge source is former Nucleus of the son as silicon atom aggregation growth in the silicon source, to increase silicon crystal grain in the conductor filled structure formed Degree, the silicon grain size number are 500~1000 angstroms；The conductor filled structure includes filling perforation conductive layer and gap storehouse, between described Gap storehouse is made of the gap between the polysilicon of the filling perforation conductive layer of capacitor hole institute characterizing portion, and the filling perforation is led Electric layer coats the gap storehouse, and the weight percent of the germanium in the conductor filled structure is between 40%~60%；And

8. the preparation method of capacitor arrangement array according to claim 7, which is characterized in that the filling perforation conductive layer Upper surface is higher by 120~800 angstroms compared to the upper surface of the upper electrode layer of the lower electrode layer over top.

9. the preparation method of capacitor arrangement array according to claim 7, which is characterized in that the filling perforation conductive layer pair At least one of both the upper surface at gap silo roof end and the upper surface of the filling perforation conductive layer described in Ying Yu have by more Crystal silicon accumulates the high point to be formed and low spot, and the high point is higher by 80~300 angstroms of the low spot.

10. the preparation method of capacitor arrangement array according to claim 7, which is characterized in that described to lead in step 5) Silicon grain size number is between 50~1500 angstroms in body interstitital texture；Formed the pressure of the conductor filled structure between 250~ Between 900 millitorrs.

11. the preparation method of capacitor arrangement array according to claim 7, which is characterized in that in step 1), the branch The quantity for supportting layer is three layers, including top support layer, middle support layer and base layer support layer, and the quantity of the sacrificial layer is two Layer, including the first sacrificial layer and positioned at the base layer support layer positioned at the top support layer and the middle support layer between The second sacrificial layer between the middle support layer；In step 3), the step of removing the sacrificial layer, includes:

The first opening is formed in Yu Suoshu top support layer, 3-1) to expose first sacrificial layer for being located at its lower surface；

The second opening is formed in Yu Suoshu middle support layer, 3-3) to expose second sacrificial layer for being located at its lower surface；

3-4) based on second opening, second sacrificial layer is removed using wet-etching technology.

12. the preparation method of capacitor arrangement array according to claim 11, which is characterized in that step 3-1) in, one A first opening only with a capacitor hole is overlapping or first opening simultaneously with multiple capacitor holes It is overlapping；Step 3-3) in, second opening is only overlapped with a capacitor hole or second opening is same When it is overlapping with multiple capacitor holes.

13. the preparation method of capacitor arrangement array according to claim 7, which is characterized in that in step 5), further include The step of conductor filled structure is doped, any one of doped chemical in boron, phosphorus and arsenic；Step 6) it Afterwards, further include the steps that forming oxide layer in the top electrode cover surface.

14. the preparation method of capacitor arrangement array according to any one of claim 7~13, which is characterized in that It is further comprised the steps of: between step 5) and step 6) and forms a protective layer in the conductor filled body structure surface, it is described protective layer used In preventing influence of the germanium in the conductor filled structure to follow-up process, wherein the material of the protective layer includes boron doping Polysilicon.

15. the preparation method of capacitor arrangement array according to claim 14, which is characterized in that the conductor filled knot Structure is prepared in same reaction chamber with the protective layer；The silicon source gas for forming the protective layer includes SiH₄、Si₂H₆And SiH₆At least one of Cl, the boron source gas for forming the protective layer includes BCl₃And B₂H₆At least one of；Wherein, shape At the temperature of the protective layer between 300~500 DEG C, pressure is between 200~900 millitorrs, the protection of formation The thickness of layer is between 400~1500 angstroms.

16. a kind of conductor structure based on polysilicon processing procedure characterized by comprising

Substrate is formed with cave structure in the substrate；And

Conductor filled structure is located in the cave structure, and the conductor filled structure is by the silicon source gas and germanium that are passed through simultaneously Source gas precursor reactant is formed, and reaction temperature is 380 DEG C~420 DEG C, and the silicon source gas is selected from SiH₄、Si₂H₆And SiH₆In Cl extremely Few one kind, the ge source gas are selected from GeH₄And Ge₂H₆At least one of, wherein described in the germanium atom in the ge source is used as The nucleus of silicon atom aggregation growth in silicon source, to increase silicon grain size number in the conductor filled structure, the silicon grain size number It is 500~1000 angstroms；The conductor filled structure includes filling perforation conductive layer and gap storehouse, and the gap storehouse is conductive by the filling perforation Gap between the polysilicon of layer is constituted, and the filling perforation conductive layer cladding gap storehouse, in the conductor filled structure The weight percent of germanium is between 40%~60%.

17. the conductor structure according to claim 16 based on polysilicon processing procedure, which is characterized in that the filling perforation conductive layer It is filled in the cave structure and also extends over the upper surface of the substrate around the cave structure, the gap storehouse In the filling perforation conductive layer as defined by the cave structure；The filling perforation conductive layer is located at the upper surface of substrate portion The thickness divided is between 120~800 angstroms.

18. the conductor structure according to claim 16 based on polysilicon processing procedure, which is characterized in that the conductor filled knot Also there is doped chemical, any one formation of the doped chemical in boron, phosphorus and arsenic in structure.

19. the conductor structure based on polysilicon processing procedure described in any one of 6~18 according to claim 1, which is characterized in that The filling perforation conductive layer corresponds to the upper surface at gap silo roof end with the high point and low spot formed by polycrystalline, institute It states high point and is higher by 80~300 angstroms of the low spot；Silicon grain size number is between 50~1500 angstroms in the conductor filled structure.

20. a kind of array of capacitors structure characterized by comprising

Conductor filled structure is filled between the inner wall of the lower electrode layer and between the outer surface of the adjacent lower electrode layer Gap simultaneously extends over the upper electrode layer, and the conductor filled structure is by the silicon source gas being passed through simultaneously and ge source gas reaction It is formed, reaction temperature is 380 DEG C~420 DEG C, and the silicon source gas is selected from SiH₄、Si₂H₆And SiH₆At least one of Cl, institute It states ge source gas and is selected from GeH₄And Ge₂H₆At least one of, the germanium atom in the ge source is used for former as silicon in the silicon source The nucleus of son aggregation growth, to increase silicon grain size number in the conductor filled structure, the silicon grain size number is 500~1000 Angstrom；The conductor filled structure includes filling perforation conductive layer and gap storehouse, and the gap storehouse is by capacitor hole institute characterizing portion Gap between the polysilicon of the filling perforation conductive layer is constituted, and the filling perforation conductive layer coats the gap storehouse, the conductor The weight percent of germanium in interstitital texture is between 40%~60%；And

21. array of capacitors structure according to claim 20, which is characterized in that the upper surface phase of the filling perforation conductive layer Upper surface compared with the upper electrode layer of the lower electrode layer over top is higher by 120~800 angstroms；The filling perforation conductive layer pair At least one of both the upper surface at gap silo roof end and the upper surface of the filling perforation conductive layer described in Ying Yu have by more Crystal silicon accumulates the high point to be formed and low spot, and the high point is higher by 80~300 angstroms of the low spot.

22. array of capacitors structure according to claim 20, which is characterized in that the silicon of the conductor filled structure crystallizes Granularity is between 50~1500 angstroms.

23. array of capacitors structure according to claim 20, which is characterized in that also have in the conductor filled structure Doped chemical, any one of the doped chemical in boron, phosphorus and arsenic；The top electrode cover surface is also formed with oxygen Change layer.

24. the array of capacitors structure according to any one of claim 20~23, which is characterized in that the conductor is filled out It fills between structure and the top electrode coating and is also formed with protective layer, it is described protective layer used in preventing the conductor filled structure In influence of the germanium to follow-up process, wherein the material of the protective layer includes boron doped polysilicon.