CN107301976A - Semiconductor memory and its manufacture method - Google Patents
Semiconductor memory and its manufacture method Download PDFInfo
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- CN107301976A CN107301976A CN201710613385.2A CN201710613385A CN107301976A CN 107301976 A CN107301976 A CN 107301976A CN 201710613385 A CN201710613385 A CN 201710613385A CN 107301976 A CN107301976 A CN 107301976A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000003990 capacitor Substances 0.000 claims abstract description 102
- 238000003491 array Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims description 27
- 125000006850 spacer group Chemical group 0.000 claims description 26
- 239000011368 organic material Substances 0.000 claims description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 238000003475 lamination Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 150000004767 nitrides Chemical class 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 229910017107 AlOx Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 4
- 229910019897 RuOx Inorganic materials 0.000 claims description 4
- 229910018316 SbOx Inorganic materials 0.000 claims description 4
- 229910003134 ZrOx Inorganic materials 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 239000011574 phosphorus Substances 0.000 claims description 4
- 238000005452 bending Methods 0.000 claims description 3
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 8
- 238000000059 patterning Methods 0.000 abstract description 3
- 238000005728 strengthening Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 237
- 229910021341 titanium silicide Inorganic materials 0.000 description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 7
- 230000007797 corrosion Effects 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000003860 storage Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 2
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- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
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- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
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- 229910052731 fluorine Inorganic materials 0.000 description 1
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- 229910052739 hydrogen Inorganic materials 0.000 description 1
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- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of semiconductor memory and its manufacture method, including：Outside Semiconductor substrate, the first pad being formed with multiple memory array structures and memory array structure and positioned at some second pads of the first pad periphery；Double sided capacitor array, is formed on first pad, and the double sided capacitor includes double-U-shaped the first conductive layer and the second conductive layer, capacitor dielectric and the 3rd conductive layer；And rack tube, it is formed on second pad, the rack tube includes the dummy hole without electrical functionality.The present invention is produced the double sided capacitor of the double-U-shaped bottom electrode of six square arrays arrangement, with larger height to width ratio, can be effectively improved the capacitance under unit area with multiple patterning method and the support frame structure of border process strengthening.
Description
Technical field
The invention belongs to semiconductor devices and manufacture field, more particularly to a kind of semiconductor memory and its manufacturer
Method.
Background technology
Dynamic RAM (Dynamic Random Access Memory, referred to as：DRAM) commonly used in computer
Semiconductor storage unit, be made up of the memory cell of many repetitions.Each memory cell generally includes capacitor 10 and crystal
Pipe 11；The grid of transistor 11 is connected with wordline 13, drain be connected with bit line 12, source electrode is connected with capacitor 10；In wordline 13
Voltage signal be capable of opening or closing for controlling transistor 11, and then the number being stored in capacitor 10 is read by bit line 12
It is believed that breath, or data message is written in capacitor 10 by bit line 12 stored, as shown in Figure 1.
Capacitor in existing dynamic RAM is generally one side capacitor arrangement, is seriously limited in unit area
The raising of capacitance.
In addition, processing of the existing capacitor array to limit generally uses the masking layer 20 of rectangular window 22, such as Fig. 2 institutes
Show, if the masking layer of this rectangular window would generally be passed through from the position of the dry condenser 21 positioned at limit, so as to cause these
If the excalation of the dry condenser positioned at limit, greatly reduces the overall performance of array of capacitors, and have impact on follow-up
Capacitor and other chips enter row metal be connected and package application stability.
In view of the above there is provided it is a kind of with good mechanically stable structure and can effectively improve capacitor with it is other
The semiconductor memory and its manufacture method that chip enters the stability of row metal connection and package application are necessary.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of semiconductor memory and its system
Method is made, to realize that a kind of dual U-shaped bottom electrode has good mechanically stable structure and can effectively improve capacitor and other cores
Piece enters the semiconductor memory and its manufacture method of the stability of row metal connection and package application.
In order to achieve the above objects and other related objects, the present invention provides a kind of manufacture method of semiconductor memory, bag
Include：1) provide and multiple the first pads in internal memory structure of arrays and exclusion are formed with semi-conductive substrate, the substrate
Outside the memory array structure and positioned at some second pads of the first pad periphery；2) in formation on the substrate
Alternately laminated dielectric layer and supporting layer；3) in forming the first mask and the second mask on the dielectric layer, described first covers
Film is used to etch the dielectric layer to form electric capacity hole corresponding with first pad and corresponding with second pad
Dummy hole, second mask is used to sheltering outer peripheral areas outside the electric capacity hole and the dummy hole, and described the
Spacing bending is preset along apart from the one of hithermost electric capacity hole or dummy hole in the edge of two masks；4) it is based on first mask
And second mask is etched in the dielectric layer until the electric capacity hole of first pad and until second pad
Dummy hole；5) in the electric capacity hole Inner and dummy hole Inner first conductive layers of formation and the second conductive layer；6) form multiple
The part dielectric layer and the part sacrificial spacer layer in opening, the opening exposure electric capacity hole, is opened by described
Mouth carries out wet etching and removes the dielectric layer and the sacrificial spacer layer, dummy hole described in the opening relative depature；And 7)
Corresponding to the electric capacity hole site, form covering first conductive layer and the second conductive layer inner surface and the electric capacity of outer surface is situated between
Matter, and the 3rd conductive layer for covering the capacitor dielectric outer surface is formed, double sided capacitor is prepared by the electric capacity hole site,
The rack tube for connecting the supporting layer is prepared by the dummy hole site.
Preferably, step 5) in, prior to first conductive layer surface formation sacrificial spacer layer, then by between the sacrifice
Interlayer is etched back within the electric capacity hole, and in the sacrificial spacer layer and dielectric layer surface the second conductive layer of formation, described the
Two conductive layers and first conductive layer formation closing structure；Step 6) in, the part in the opening exposure electric capacity hole
The dielectric layer and the part sacrificial spacer layer, carry out wet etching by the opening and remove the dielectric layer and described sacrificial
Domestic animal wall.
Preferably, the material of the dielectric layer includes adulterating in one of silica and silicon oxynitride, the dielectric layer
There are one of boron and phosphorus, the material of the supporting layer includes constituting group wherein in silicon nitride, silicon oxynitride, aluminum oxide
One of；The corrosive liquid that the wet etching is used includes one of hydrofluoric acid solution and hydrofluoric acid ammonia spirit.
Preferably, step 7) in, an opening is only overlapping with an electric capacity hole, or an opening is same
When with multiple electric capacity holes overlap.
Preferably, step 3) include：3-1) in sequentially forming polysilicon layer, the first dielectric film layer, on the dielectric layer
One organic material layer and the first sub- mask layer；3-2) in sequentially formed on the described first sub- mask layer the second organic material layer,
Second dielectric film and the second sub- mask layer, wherein, the first window of the first sub- mask layer and the second sub- mask layer
Second window stacked arrays are to form electric capacity hole window, and angle between the first window and the second window is 55~65 °
Or 115~125 °, the polysilicon layer, the first dielectric film layer, the first organic material layer, the first sub- mask layer, second organic material
The bed of material, the second dielectric film and the second sub- mask layer collectively constitute first mask；And 3-3) in the described second sub- mask
It is upper to form second mask, and the default spacing causes step 4) etch positioned at the electric capacity hole of edge area and dummy
The pattern in hole and the consistent appearance in internally positioned electric capacity hole.
Preferably, the default spacing is 30%~80% of spacing between electric capacity hole described in adjacent two, the electric capacity
The depth-to-width ratio in hole and the dummy hole is 5~20, and the altitude range of the double sided capacitor is 0.5~5 μm.
Preferably, the cross sectional shape of first conductive layer is the first U-shape structure, the major section of second conductive layer
Be shaped as the second U-shape structure, second U-shape structure is located on the inside of first U-shape structure, and second U-shape structure with
First U-shape structure has interval, and second conductive layer separately has the connection extended by the top of second U-shape structure
Portion, to be connected to form closing structure with first U-shape structure.
Preferably, in step 6) in, the connection of second conductive layer is covered to provide the dielectric film of the opening
Portion.
Preferably, the double sided capacitor is arranged with the dummy Kong Chengliu square arrays, and the dummy hole shuffling exists
The neighboring area of the double sided capacitor.
Preferably, in addition to step 9), in forming Top electrode in the electric capacity hole, the Top electrode is not formed at the void
Put in hole, the dummy hole is closed as gasbag chamber, as excluding the branch without electrical functionality outside the memory array structure
Frame cylinder.
The present invention also provides a kind of semiconductor memory, including：Be formed with Semiconductor substrate, the substrate it is multiple including
Deposit the first pad in structure of arrays and exclude outside the memory array structure and positioned at the first pad periphery
Some second pads；Double sided capacitor array, is formed on first pad, the double sided capacitor includes：First is conductive
Layer and the second conductive layer, first conductive layer and first contact pads, the cross sectional shape of first conductive layer are the
One U-shape structure, the cross sectional shape of second conductive layer is the second U-shape structure, and second U-shape structure is located at the first U
On the inside of type structure；Capacitor dielectric, is covered in first conductive layer and the second conductive layer inner surface and outer surface；And the 3rd is conductive
Layer, is covered in the capacitor dielectric outer surface；And rack tube, it is formed on second pad, the rack tube includes dummy
Hole and it is connected to the conductive layer of second pad in the U-shaped section and bottom of the dummy hole Inner.
Preferably, the ratio of the height and the width of the double sided capacitor is 5~20, the altitude range of the double sided capacitor
For 0.5~5 μm.
Preferably, the material of first conductive layer, second conductive layer and the 3rd conductive layer includes metal nitrogen
The compound that one or both of compound and metal silicide are formed；The capacitor dielectric include ZrOx, HfOx,
One kind or above-mentioned material in ZrTiOx, RuOx, SbOx, AlOx constitute two or more the formed laminations in group.
Preferably, the double sided capacitor is arranged with the rack tube in six square arrays, and the rack tube shuffling exists
The neighboring area of the double sided capacitor.
Preferably, in addition to the Top electrode that is formed on double sided capacitor array, wherein, be hollow shape in the rack tube
State, the Top electrode does not insert the dummy hole Inner.
Preferably, the dummy hole is closed as gasbag chamber without electrical functionality.
Preferably, the rack tube is additionally included in the sacrifice interval between first conductive layer and second conductive layer
Layer.
Preferably, second U-shape structure has interval with first U-shape structure, and second conductive layer separately has
The connecting portion extended by the top of second U-shape structure, to be connected to form closing structure, and institute with first U-shape structure
Stating has breach in closing structure.
Preferably, the connecting portion of second conductive layer is covered to provide the dielectric film of the breach.
As described above, the semiconductor memory and its manufacture method of the present invention, have the advantages that：
1) present invention manufactures the double sided capacitor of six square arrays arrangement with multiple patterning method, and the capacitor has larger
Height to width ratio, can effectively improve the capacitance under unit area, improve the storage capacity of semiconductor memory；
2) double sided capacitor of the invention has the first conductive layer and the second conductive layer of double-U-shaped cross section structure as lower pole
Plate, can greatly increase the capacitance under unit area；
3) support frame structure of the invention by border process strengthening, and in support of the edge area formation without electrical functionality
Cylinder so that capacitor framework has higher mechanical strength, is not easy to electric capacity acid tank technique with being produced in plasma etching process
Defect, can produce low defect and with rock-steady structure capacitor, and it is had stronger in follow-up cmp
Marginal structure；
4) mask pattern of the invention by designing edge area, can obtain the good marginal capacitor arrangement of pattern,
Improve the overall performance of array of capacitors.
Brief description of the drawings
Fig. 1 is shown as the structural representation of dynamic RAM.
The Rotating fields of sheltering that Fig. 2 is shown as the rectangular window that processing of the capacitor array of the prior art to limit is used show
It is intended to.
Fig. 3 a~Figure 23 is shown as the structural representation that each step of manufacture method of the semiconductor memory of the present invention is presented
Figure.
Component label instructions
10 capacitors
11 transistors
12 bit lines
13 wordline
20 masking layers
21 capacitors
22 rectangular windows
30 double sided capacitors
101 Semiconductor substrates
102 walls
103 first pads
104 second pads
105 first mediums layer
106 first supporting layers
107 second dielectric layer
108 second supporting layers
109 polysilicon layers
110 first dielectric film layers
111 first organic material layers
112 first sub- mask layers
113 second organic material layers
114 second dielectric films
114 ' second sub- mask layers
115 second masks
116 electric capacity hole windows
117 electric capacity holes
117 ' dummy holes
118 first conductive layers
119 the 3rd dielectric films
120 the 3rd organic material layers
121 the 4th dielectric films
121 ' photo etched masks
122 openings
123 capacitor dielectrics
124 the 3rd conductive layers
125 Top electrodes
126 sacrificial spacer layers
127 second conductive layers
128 gasbag chambers
129 connecting portions
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 3 a~Figure 23.It should be noted that the diagram provided in the present embodiment only illustrates in a schematic way
The basic conception of the present invention, only display is with relevant component in the present invention rather than according to package count during actual implement in illustrating then
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
As shown in Fig. 3 a~Figure 23, the present embodiment provides a kind of manufacture method of semiconductor memory, the manufacture method
Including：
As shown in Fig. 3 a~Fig. 3 b, step 1 is carried out first) there is provided semi-conductive substrate 101, the Semiconductor substrate 101
In be formed with memory array structure, the memory array structure include multiple first pads 103 and exclude in the internal memory
Outside structure of arrays and positioned at some second pads 104 of the multiple periphery of first pad 103.
The memory array structure also includes transistor character line (Word line) and bit line (Bitline), described
One pad 103 and the second pad 104 are electrically connected with the transistor source in the memory array structure.
First pad 103 is arranged in six square arrays, and the arrangement of the double sided capacitor 30 with subsequently making is corresponding.
Carried out between first pad 103, and between the first pad 103 and the second pad 104 by wall 102
Isolation, the material of the wall 102 can be silicon nitride (SiN), silica (SiO2), aluminum oxide (Al2O3) in it is any one
Plant or any two or more combination, in the present embodiment, the material selection of the wall 102 is SiN.Wherein, Fig. 3 a show
The planar graph of the pad 104 of the first pad 103 and second is shown as, Fig. 3 b are shown as the sectional view at A-A ' places in Fig. 3 a.
As shown in figure 4, then carrying out step 2), in formed in the Semiconductor substrate 101 alternately laminated dielectric layer and
Supporting layer.
As an example, using atom layer deposition process (Atomic Layer Deposition) or plasma vapor deposition
Technique (Chemical Vapor Deposition) the formation dielectric layer and supporting layer, the electricity of the dielectric layer and supporting layer
Resistance rate is from 2 × 10^11 (Ω m) to 1 × 10^25 (Ω m), and integral thickness is chosen as between 3 nanometers to 500 nanometers.
As an example, the material of the dielectric layer includes silica or silicon oxynitride, in the dielectric layer doped with boron or
Phosphorus, the material of the supporting layer includes any one or any two or more groups in silicon nitride, silicon oxynitride, aluminum oxide
Close.The material of the dielectric layer is different from the material of the supporting layer, and both corrosion rates are different in same corrosive liquid,
It is embodied in same corrosive liquid, the corrosion rate of the dielectric layer is far longer than the corrosion rate of the supporting layer, makes
When the proper dielectric layer is completely removed, the supporting layer is almost fully retained.In the present embodiment, the dielectric layer
Material is SiO2, and the material of the supporting layer is SiN, and the corrosive liquid that the wet etching is used includes hydrofluoric acid solution and hydrogen fluorine
One of sour ammonia spirit.
The quantity of the dielectric layer and supporting layer can be set according to the height required for follow-up double sided capacitor 30
Fixed, its quantity being laminated can be for 1~10 time or more, wherein, it is advisable with 2~5 times.In the present embodiment, described half
The 105, first supporting layer 106 of first medium layer, the supporting layer of second dielectric layer 107 and second are sequentially formed on conductor substrate 101
108。
The first medium layer 105 and second dielectric layer 107 can be removed during subsequent technique, and described first
Supportting the supporting layer 108 of layer 106 and second is used for the first medium layer 105 and the quilt of second dielectric layer 107 during subsequent technique
As support frame after removal, due to embodiment adds the support frame, can not only greatly improve follow-up making electricity
The mechanical strength of structure during container, can more avoid the destruction caused during subsequent technique (such as grinding) to capacitor.
In the present embodiment, doped with boron or phosphorus in first medium layer 105 and second dielectric layer 107, it is ensured that
The uniformity of critical size, and improve the removal rate of the first medium layer 105 and second dielectric layer 107.
As shown in Fig. 5~Fig. 8, step 3 is then carried out), in forming the first mask and the second mask on the dielectric layer
115, first mask be used for etch the dielectric layer with formed electric capacity hole 117 corresponding with first pad 103 and
Dummy hole 117 ' corresponding with second pad 104, second mask 115 is used to shelter positioned at the electric capacity hole of edge area
117 and dummy hole 117 ' outside outer peripheral areas, and second mask 115 edge along apart from hithermost electric capacity hole
The default spacing a bendings of the one of 117 or dummy holes 117 '.
As an example, step 3) include：
As shown in figure 5, carrying out step 3-1 first), in sequentially forming polysilicon layer 109, the first dielectric on the dielectric layer
Film layer 110, the first organic material layer 111 and the first sub- mask layer 112.
As an example, the material of first dielectric film layer 110 and most first sub- mask layers 112 includes silica or nitrogen
One kind in silica.
As Figure 6-Figure 8, step 3-2 is then carried out), have in sequentially forming second on the described first sub- mask layer 112
Machine material layer 113, the second dielectric film 114 and the second sub- mask layer 114 ', wherein, the of the first sub- mask layer 112
Second window stacked arrays of one window and the second sub- mask layer 114 ' are to form electric capacity hole window 116, and the first window
Angle between the second window is 55~65 ° or 115~125 °, the polysilicon layer 109, the first dielectric film layer 110, first
Organic material layer 111, the first sub- mask layer 112, the second organic material layer 113, the second dielectric film 114 and the second sub- mask
Layer 114 ' collectively constitutes first mask.
As an example, the material of first dielectric film and the second sub- mask layer 114 ' includes silica or silicon oxynitride
In one kind.
Angle between the first window and the second window is 55~65 ° or 115~125 °, can be conducive to follow-up acquisition
The electric capacity hole of six square arrays arrangement.
The first window and the second window stacked arrays into electric capacity hole window 116, its flat shape is parallel
Quadrangle a, it is however preferred to have interior angle is 60 ° of rhombus, it is act as when being etched downwards from electric capacity hole window 116,
Because first mask is by polysilicon layer 109, the first dielectric film layer 110, the first organic material layer 111, the first sub- mask layer
112 second organic material layers 113, the second dielectric film 114 and the second sub- mask layer 114 ' are collectively constituted, and it is in etching process
It is middle to gradually form a circle or approximate circle etching window, therefore, the electric capacity hole that finally etches and dummy hole it is flat
Face is shaped as circular or approximate circle.
As an example, the material of the organic material layer 113 of the first organic material layer 111 and second is carbon or polymer.
As shown in Fig. 7~Fig. 8, step 3-3 is finally carried out), in forming the second mask on the described second sub- mask 114 '
115, the window area of second mask 115 is used for the region for defining array of capacitors, and second mask 115 is used to shelter
Outer peripheral areas positioned at the electric capacity hole 117 of edge area and dummy hole 117 ', and the edge of second mask 115 near
Electric capacity hole 117 or dummy hole 117 ' between there is a default spacing a so that subsequent step 4) etch be located at edge area
Electric capacity hole 117 and dummy hole 117 ' pattern and the consistent appearance in internally positioned electric capacity hole 117, first ultimately formed cover
The schematic diagram of film and the second mask 115 is as shown in Figure 8.
As an example, second mask 115 can select the lamination being made up of photoresist or photoresist and hard mask.
One specific example of second mask 115 as shown in figure 8, it is in the arc shaped that multistage is connected that it, which specifically shows as border,
The pattern positioned at the electric capacity hole 117 of edge area and dummy hole 117 ' and internally positioned electric capacity hole 117 with maximum guarantee
Consistent appearance.
As an example, the default spacing a is 30%~80% of spacing b between electric capacity hole 117 described in adjacent two, it is excellent
Selection of land, the default spacing a is 40%~60% of spacing b between electric capacity hole 117 described in adjacent two, and this spacing can be protected
The electric capacity hole of card edge area can obtain complete pattern, and other electric capacity holes of marginal periphery or other functions can be protected again
Region will not because of etching technics and caused by defect.
As shown in figure 9, then carrying out step 4), based on first mask and the second mask 115 in the dielectric layer
Etch until the electric capacity hole 117 of first pad 103 and until the dummy hole 117 ' of second pad 104.
Specifically, when from electric capacity hole window 116 downwards etch when, due to first mask by polysilicon layer 109,
First dielectric film layer 110, the first organic material layer 111, the first sub- organic material layer 113 of mask layer 112 second, the second dielectric are thin
The sub- mask layer 114 ' of film 114 and second is collectively constituted, and it can gradually form a circle or approximate circle in etching process
Etching window, therefore, the electric capacity hole 117 finally etched and the flat shape in dummy hole 117 ' are circular or approximate circle.
As an example, the depth-to-width ratio in the electric capacity hole 117 and dummy hole 117 ' is 5~20, preferably 6~10.This reality
Stepped construction of the example by the first mask of design is applied, the electric capacity hole 117 and dummy hole 117 ' of larger depth-to-width ratio can be obtained, so that
The capacitance of unit area is greatly improved, the integrated level and performance of memory device is improved.Specifically, in the present embodiment, it is described
The depth in electric capacity hole 117 and dummy hole 117 ' is 0.5~5 μm.
As shown in Figure 10~Figure 12, wherein, Figure 11~Figure 14 only shows the structural diagrams in an electric capacity hole 117, then enters
Row step 5), the first conductive layer 118 is formed in the electric capacity hole 117 and the dummy surface of hole 117 ', and lead in described first
The first conductive layer 118 that the surface of electric layer 118 is formed in sacrificial spacer layer 126, the electric capacity hole 117 is used as follow-up double sided capacitor
30 first electrode plate.
As an example, using atom layer deposition process (Atomic Layer Deposition) or plasma vapor deposition
Technique (Chemical Vapor Deposition) is in the electric capacity hole 117, the dummy hole 117 ' and the dielectric layer surface
Depositing first conductive layer 118, first conductive layer 118 includes one or both of metal nitride and metal silicide institute
The compound of formation, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide
(Titanium Silicide), silicon titanium nitride (TiSixNy), the resistivity of first conductive layer 118 is 2 × 10^-8 (Ω
M) between 1 × 10^2 (Ω m).
As shown in Figure 13~Figure 14, then carry out step 6), by the sacrificial spacer layer 126 be etched back to the electric capacity hole with
It is interior, and in the sacrificial spacer layer and dielectric layer surface the second conductive layer 127 of formation, second conductive layer 127 and described the
One conductive layer 118 formation closing structure.
As an example, the top surface of the sacrificial spacer layer 126 after eatch-back is inclined plane, in favor of the shape of follow-up second conductive layer
Into being more beneficial for the formation of subsequent capacitance medium and the 3rd conductive layer.
As an example, using atom layer deposition process (Atomic Layer Deposition) or plasma vapor deposition
Technique (Chemical Vapor Deposition) is led in the sacrificial spacer layer 126 and dielectric layer surface deposition second
Electric layer 127, second conductive layer 127 includes the chemical combination that one or both of metal nitride and metal silicide are formed
Thing, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide (Titanium
Silicide), silicon titanium nitride (TiSixNy), the resistivity of first conductive layer 118 is 2 × 10^-8 (Ω m) to 1 × 10^2
Between (Ω m).
As an example, the cross sectional shape of first conductive layer 118 is the first U-shape structure, second conductive layer 127
Cross sectional shape is the second U-shape structure, and second U-shape structure is located on the inside of first U-shape structure, and the described second U-shaped knot
Structure has interval with first U-shape structure, described to be spaced for forming cavity after sacrificial spacer layer is removed, for making
Follow-up capacitor dielectric 123, the 3rd conductive layer 124 and Top electrode 125, second conductive layer separately has by the 2nd U
The connecting portion 129 of the top extension of type structure, to be connected to form closing structure with first U-shape structure.
As shown in Figure 15 a~Figure 18, step 7 is then carried out), multiple openings 122 are formed, the opening 122 at least exposes
The 117 part dielectric layer and the part sacrificial spacer layer 126 in the electric capacity hole, are carried out wet by the opening 122
Dielectric layer described in method erosion removal and the sacrificial spacer layer 126, dummy hole 117 ' described in the opening relative depature (do not have
Appear the dummy hole 117 ').
Specifically, step 7) include：
Step 7-1), form the opening 122 of multiple exposure dielectric layers and the part sacrificial spacer layer 126.
As an example, step 7-1) in, an opening 122 is only overlapping with an electric capacity hole 117, or one
Multiple electric capacity holes 117 are overlapped the opening 122 simultaneously.
As an example, Figure 15 b- Figure 15 c are shown as several plane figures of the opening 122.Wherein, show in Figure 15 b
The situation of 1,2,3,4,5 through hole of correspondence of opening 122 is gone out.In the present embodiment, it is preferred to use shown in Figure 15 c
Layout type, the shape of multiple openings 122 is triangle, and each opening 122 is overlapping with 3 electric capacity holes.
In the present embodiment, electric capacity hole only a fraction is overlapped with the opening 122, so as to can be protected around each electric capacity hole
A part of supporting construction is stayed, to ensure the structural stability of the first conductive layer 118 described in subsequent wet corrosion process.
As an example, forming the opening 122 using dry etching, the 3rd dielectric is formed first on the dielectric layer
Film 119, the 3rd organic material layer 120, the 4th dielectric film 121 and photo etched mask 121 ', as shown in fig. 15 a, by described
The etching of photo etched mask 121 ' the 4th dielectric film 121, the 3rd organic material layer 120, the 3rd dielectric film 119, first are led
The supporting layer 108 of electric layer 118 and second, to form the opening 122, as shown in figure 16.
Afterwards, the photo etched mask 121 ', the 4th dielectric film 121 and the 3rd organic material layer 120 are removed, retains described
3rd dielectric film 119, as shown in figure 17.
As an example, step 7-1) in, cover second conduction to provide the 3rd dielectric film 119 of the opening
The connecting portion 129 of layer 127.
Step 7-2), carry out wet etching by the opening 122 and remove the dielectric layer and the sacrificial spacer layer
126。
As an example, the corrosive liquid that the wet etching is used includes hydrofluoric acid solution, the corrosion rate of the dielectric layer
It is far longer than the corrosion rate of the supporting layer, when the dielectric layer is completely removed, the supporting layer is almost protected completely
Stay, as shown in figure 18.
In the present embodiment, the use of sacrificial spacer layer 126 and the dielectric layer identical material, so that the wet method
Corrosion can remove the dielectric layer and the sacrificial spacer layer 126 simultaneously.
As shown in Figure 19~22, wherein, Figure 19~Figure 22 only show the structural diagrams in an electric capacity hole 117, then enter
Row step 8), corresponding to the position of electric capacity hole 117, form table in the covering conductive layer 127 of the first conductive layer 118 and second
The capacitor dielectric 123 of face and outer surface, and the 3rd conductive layer 124 for covering the outer surface of capacitor dielectric 123 is formed, by described
The connection supporting layer is prepared by the position in the dummy hole 117 ' to prepare double sided capacitor 30 in the position of electric capacity hole 117
Rack tube, retained the 3rd dielectric film 119 in the dummy hole 117 ' is blocked, without forming the capacitor dielectric
123 and the 3rd conductive layer 124.
As an example, the altitude range of the double sided capacitor 30 is 0.5~5 μm.The double sided capacitor 30 with it is described
Dummy hole 117 ' is arranged in six square arrays, and the dummy shuffling of hole 117 ' is in the neighboring area of the double sided capacitor 30.
In the present embodiment, the capacitor dielectric 123 is from being high K dielectric, to improve the electric capacity of unit-area capacitance device
Value, its one kind or above-mentioned material included in ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx constitutes two kinds in group
The lamination that the above is formed.
As an example, using atom layer deposition process (Atomic Layer Deposition) or plasma vapor deposition
3rd conductive layer 124 of technique (Chemical Vapor Deposition) the formation covering outer surface of capacitor dielectric 123,
3rd conductive layer 124 includes the compound that one or both of metal nitride and metal silicide are formed, such as nitrogen
Change titanium (Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide (Titanium Silicide), silicon
Titanium nitride (TiSixNy), the resistivity of the 3rd conductive layer 124 is between 2 × 10^-8 (Ω m) to 1 × 10^2 (Ω m).
As shown in FIG. 22 and 23, wherein, Figure 22 be Figure 23 in the single structure of double sided capacitor 30 enlarged diagram, most
Step 9 is carried out afterwards), in forming Top electrode 125 in the electric capacity hole 117, the Top electrode 125 is not formed at the dummy hole
In 117 ', the dummy hole 117 ' is closed as gasbag chamber 128, as excluding outside the memory array structure without electrical work(
The rack tube of energy, to strengthen the stability of the structure of double sided capacitor 30, and makes it have in follow-up cmp
Stronger marginal structure.
As an example, the Top electrode 125 is included in tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon, p-type polysilicon
One kind or above-mentioned material constitute two or more formed laminations in group.
As shown in FIG. 22 and 23, wherein, Figure 22 be Figure 23 in the single structure of double sided capacitor 30 enlarged diagram, this
Embodiment also provides a kind of semiconductor memory, including：It is formed with Semiconductor substrate 101, the Semiconductor substrate 101 multiple
The first pad and exclusion in internal memory structure of arrays is outside the memory array structure and positioned at the multiple first weldering
Some second pads 104 of the periphery of disk 103, the memory array structure also include transistor character line (Word line) and
Bit line (Bitline), the pad 104 of the first pad 103 and second is electrically connected with the transistor in the memory array structure
Source electrode；The array of double sided capacitor 30, is formed on first pad 103, and the double sided capacitor 30 includes：First conductive layer
118 and second conductive layer 127, first conductive layer 118 is contacted with first pad 103, first conductive layer 118
Cross sectional shape is the first U-shape structure, and the cross sectional shape of second conductive layer 127 is the second U-shape structure, the described second U-shaped knot
Structure is located on the inside of first U-shape structure and has interval, first U-shape structure and described the with first U-shape structure
The top of two U-shape structures, which is connected to form in closing structure, the closing structure, has breach；Capacitor dielectric 123, is covered in described
First conductive layer 118 and the inner surface of the second conductive layer 127 and outer surface；And the 3rd conductive layer 124, it is covered in the capacitor dielectric
123 outer surfaces；And rack tube, it is formed on second pad 104, the rack tube includes dummy hole 117 ' and in institute
The U-shaped section and bottom for stating the dummy Inner of hole 117 ' connect the first conductive layer 118 of second pad 104.The two-sided electric capacity
Covered with Top electrode 125 in device 30, wherein, it is hollow morphology in the rack tube, the Top electrode 125 is not inserted described dummy
The Inner of hole 117 ', the dummy hole 117 ' is closed as gasbag chamber 128, as excluding outside the memory array structure without electrically
The rack tube of function.
As an example, the array of double sided capacitor 30 is arranged in six square arrays.The two-sided electricity arranged using six square arrays
Container 30, compared with the capacitor of cubic array arrangement, the area shared by its specific capacitance can be reduced up to 14% or so, significantly
The density of capacitor is improved, the storage capacity of semiconductor memory is improved.
As an example, the ratio of the height and the width of the double sided capacitor 30 is 5~20, preferably 6~10.Pass through design
The ratio of the height and the width of the double sided capacitor 30, can greatly improve the capacitance of unit area, improve memory device
Integrated level and performance.
As an example, the altitude range of the double sided capacitor 30 is 0.5~5 μm.
As an example, the material of first conductive layer 118, the second conductive layer 127 and the 3rd conductive layer 124 includes metal
The compound that one or both of nitride and metal silicide are formed；The capacitor dielectric 123 include ZrOx, HfOx,
One kind or above-mentioned material in ZrTiOx, RuOx, SbOx, AlOx constitute two or more the formed laminations in group；Institute
Stating Top electrode 125 includes one kind in tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon, p-type polysilicon or above-mentioned material institute
Constitute two or more the formed laminations in group.
As an example, the double sided capacitor 30 is arranged with the rack tube in six square arrays, and the rack tube is mixed
It is organized in the neighboring area of the double sided capacitor 30.
As an example, also include the Top electrode 125 being formed on the array of double sided capacitor 30, wherein, in the rack tube
For hollow morphology, the Top electrode 125 does not insert the dummy Inner of hole 117 '.
As an example, the dummy hole 117 ' is closed as gasbag chamber 128, as exclude the memory array structure it
The outer rack tube without electrical functionality.
As an example, the rack tube is additionally included between first conductive layer 118 and second conductive layer 127
Sacrificial spacer layer 126.
As an example, second U-shape structure has interval with first U-shape structure, second conductive layer 127 is another
With the connecting portion 129 extended by the top of second U-shape structure, to be connected to form closure knot with first U-shape structure
There is breach in structure, and the closing structure.
As an example, covering the connection of 119 lids, second conductive layer 127 to provide the dielectric film of the breach
Portion 129.
The semiconductor memory (dynamic random access memory) of the present embodiment has the structure of double sided capacitor 30, and described
The structure of double sided capacitor 30 has larger height to width ratio, and the capacitance of its unit area can exceed common one side capacitor
More than 2 times, can realize bigger capacitance on identical memory cell area, improve the storage energy of semiconductor memory
Power.Further, the first conductive layer and the second conductive layer that the double sided capacitor 30 has double-U-shaped cross section structure are used as lower pole
Plate, can greatly increase the capacitance under unit area.
As described above, the semiconductor memory and its manufacture method of the present invention, have the advantages that：
1) present invention with multiple patterning method manufacture six square arrays arrangement double sided capacitor 30, the capacitor have compared with
Big height to width ratio, can effectively improve the capacitance under unit area, improve the storage capacity of semiconductor memory；
2) double sided capacitor 30 of the invention has the first conductive layer and the second conductive layer of double-U-shaped cross section structure under
Pole plate, can greatly increase the capacitance under unit area；
3) support frame structure of the invention by border process strengthening, and in support of the edge area formation without electrical functionality
Cylinder so that capacitor framework has higher mechanical strength, is not easy to electric capacity acid tank technique with being produced in plasma etching process
Defect, can produce low defect and with rock-steady structure capacitor, and it is had stronger in follow-up cmp
Marginal structure；
4) mask pattern of the invention by designing edge area, can obtain the good marginal capacitor arrangement of pattern,
Improve the overall performance of array of capacitors.
So, the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (19)
1. a kind of manufacture method of semiconductor memory, it is characterised in that including：
1) provide on semi-conductive substrate, the substrate and be formed with multiple the first pad, Yi Jipai in internal memory structure of arrays
In addition in the memory array structure and positioned at some second pads of the first pad periphery；
2) in forming alternately laminated dielectric layer and supporting layer on the substrate；
3) in forming the first mask and the second mask on the dielectric layer, first mask be used to etching the dielectric layer with
Electric capacity hole corresponding with first pad and dummy hole corresponding with second pad are formed, second mask is used for
The outer peripheral areas outside the electric capacity hole and the dummy hole is sheltered, and the edge of second mask is most leaned on along distance
Near electric capacity hole or the one of dummy hole default spacing bending；
4) electricity until first pad is etched in the dielectric layer based on first mask and second mask
Hold hole and until the dummy hole of second pad；
5) in the electric capacity hole Inner and dummy hole Inner first conductive layers of formation and the second conductive layer；
6) described sacrifice of the part dielectric layer and part formed in multiple openings, the opening exposure electric capacity hole is spaced
Layer, carries out wet etching by the opening and removes the dielectric layer and the sacrificial spacer layer, the opening relative depature institute
State dummy hole；And
7) correspond to the electric capacity hole site, form covering first conductive layer and the second conductive layer inner surface and outer surface
Capacitor dielectric, and the 3rd conductive layer for covering the capacitor dielectric outer surface is formed, prepared by the electric capacity hole site two-sided
Capacitor, the rack tube for connecting the supporting layer is prepared by the dummy hole site.
2. the manufacture method of semiconductor memory according to claim 1, it is characterised in that：Step 5) in, prior to described
The sacrificial spacer layer, is then etched back within the electric capacity hole by the first conductive layer surface formation sacrificial spacer layer, and in institute
Sacrificial spacer layer and dielectric layer surface the second conductive layer of formation are stated, second conductive layer is closed with first conductive layer formation
Structure；Step 6) in, the part dielectric layer and the part sacrificial spacer layer in the opening exposure electric capacity hole, by
Wet etching is carried out by the opening and removes the dielectric layer and the sacrificial spacer layer.
3. the manufacture method of semiconductor memory according to claim 1, it is characterised in that：The material bag of the dielectric layer
Include in one of silica and silicon oxynitride, the dielectric layer doped with one of boron and phosphorus, the material of the supporting layer
Including constituting one of group in silicon nitride, silicon oxynitride, aluminum oxide；The corrosive liquid that the wet etching is used includes
One of hydrofluoric acid solution and hydrofluoric acid ammonia spirit.
4. the manufacture method of semiconductor memory according to claim 1, it is characterised in that：Step 7) in, described in one
Opening is only overlapping with an electric capacity hole, or an opening is simultaneously overlapping with multiple electric capacity holes.
5. the manufacture method of semiconductor memory according to claim 1, it is characterised in that：Step 3) include：
It is 3-1) sub in sequentially forming polysilicon layer, the first dielectric film layer, the first organic material layer and first on the dielectric layer
Mask layer；
3-2) in sequentially forming the second organic material layer, the second dielectric film and the second sub- mask on the described first sub- mask layer
Layer, wherein, the first window of the first sub- mask layer and the second window stacked arrays of the second sub- mask layer are to form electric capacity
Angle between hole window, and the first window and the second window is 55~65 ° or 115~125 °, the polysilicon layer,
One dielectric film layer, the first organic material layer, the first sub- mask layer, the second organic material layer, the second dielectric film and the second son
Mask layer collectively constitutes first mask；And
3-3) in forming second mask on the described second sub- mask, and the default spacing causes step 4) position that etches
Pattern and the consistent appearance in internally positioned electric capacity hole in the electric capacity hole of edge area and dummy hole.
6. the manufacture method of semiconductor memory according to claim 1, it is characterised in that：The default spacing is adjacent
Two described between electric capacity hole spacing 30%~80%, the depth-to-width ratio in the electric capacity hole and the dummy hole is 5~20, institute
The altitude range for stating double sided capacitor is 0.5~5 μm.
7. the manufacture method of semiconductor memory according to claim 1, it is characterised in that：Section of first conductive layer
Face is shaped as the first U-shape structure, and the major section of second conductive layer is shaped as the second U-shape structure, second U-shape structure
On the inside of first U-shape structure, and second U-shape structure has interval with first U-shape structure, and described second leads
Electric layer separately has the connecting portion extended by the top of second U-shape structure, to be connected to form closure with first U-shape structure
Structure.
8. the manufacture method of double sided capacitor according to claim 7, it is characterised in that：In step 6) in, to provide
The dielectric film of the opening covers the connecting portion of second conductive layer.
9. the manufacture method of semiconductor memory according to claim 1, it is characterised in that：The double sided capacitor and institute
Dummy Kong Chengliu square arrays arrangement is stated, and the dummy hole shuffling is in the neighboring area of the double sided capacitor.
10. the manufacture method of the semiconductor memory according to any one of claim 1 to 9, it is characterised in that：Also include step
It is rapid 9), in forming Top electrode in the electric capacity hole, the Top electrode is not formed in the dummy hole, and the dummy hole is closed
For gasbag chamber, as excluding the rack tube without electrical functionality outside the memory array structure.
11. a kind of semiconductor memory, it is characterised in that including：
Multiple the first pads in internal memory structure of arrays are formed with Semiconductor substrate, the substrate and are excluded described interior
Deposit outside structure of arrays and positioned at some second pads of the first pad periphery；
Double sided capacitor array, is formed on first pad, the double sided capacitor includes：First conductive layer and second lead
Electric layer, first conductive layer and first contact pads, the cross sectional shape of first conductive layer is the first U-shape structure,
The cross sectional shape of second conductive layer is the second U-shape structure, and second U-shape structure is located on the inside of first U-shape structure；
Capacitor dielectric, is covered in first conductive layer and the second conductive layer inner surface and outer surface；And the 3rd conductive layer, it is covered in institute
State capacitor dielectric outer surface；And
Rack tube, is formed on second pad, and the rack tube includes dummy hole and U-shaped section in the dummy hole Inner
Face and bottom are connected to the conductive layer of second pad.
12. semiconductor memory according to claim 11, it is characterised in that：The height and the width of the double sided capacitor
Ratio be 5~20, the altitude range of the double sided capacitor is 0.5~5 μm.
13. semiconductor memory according to claim 11, it is characterised in that：First conductive layer, described second are led
The material of electric layer and the 3rd conductive layer includes the change that one or both of metal nitride and metal silicide are formed
Compound；One kind or above-mentioned material that the capacitor dielectric is included in ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx are constituted
Two or more formed laminations in group.
14. semiconductor memory according to claim 11, it is characterised in that：The double sided capacitor and the rack tube
Arranged in six square arrays, and the rack tube shuffling is in the neighboring area of the double sided capacitor.
15. semiconductor memory according to claim 11, it is characterised in that：Also include being formed at double sided capacitor array
On Top electrode, wherein, be hollow morphology in the rack tube, the Top electrode does not insert the dummy hole Inner.
16. semiconductor memory according to claim 15, it is characterised in that：The dummy hole is closed as gasbag chamber
Without electrical functionality.
17. semiconductor memory according to claim 11, it is characterised in that：The rack tube is additionally included in described first
Sacrificial spacer layer between conductive layer and second conductive layer.
18. the semiconductor memory according to any one of claim 11 to 17, it is characterised in that：Second U-shape structure
There is interval with first U-shape structure, second conductive layer separately has the company extended by the top of second U-shape structure
Socket part, has breach to be connected to form with first U-shape structure in closing structure, and the closing structure.
19. semiconductor memory according to claim 18, it is characterised in that：Dielectric film to provide the breach
Cover the connecting portion of second conductive layer.
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| US11784216B2 (en) | 2020-09-10 | 2023-10-10 | Changxin Memory Technologies, Inc. | Manufacturing method of capacitive structure, and capacitor |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6436787B1 (en) * | 2001-07-26 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Method of forming crown-type MIM capacitor integrated with the CU damascene process |
| CN1610122A (en) * | 2003-10-20 | 2005-04-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and producing method thereof |
| CN1773710A (en) * | 2004-11-10 | 2006-05-17 | 茂德科技股份有限公司 | Stacked capacitor and producing method thereof |
| US20060192239A1 (en) * | 2003-08-29 | 2006-08-31 | Patraw Robert D | Permeable capacitor electrode |
-
2017
- 2017-07-25 CN CN201710613385.2A patent/CN107301976B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6436787B1 (en) * | 2001-07-26 | 2002-08-20 | Taiwan Semiconductor Manufacturing Company | Method of forming crown-type MIM capacitor integrated with the CU damascene process |
| US20060192239A1 (en) * | 2003-08-29 | 2006-08-31 | Patraw Robert D | Permeable capacitor electrode |
| CN1610122A (en) * | 2003-10-20 | 2005-04-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and producing method thereof |
| CN1773710A (en) * | 2004-11-10 | 2006-05-17 | 茂德科技股份有限公司 | Stacked capacitor and producing method thereof |
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