CN207353241U - A kind of semiconductor devices anti-fuse structures - Google Patents
A kind of semiconductor devices anti-fuse structures Download PDFInfo
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- CN207353241U CN207353241U CN201721427568.7U CN201721427568U CN207353241U CN 207353241 U CN207353241 U CN 207353241U CN 201721427568 U CN201721427568 U CN 201721427568U CN 207353241 U CN207353241 U CN 207353241U
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- contact hole
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- area
- groove structure
- antifuse
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 105
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims description 45
- 238000011049 filling Methods 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910052697 platinum Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
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- 239000010937 tungsten Substances 0.000 claims description 5
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 4
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- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The utility model provides a kind of semiconductor devices anti-fuse structures, and preparation includes：Semi-conductive substrate is provided, there is active area and isolated area；In defining an antifuse configuring area in Semiconductor substrate, a groove structure for surrounding antifuse configuring area is formed, antifuse configuring area includes the Part I being located in active area and the Part II extended in isolated area；Dielectric layer and conductive layer are formed in the bottom of groove structure and partial sidewalls；Conductive layer and the first contact hole are electrically connected in being formed in isolated area, second contact hole with side of the groove structure away from the first contact hole in formation in active area with the second spacing.Through the above scheme, the utility model passes through one jiao of setting protrusion in flush type metal wire, tie point when can be turned on control circuit, first contact hole is arranged in isolated area, stability during ensureing break-over of device, its preparation can be completed in the preparation flow of the flush type character line of memory, without increasing extra processing step.
Description
Technical field
The utility model belongs to ic manufacturing technology field, more particularly to a kind of semiconductor devices antifuse knot
Structure.
Background technology
It is well known that nonvolatile memory can still preserve its data content after power is turned off.In general, when non-
Volatile memory manufacture is completed and after dispatching from the factory, and user can program (program) nonvolatile memory, and then by number
According to record in the nonvolatile memory.And according to the number of programming, nonvolatile memory can further discriminate between for：Repeatedly compile
Memory (multi-time programmable memory, abbreviation MTP memory), the memory of one-time programming of journey
(Mask ROM are stored for (onetime programmable memory, abbreviation otp memory) or mask read-only storage
Device).
Otp memory part can be classified as fuse-type otp memory part or anti-fuse type otp memory part.Including
Each storage unit in fuse-type otp memory part can provide short circuit before it is programmed, and can be in its quilt
Open circuit is provided after programming.On the contrary, each storage unit being included in anti-fuse type otp memory part can be compiled at it
Open circuit is provided before journey, and short circuit can be provided after it is programmed.In view of the feature of MOS transistor, CMOS technology
It can be adapted for the manufacture of anti-fuse type otp memory part.
And as DRAM spare memory cells control, anti-fuse structures are most important, and in the prior art, there is antifuse knot
Not the problems such as when structure turns on, firing point position is not known, and conducting circuit is single, and device is unstable after conducting, in addition, existing skill
The preparation of antifuse device structure in art mostly independently of the preparation process flow of other devices outside, complex process, production
Cycle is grown, and cost is higher.
Therefore, how a kind of anti-fuse structures and preparation method thereof are provided, it is real to solve the above problem of the prior art
Belong to necessary.
Utility model content
In view of the foregoing deficiencies of prior art, melt the purpose of this utility model is to provide a kind of semiconductor devices is counter
Silk structure, for solving, anti-fuse structures connectivity points in the prior art are not known and device is unstable and anti-molten after line conduction
The problems such as silk structure preparation process is complicated.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor devices anti-fuse structures
Preparation method, includes the following steps：
1) semi-conductive substrate is provided, the Semiconductor substrate has active area and the isolation positioned at active area periphery
Area；
2) in defining an antifuse configuring area in the Semiconductor substrate, and one is formed around the antifuse configuring area
Groove structure, wherein, the antifuse configuring area includes Part I in the active area and with being connected described the
One end of a part simultaneously extends in the Part II in the isolated area；
3) continuous dielectric layer is formed in the bottom of the groove structure and partial sidewalls, and is filled in the dielectric layer
Conductive layer, the top of the conductive layer are less than the upper surface of the Semiconductor substrate；And
4) it is electrically connected to the conductive layer and has the of the first spacing with the active area in being formed in the isolated area
One contact hole, and in forming the second contact hole in the active area, second contact hole is with the groove structure away from institute
The side for stating the first contact hole has the second spacing.
As a kind of preferred solution of the utility model, in step 2), the step of forming the groove structure：
2-1) in being correspondingly formed the first mask layer on the antifuse configuring area, and formed in the semiconductor substrate surface
Cover the top of first mask layer and the second mask layer of side wall；
Second mask layer and first mask layer at the top of first mask layer 2-2) are removed, to retain
State the part that the second mask layer is formed in the side of first mask layer；
2-3) in step 2-2) surface one layer of the 3rd mask layer of deposition of structure is obtained, separately make the upper of the 3rd mask layer
Surface is not higher than the upper surface of remaining second mask layer；
Remaining second mask layer 2-4) is removed, to obtain groove opening；And
2-5) continue to etch the Semiconductor substrate by the groove opening, with the Semiconductor substrate formed with
The corresponding groove structure of groove opening.
As a kind of preferred solution of the utility model, step 2-3) in, formed three mask layer the step of include：
Prior to step 2-2) obtain threeth mask material of surface one layer height of formation higher than remaining second mask layer of structure
Layer, then part the 3rd mask layer is removed until exposing remaining second mask layer using flatening process
Top, to obtain the 3rd mask layer.
As a kind of preferred solution of the utility model, in step 2), the groove structure of formation include ring part with
And protrusion, wherein, the ring part is around the lateral wall of the antifuse configuring area, and the protruding parts is in the ring part
Have on the lateral wall of the side of second contact hole and between the protrusion and second contact hole between the 3rd
Away from.
As a kind of preferred solution of the utility model, in step 1), further include and formed in the semiconductor substrate surface
The step of one layer of etching barrier layer.
As a kind of preferred solution of the utility model, in step 3), before further including the filling conductive layer, in described
Dielectric layer surface forms the step of one layer of cementing layer.
As a kind of preferred solution of the utility model, the top of the dielectric layer is less than the upper table of the Semiconductor substrate
Face；Further include in step 3) obtain structure surface formed one layer of filling perforation insulating layer the step of, the filling perforation insulating layer is filled in
The top of the groove structure and the upper surface for extending to the Semiconductor substrate.
As a kind of preferred solution of the utility model, in step 4), first spacing is 0.3~30 nanometer；It is described
Second spacing is 0.3~30 nanometer.
As a kind of preferred solution of the utility model, the depth of the isolated area is the semiconductive substrate thickness
50%~90%；The length in the isolated area of the Part II of the antifuse configuring area is total for the Part II
The 10%~50% of length；The width of the groove structure is the 10%~50% of the width of the antifuse configuring area；It is described
The depth of groove structure is the 30%~70% of the semiconductive substrate thickness；The top of the dielectric layer and the conductive layer with
The distance between described semiconductor substrate surface is the 20%~60% of the groove structure depth；The thickness of the dielectric layer is
The 0.1%~10% of the groove structure width.
As a kind of preferred solution of the utility model, the process implementing of step 1)~step 4) is in flush type character line
In making.
The utility model also provides a kind of semiconductor device structure, and the semiconductor device structure includes：
Semiconductor substrate, has active area and the isolated area positioned at active area periphery；Antifuse configuring area, is defined in
In the Semiconductor substrate, the antifuse configuring area include Part I in the active area and be connected described in
One end of Part I simultaneously extends to the Part II in the isolated area；Groove structure, in the Semiconductor substrate, and
Around the outer rim for being arranged at the antifuse configuring area；
Dielectric layer and conductive layer, the dielectric layer are incorporated into bottom and the partial sidewalls of the groove structure, the conduction
Layer is filled in the dielectric layer, and the surface of the Semiconductor substrate is below at the top of the dielectric layer and the conductive layer；
And
First contact hole and the second contact hole, first contact hole are electrically connected to described in the isolated area and lead
There is the first spacing in electric layer and with the active area, second contact hole be located in the active area and with the groove knot
Side of the structure away from first contact hole has the second spacing.
As a kind of preferred solution of the utility model, the groove structure includes ring part and protrusion, wherein, institute
Lateral wall of the ring part around the antifuse configuring area is stated, the protruding parts is in the ring part close to the described second contact
There is the 3rd spacing on the lateral wall of the side of window and between the protrusion and second contact hole.
As a kind of preferred solution of the utility model, the top of the dielectric layer is less than the upper table of the Semiconductor substrate
Face；The semiconductor devices anti-fuse structures further include filling perforation insulating layer, are filled in the top of the groove structure and extend to
The upper surface of the Semiconductor substrate, wherein, first contact hole is electrically connected through the filling perforation insulating layer with the conductive layer
Connect, second contact hole is through the filling perforation insulating layer and extends in the active area.
As a kind of preferred solution of the utility model, one layer of glue is also formed between the dielectric layer and the conductive layer
Close layer.
As a kind of preferred solution of the utility model, the material of the cementing layer includes titanium nitride.
As a kind of preferred solution of the utility model, the material of the conductive layer is selected from tungsten, titanium, nickel, aluminium, platinum, silicon nitrogen
At least one of group that change titanium, metal nitride, metal silicide and DOPOS doped polycrystalline silicon are formed；The conductive layer
Resistivity is 2 × 10-8Ω m~1 × 102Ωm；；The group that the material of the dielectric layer is selected from silica, hafnium oxide is formed
At least one of.
As a kind of preferred solution of the utility model, the structure phase of first contact hole and second contact hole
Together, including conductive column and lateral wall and the bonding layer of bottom positioned at the conductive column.
As a kind of preferred solution of the utility model, first spacing is 0.3~30 nanometer；Second spacing is
0.3~30 nanometer.
As described above, semiconductor structure of the utility model and preparation method thereof, has the advantages that：
The semiconductor device structure of the utility model, can be used as DRAM spare memory cells control anti-fuse structures, lead to
Cross one jiao in its flush type metal wire and be arranged to projective structure, tie point when being turned on so as to control circuit, and pass through
First contact hole is arranged in the isolated area for having the first spacing with active area, stability during ensureing break-over of device, together
When, by the setting of two flush type metal wires, shortest one of circuit selection after line conduction can be made；In addition, this practicality
The preparation of new semiconductor device structure can be completed in the preparation flow of the flush type character line of memory, without increase
Extra processing step, so as to simplify preparation process, shortens the production cycle, reduces production cost.
Brief description of the drawings
Fig. 1 is shown as flow chart prepared by the semiconductor device structure of the utility model.
Fig. 2 is shown as providing the structure diagram of Semiconductor substrate in the semiconductor device structure preparation of the utility model.
Fig. 3 is shown as the schematic diagram of the antifuse configuring area defined in the semiconductor device structure preparation of the utility model.
Fig. 4 is shown as the top view of the groove structure formed in the semiconductor device structure preparation of the utility model.
Fig. 5 is shown as being formed the structure diagram of the first mask layer in the semiconductor device structure preparation of the utility model.
Fig. 6 is shown as the sectional view in A-A ' directions in structure shown in Fig. 5.
Fig. 7 is shown as the sectional view in B-B ' directions in structure shown in Fig. 5.
Fig. 8 is shown as being formed the structure diagram of the second mask layer in the semiconductor device structure preparation of the utility model.
Fig. 9 is shown as the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 10 is shown as the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 11 is shown as being formed the structure of remaining second mask layer in the sectional view in A-A ' directions in structure shown in Fig. 8
Figure.
Figure 12 is shown as being formed the structure of remaining second mask layer in the sectional view in B-B ' directions in structure shown in Fig. 8
Figure.
Figure 13 is shown as being formed the structure chart of the first mask layer in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 14 is shown as being formed the structure chart of the first mask layer in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 15 is shown as being formed the structure chart of the first mask layer in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 16 is shown as being formed the structure chart of the first mask layer in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 17 is shown as being formed the structure chart of groove opening in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 18 is shown as being formed the structure chart of groove opening in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 19 is shown as being formed the structure chart of groove structure in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 20 is shown as being formed the structure chart of groove structure in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 21 is shown as being formed the structure chart of dielectric layer in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 22 is shown as being formed the structure chart of dielectric layer in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 23 is shown as being formed the structure chart of cementing layer in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 24 is shown as being formed the structure chart of cementing layer in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 25 is shown as being formed the structure chart of conductive layer in the sectional view in A-A ' directions in structure shown in Fig. 8.
Figure 26 is shown as being formed the structure chart of conductive layer in the sectional view in B-B ' directions in structure shown in Fig. 8.
Figure 27 is shown as forming bowing for first, second contact hole in prepared by semiconductor device structure provided by the utility model
View.
Figure 28 is shown as the sectional view in A-A ' directions in structure shown in Figure 27.
Figure 29 is shown as the sectional view in B-B ' directions in structure shown in Figure 27.
Component label instructions
1 Semiconductor substrate
11 active areas
12 isolated areas
13 antifuse configuring areas
131 Part II
132 Part I
21 first mask layers
The Part I of 211 first mask layers
The Part II of 212 first mask layers
31 etching barrier layers
41 second mask layers
42 remaining second mask layers
51 the 3rd mask layers
52 the 3rd mask layers
61 groove openings
71 groove structures
711 ring parts
712 protrusions
81 dielectric layers
82 cementing layers
83 conductive layers
91 first contact holes
92 second contact holes
S1~S4 steps 1)~step 4)
Embodiment
Illustrate the embodiment of the utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Please refer to Fig.1 to Figure 29.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when only display is with related component in the utility model rather than according to actual implementation in diagram
Component count, shape and size are drawn, and form, quantity and the ratio of each component can be a kind of random change during its actual implementation
Become, and its assembly layout form may also be increasingly complex.
As shown in Figure 1, the utility model provides a kind of preparation method of semiconductor devices anti-fuse structures, including following step
Suddenly：
1) semi-conductive substrate is provided, the Semiconductor substrate has active area and the isolation positioned at active area periphery
Area；
2) in defining an antifuse configuring area in the Semiconductor substrate, and one is formed around the antifuse configuring area
Groove structure, wherein, the antifuse configuring area includes Part I in the active area and with being connected described the
One end of a part simultaneously extends to the Part II in the isolated area；
3) continuous dielectric layer is formed in the bottom of the groove structure and partial sidewalls, and is filled in the dielectric layer
Conductive layer, the top of the conductive layer are less than the upper surface of the Semiconductor substrate；And
4) it is electrically connected to the conductive layer and has the of the first spacing with the active area in being formed in the isolated area
One contact hole, and in forming the second contact hole in the active area, second contact hole is with the groove structure away from institute
The side for stating the first contact hole has the second spacing.
Describe semiconductor device structure of the utility model and preparation method thereof in detail below in conjunction with attached drawing.
As shown in S1 and Fig. 2 in Fig. 1, step 1) is carried out, there is provided semi-conductive substrate 1, the Semiconductor substrate 1 have
Active area 11 and the isolated area 12 positioned at the periphery of active area 11；
Specifically, the material of the Semiconductor substrate 1 of the utility model includes but not limited to monocrystalline or polycrystalline semiconductor material,
In addition, the substrate 1 can also be the silicon substrate of intrinsic monocrystalline substrate either light dope, can also be on insulator
The substrate materials well known within the skill of those ordinarily skilled such as silicon, germanium silicon, the active area 11 include the material with element doping,
In the present embodiment, the material of the Semiconductor substrate 1 is single crystal silicon material.In addition, the channel separating zone 12 can be shallow ridges
Recess isolating structure, including shallow trench and the dielectric material that is filled in the shallow trench, the K values of the dielectric material are usually small
In 3, it acts as the electric leakage of isolation shallow trench and mitigation to be electrically coupled (coupling), and the dielectric material can be silica material
Material etc..In addition, periphery here refers to the abducent region of active region sidewalls, the active area and isolated area side phase
Contact.
As an example, the depth of the isolated area 12 is the 50%~90% of 1 thickness of Semiconductor substrate.
Specifically, the depth of the isolated area 12 is preferably the 60%~80% of 1 thickness of Semiconductor substrate, so as to control
Degree of isolation between transistor processed, it is ensured that the component of the utility model such as the first contact hole realizes its function, this example
The depth of the middle selection isolated area 12 is the 70% of 1 thickness of Semiconductor substrate.
As an example, in step 1), further include and form the step of one layer of etching barrier layer 31 in 1 surface of Semiconductor substrate
Suddenly.
Specifically, the step of whole surface for being additionally included in Semiconductor substrate 1 deposits one layer of etching barrier layer 31, its material
Including but not limited to silicon nitride, the etching barrier layer 31 are used to protect Semiconductor substrate in the techniques such as follow-up etching are carried out
It is injury-free, so that the further stability of retainer member performance.
As shown in the S2 in Fig. 1 and Fig. 3~20, step 2) is carried out, is matched somebody with somebody in defining an antifuse in the Semiconductor substrate 1
Area 13 is put, and forms a groove structure 71 for surrounding the antifuse configuring area 13, wherein, the antifuse configuring area 13 includes
Part I 132 in the active area 11 and it is connected with one end of the Part I 132 and extends to described
Part II 131 in isolated area 12；
Specifically, the purpose of the step is the semiconductor device structure for the application, such as anti-fuse structures, there is provided forms two
The groove of bar flush type metal wire, wherein, the antifuse configuring area 13 is used to define the groove structure 71 being subsequently formed
Shape and position, so as to finally determine the position of two flush type metal wires.In addition, the Part I and described
Part II is preferably orthogonal, the shape of the antifuse configuring area 13 can be L-type, with the shape such as L-type is mirror-symmetrical
Shape, certainly, the Part II can also have certain non-perpendicular angle in other embodiments with the Part I,
It is preferably the antifuse configuring area 13 of the two vertical L-type in this example.
As an example, in step 2), the step of forming groove structure 71, specifically includes：
2-1) in being correspondingly formed the first mask layer 21 on the antifuse configuring area 13, and in 1 table of Semiconductor substrate
Face forms the second mask layer 41 of the top for covering first mask layer 21 and side wall, wherein, second mask layer 41 is right
The region of Semiconductor substrate 1 described in Ying Yu is used to be subsequently formed the groove structure 71, as shown in Fig. 5~10；
Second mask layer 41 at the top of the first mask layer 21 and first mask layer 21 2-2) are removed, with
Retain the part that second mask layer 41 is formed in the side of first mask layer 21, as shown in Figure 11~12；
2-3) in step 2-2) surface one layer of the 3rd mask layer 52 of deposition of structure is obtained, separately make the 3rd mask layer 52
Upper surface be not higher than remaining second mask layer 41 upper surface, as shown in Figure 13~16；
Remaining second mask layer 41 2-4) is removed, to obtain groove opening 61, as shown in Figure 17~18；And
2-5) continue to etch the Semiconductor substrate 1 by the groove opening 61, with shape in the Semiconductor substrate 1
Into with the corresponding groove structure 71 of the groove opening 61, as shown in Figure 19~20.
Specifically, this example provides a kind of preparation method of groove structure, one layer of first mask layer 21 is deposited first, its
In, first mask layer 21 includes but not limited to photoresist, and one layer of second mask layer is then covered on the first mask layer 21
41, second mask layer 41 includes but not limited to SADP (self-aligned double patterning) hard mask, institute
The depositional mode for stating the first mask layer 21 and second mask layer 41 is well known within the skill of those ordinarily skilled any heavy
Product mode.
In addition, in this example, first mask layer 21 also just has due to being correspondingly formed with the antifuse configuring area 13
Corresponding Part I 211 and Part II 212, wherein, the Part I 211 is entirely located in the active area 11, institute
212 one end of Part II to be stated with the Part I 211 to be connected, the other end is extended in the isolated area 12, correspondingly, by
Cover first mask layer 21 in second mask layer 41, then its it is inevitable also some be located in the active area, one
Part is located in the isolated area, wherein, the part of active area is located at for the first mask layer 21, it is corresponding to be covered in its side
Second mask layer 41 is also entirely located on the active area, and the part of isolated area, corresponding covering are located at for the first mask layer 21
The second mask layer 41 in its side is also entirely located in the isolated area, as shown in Figure 8.
Specifically, the step of removing first mask layer 21 and the second mask layer of part 41 is further included, by these
After the removal of material, the patterning of double exposure is formd, obtained remaining second mask layer 41 is first to cover
Twice of 21 quantity of film layer, so as to the flush type metal wire of the anti-fuse structures needed.Wherein, the first mask is removed
Can use flatening process during second mask layer 41 at the top of layer 21, remove the first mask layer 21 can using ion etching or
The technique of person's wet etching, is not particularly limited herein.It should be noted that this technique and the litho pattern in device array area
Unanimously, the two can be completed in same technique, so as to simplify the complexity of technique, shortened production manufacturing cycle, gone forward side by side
One step reduces device cost, and so that size preferably matches between device, device performance is stablized.
As an example, step 2-3) in, formed the 3rd mask layer 52 the step of include：Prior to step 2-2) tied
The surface of structure forms the 3rd mask layer 51 that a layer height is higher than remaining second mask layer 41, then using planarization
Technique removes part the 3rd mask layer 51 until the top of remaining second mask layer 41 is exposed, to obtain
3rd mask layer 52.
Specifically, first in step 2-2) after structure on cover one layer of the 3rd mask layer 51, its material is included but not
It is limited to silica, then exposes the top of the second mask layer 41 by flatening process, ensures that subsequent technique is smoothed out.
As an example, for the antifuse configuring area 13, described vertical 131 length in the isolated area 12
For the 10%~50% of 131 total length of Part II；The width of the groove structure 71 is the antifuse configuring area 13
Width 10%~50%；The depth of the groove structure 71 is the 30%~70% of 1 thickness of Semiconductor substrate.
Specifically, have to the antifuse configuring area 13 i.e. corresponding first mask layer 21 in isolated area
The limitation of length is to rationally design the position of the first follow-up contact hole, and the anti-fuse structures so as to obtain stable are led
Logical stability, described vertical 131 length in the isolated area 12 is preferably 131 total length of Part II
20%~40%, it is 30% in this example；The width of the groove structure 71 is preferably the width of the antifuse configuring area 13
20%~40%, be 30% in this example；The depth of the groove structure 71 is preferably 1 thickness of Semiconductor substrate
40%~60%, it is 50% in this example.The setting of the parameter can match each other, and can obtain the device of performance stabilization
Structure.
As an example, the groove structure 71 formed includes ring part 711 and on the ring part lateral wall
Protrusion 712, the ring part 711 is surrounded on the lateral wall of the antifuse configuring area 13, and the protrusion 712 is located at institute
Ring part is stated on the lateral wall of the side of second contact hole 92 and the protrusion 712 and second contact hole 92
Between there is the 3rd spacing Z3.
Specifically, in this example, there is provided the groove structure 71 of another shape, at it close to the second contact hole 92
One jiao of setting, one protrusion 712, so that the flush type metal wire for ensureing to be subsequently formed has a protrusion 712, due to this
Protrusion 712 and the position of second contact hole are closer to, and thereby may be ensured that the connectivity points of anti-fuse structures occur herein
Place, so as to control the communicating position of antifuse device, improves the stability and certainty of antifuse device structure.
As shown in the S3 in Fig. 1 and Figure 22~26, step 3) is carried out, in the bottom of the groove structure 71 and partial sidewalls
Continuous dielectric layer 81 is formed, and in filling conductive layer 83 in the dielectric layer 81, the top of the conductive layer 83 is less than described
The upper surface of Semiconductor substrate 1；
As an example, the top of the dielectric layer 81 is less than the upper surface of the Semiconductor substrate 1, it is preferable that is given an account of
The upper surface flush of matter layer 81 and the conductive layer 83, is below the upper surface of the Semiconductor substrate 1.
As an example, in step 3), further include to be formed after the dielectric layer 81 and the filling conductive layer 83 before, in described
81 surface of dielectric layer forms the step of one layer of cementing layer 82.
Specifically, the purpose of the step is the filling groove structure 71, to obtain the metal wire of flush type, wherein, can
Pass through low pressure gas phase deposition (Low Presure Chemical Vapor Deposition) or plasma gas-phase deposit
(Atomic Layer are made in (Plasma Enhancement Chemical Vapor Deposition) or atomic deposition
) etc. Deposition technique is formed, and the material of the conductive layer 83 is selected from tungsten, titanium, nickel, aluminium, platinum, silicon titanium nitride, nitride metal
In the group that thing, metal silicide (titanium silicide, nickle silicide) and DOPOS doped polycrystalline silicon (N-type polycrystalline silicon, p-type polysilicon) are formed
At least one, certainly, its can be above-mentioned material in two kinds or the laminated material bed of material formed above；The conductive layer 83
Resistivity is 2 × 10-8Ω m~1 × 102Ωm；The group that the material of the dielectric layer 81 is selected from silica, hafnium oxide is formed
At least one of group, or the laminated material bed of material that two kinds of materials are formed.In addition, be additionally included in dielectric layer and conductive layer it
Between form one layer of cementing layer, such as the step of titanium nitride, to improve contact turn-on effect therebetween.
As an example, between the dielectric layer 81 and 1 surface of top and the Semiconductor substrate of the conductive layer 83
Distance is the 20%~60% of 71 depth of groove structure；The thickness of the dielectric layer 81 is 71 width of groove structure
0.1%~10%.
Specifically, between the dielectric layer 81 and 1 surface of top and the Semiconductor substrate of the conductive layer 83 away from
It is 40% from the 30%~50% of preferably described 71 depth of groove structure, in this example；The thickness of the dielectric layer 81 is preferred
For the 1%~8% of 71 width of groove structure, selected as 5% in this example.
As an example, further include in body structure surface that step 3) obtains forms one layer of filling perforation insulating layer 93 the step of, it is described
Filling perforation insulating layer 93 is filled in the top of the groove structure 71 and extends to the upper surface of the Semiconductor substrate 1.
Specifically, the utility model be additionally included in prepare the first contact hole 91 and the second contact hole 92 before formed and fill out
The step of hole insulating layer 93, its material include but not limited to silica.Wherein, first contact hole 91 passes through the filling perforation
Insulating layer is electrically connected with the conductive layer, and second contact hole 92 is through the filling perforation insulating layer and extends to the active area
It is interior.
As shown in the S4 in Fig. 1 and Figure 27~29, step 4) is carried out, is electrically connected in formation in the isolated area 12 described
Conductive layer 83 and first contact hole 91 with the active area 11 with the first spacing Z1, and in formation in the active area 11
Second contact hole 92, second contact hole 92 and side of the groove structure 71 away from first contact hole 91 have the
Two spacing Z2, wherein, for the position relationship between each device architecture of clearer display, other not phases for being omitted in Figure 27
The structure of pass.
As an example, in step 4), first spacing is 0.3~30 nanometer；Second spacing is received for 0.3~30
Rice.
As an example, first contact hole 91 is identical with the structure of second contact hole 92, including conductive column and
Positioned at the lateral wall of the conductive column and the bonding layer of bottom.Wherein, the conductive layer material of conductive column and the flush type metal wire
Material etc. is identical, and the bonding layer is identical with the cementing layer in the flush type metal wire, selected as titanium nitride.
Specifically, this step completes the making of contact hole, so that the semiconductor device structure of the utility model is completed, it is such as anti-
The preparation of fuse-wires structure.Wherein, the first spacing and the second spacing rationally are provided with, wherein, the first spacing is preferably 5~20 to receive
Rice, the second spacing is preferably 5~20 nanometers, and in the present embodiment, first spacing and second spacing are disposed as 10nm,
Wherein, first spacing refer to first contact hole close to one side of the active area with the active area close to described first
The distance between one side of contact hole, the first contact hole is arranged in the isolated area and keeps the first spacing with active area,
It is because when anti-fuse structures turn on, there is very big electrical potential difference, and the insulating materials of isolated area can alleviate this electricity
Influence caused by potential difference, and the application rationally sets the size of the first spacing, so as to ensure that size of devices, cost and steady
It is qualitative.In addition, second spacing refers to second contact hole close to one side of the isolation structure and the isolation structure
Close to the distance between one side of first contact hole, it is preferably identical with first spacing, so as to ensure that device
The matching of structural member.
As an example, the process implementing of step 1)~step 4) is in the making of flush type character line.
It should be noted that the flush type metal wire of the utility model can be with existing flush type character line with identical
Structure, using the litho pattern and technique identical with device array area, so that the processing step of the utility model can made
Completed while standby character line, may not need increases other steps, simplifies the complexity of existing process, reduces preparation week
Phase, reduces cost.
As shown in Fig. 2~29, the utility model also provides a kind of semiconductor device structure, wherein, the semiconductor structure
Can be the structure being prepared using the method for the utility model, or prepared by other methods, with the utility model system
Illustrated exemplified by standby obtained structure, the semiconductor device structure includes：
Semiconductor substrate 1, has active area 11 and the isolated area 12 positioned at active area periphery；Antifuse configuring area
13, it is defined in the Semiconductor substrate 1, the antifuse configuring area 13 includes the Part I in the active area 11
132 and with being connected one end of the Part I 132 and extending to the Part II 131 in the isolated area 12, referring to Fig. 3
It is shown；Groove structure 71, is set in the Semiconductor substrate 1, and around the antifuse configuring area 13, referring in Fig. 4
Structure shown in；
Dielectric layer 81 and conductive layer 83, the dielectric layer 81 are incorporated into bottom and the partial sidewalls of the groove structure 71,
The conductive layer 83 is filled in the dielectric layer 81, and the top of the conductive layer 83 is less than the upper table of the Semiconductor substrate 1
Face, participate in Figure 24 and Figure 25 sectional view described in；And
First contact hole 91 and the second contact hole 92, first contact hole 91 are electrically connected in the isolated area 12
There is the first spacing on the conductive layer 83 and with the active area 11, second contact hole 92 is located in the active area 11
And there is the second spacing with side of the groove structure 71 away from first contact hole 91, referring to shown in Figure 26~29.
Specifically, semiconductor device structure provided by the utility model may be used as anti-fuse structures, it has two and buries
Enter formula metal wire, and the first spacing and the second spacing set, wherein, the setting of the first spacing, can prevent antifuse
When structure turns on, the unstable phenomenon of device architecture is caused to occur due to high-tension presence, first contact hole 91 is set
Put in isolated area, there is scattered alleviation, so as to improve the stability of break-over of device.
Specifically, the material of the Semiconductor substrate 1 of the utility model includes but not limited to monocrystalline or polycrystalline semiconductor material,
In addition, the substrate 1 can also be the silicon substrate of intrinsic monocrystalline substrate either light dope, can also be on insulator
The substrate materials well known within the skill of those ordinarily skilled such as silicon, germanium silicon, the active area 11 include the material with element doping,
In the present embodiment, the material of the Semiconductor substrate 1 is single crystal silicon material.In addition, the channel separating zone 12 can be shallow ridges
Recess isolating structure, including shallow trench and the dielectric material that is filled in the shallow trench, the K values of the dielectric material are usually small
In 3, it acts as the electric leakage of isolation shallow trench and mitigation to be electrically coupled (coupling), and the dielectric material can be silica material
Material etc..In addition, periphery here refers to the abducent region of active region sidewalls, the active area and isolated area side phase
Contact.
As an example, the groove structure 71 includes ring part 711 and protrusion 712, wherein, the ring part 711
Lateral wall around the antifuse configuring area, the protrusion 712 are located at the ring part close to second contact hole 92
Side lateral wall on and there is between the protrusion 712 and second contact hole 92 the 3rd spacing Z3.
Specifically, in this example, there is provided the groove structure 71 of another shape, at it close to the second contact hole 92
One jiao of setting, one protrusion, so that the flush type metal wire for ensureing to be subsequently formed has a protrusion, due to the protrusion
Be closer to the position of second contact hole, thereby may be ensured that anti-fuse structures connectivity points occur here, so as to
To control the communicating position of antifuse device, the stability and certainty of antifuse device structure are improved.
As an example, the top of the dielectric layer 81 is less than the upper surface of the Semiconductor substrate 1, it is preferable that is given an account of
The upper surface flush of matter layer 81 and the conductive layer 83, is below the upper surface of the Semiconductor substrate 1.
As an example, further include filling perforation insulating layer 93, it is filled in the top of the groove structure 71 and extends to described half
The upper surface of conductor substrate 1, wherein, first contact hole 91 is electrically connected through the filling perforation insulating layer 93 with the conductive layer 83
Connect, second contact hole 92 is through the filling perforation insulating layer 93 and extends in the active area 11.
Specifically, the utility model be additionally included in prepare the first contact hole 91 and the second contact hole 92 before formed and fill out
The step of hole insulating layer 93, its material include but not limited to silica.Wherein, first contact hole 91 passes through the filling perforation
Insulating layer is electrically connected with the conductive layer, and second contact hole 92 is through the filling perforation insulating layer and extends to the active area
It is interior.
As an example, one layer of cementing layer 82 is also formed between the dielectric layer 81 and the conductive layer 83.Specifically, institute
Stating the material of cementing layer 82 includes titanium nitride, to improve contact turn-on effect therebetween.
As an example, the material of the conductive layer 83 is selected from tungsten, titanium, nickel, aluminium, platinum, silicon titanium nitride, metal nitride, gold
Belong at least one of group that silicide and DOPOS doped polycrystalline silicon are formed；The resistivity of the conductive layer 83 is 2 × 10-8Ω
M~1 × 102Ωm；The material of the dielectric layer 81 is selected from least one of silica, the group that hafnium oxide is formed.
Specifically, the material of the conductive layer 83 is selected from tungsten, titanium, nickel, aluminium, platinum, silicon titanium nitride, metal nitride, metal
In the group that silicide (titanium silicide, nickle silicide) and DOPOS doped polycrystalline silicon (N-type polycrystalline silicon, p-type polysilicon) are formed at least
One kind, certainly, it can be two kinds or the laminated material bed of material formed above in above-mentioned material；The resistivity of the conductive layer 83
For 2 × 10-8Ω m~1 × 102Ωm；The material of the dielectric layer 81 is in the group that silica, hafnium oxide are formed
It is at least one, or the laminated material bed of material that two kinds of materials are formed.
As an example, first contact hole 91 is identical with the structure of second contact hole 92, including conductive column and
Positioned at the lateral wall of the conductive column and the bonding layer of bottom.Wherein, the conductive layer material of conductive column and the flush type metal wire
Material etc. is identical, and the bonding layer is identical with the cementing layer in the flush type metal wire, selected as titanium nitride.
As an example, first spacing is 0.3~30 nanometer；Second spacing is 0.3~30 nanometer.
Specifically, this step completes the making of contact hole, so that the semiconductor device structure of the utility model is completed, it is such as anti-
The preparation of fuse-wires structure.Wherein, the first spacing and the second spacing rationally are provided with, wherein, the first spacing is preferably 5~20 to receive
Rice, the second spacing is preferably 5~20 nanometers, and in the present embodiment, first spacing and second spacing are disposed as 10nm,
Wherein, first spacing refer to first contact hole close to one side of the active area with the active area close to described first
The distance between one side of contact hole, the first contact hole is arranged in the isolated area and keeps the first spacing with active area,
It is because when anti-fuse structures turn on, there is very big electrical potential difference, and the insulating materials of isolated area can alleviate this electricity
Influence caused by potential difference, and the application rationally sets the size of the first spacing, so as to ensure that size of devices, cost and steady
It is qualitative.In addition, second spacing refers to second contact hole close to one side of the isolation structure and the isolation structure
Close to the distance between one side of first contact hole, it is preferably identical with first spacing, so as to ensure that device
The matching of structural member.
In conclusion the utility model provides a kind of semiconductor devices anti-fuse structures, preparation includes the following steps：1) carry
For semi-conductive substrate, the Semiconductor substrate has active area and the isolated area positioned at active area periphery；2) in described
An antifuse configuring area is defined in Semiconductor substrate, and forms a groove structure for surrounding the antifuse configuring area, wherein, institute
Stating antifuse configuring area includes the Part I in the active area and is connected simultaneously with one end of the Part I
Extend to the Part II in the isolated area；3) continuous medium is formed in the bottom of the groove structure and partial sidewalls
Layer, and in filling conductive layer in the dielectric layer, the top of the conductive layer is less than the surface of the Semiconductor substrate；And 4)
The conductive layer is electrically connected in formation in the isolated area and there is the first contact hole of the first spacing with the active area, with
And in forming the second contact hole in the active area, second contact hole is with the groove structure away from first contact hole
Side there is the second spacing.Through the above scheme, the semiconductor devices anti-fuse structures of the utility model, can be used as DRAM
Spare memory cell controls anti-fuse structures, by being arranged to projective structure in one jiao of its flush type metal wire, so as to
Tie point when control circuit turns on, and by the way that the first contact hole is arranged on the isolated area for having the first spacing with active area
In, stability during ensureing break-over of device, meanwhile, by the setting of two flush type metal wires, after line conduction being made
Shortest one of circuit selection；In addition, the preparation of the semiconductor device structure of the utility model can be in the flush type of memory
Completed in the preparation flow of character line, without increasing extra processing step, so as to simplify preparation process, shorten production week
Phase, reduces production cost.So the utility model effectively overcomes various shortcoming of the prior art and has high industrial profit
With value.
The above embodiments are only illustrative of the principle and efficacy of the utility model, new not for this practicality is limited
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by the claim of the utility model.
Claims (9)
- A kind of 1. semiconductor devices anti-fuse structures, it is characterised in that including：Semiconductor substrate (1), has active area (11) and the isolated area (12) positioned at active area periphery, antifuse configuring area (13) it is defined in the Semiconductor substrate, the antifuse configuring area includes the Part I in the active area (132) and connect one end of the Part I and extend to the Part II (132) in the isolated area, groove structure (71) in the Semiconductor substrate, and set around the antifuse configuring area；Dielectric layer (81) and conductive layer (83), the dielectric layer is incorporated into bottom and the partial sidewalls of the groove structure, described Conductive layer is filled in the dielectric layer, and the top of the conductive layer is less than the upper surface of the Semiconductor substrate；AndFirst contact hole (91) and the second contact hole (92), first contact hole are electrically connected to the institute in the isolated area State on conductive layer and there is the first spacing (Z1) with the active area, second contact hole be located in the active area and with institute Stating side of the groove structure away from first contact hole has the second spacing (Z2).
- 2. semiconductor devices anti-fuse structures according to claim 1, it is characterised in that the groove structure includes annular Portion (711) and protrusion (712), wherein, the ring part is around the lateral wall of the antifuse configuring area, the protrusion Positioned at the ring part on the lateral wall of the side of second contact hole and the protrusion and second contact hole Between there is the 3rd spacing (Z3).
- 3. semiconductor devices anti-fuse structures according to claim 1, it is characterised in that the top of the dielectric layer is less than The upper surface of the Semiconductor substrate；The semiconductor devices anti-fuse structures further include filling perforation insulating layer (93), are filled in institute State the top of groove structure and extend to the upper surface of the Semiconductor substrate, wherein, first contact hole is filled out through described Hole insulating layer is electrically connected with the conductive layer, and second contact hole is through the filling perforation insulating layer and extends to the active area It is interior.
- 4. semiconductor devices anti-fuse structures according to claim 1, it is characterised in that the dielectric layer and the conduction One layer of cementing layer (82) is also formed between layer.
- 5. semiconductor devices anti-fuse structures according to claim 4, it is characterised in that the material of the cementing layer includes Titanium nitride.
- 6. semiconductor devices anti-fuse structures according to claim 1, it is characterised in that the material of the conductive layer is selected from In the group that tungsten, titanium, nickel, aluminium, platinum, silicon titanium nitride, metal nitride, metal silicide and DOPOS doped polycrystalline silicon are formed extremely Few one kind；The resistivity of the conductive layer is 2 × 10-8Ω m~1 × 102Ωm；The material of the dielectric layer be selected from silica, At least one of group that hafnium oxide is formed.
- 7. semiconductor devices anti-fuse structures according to claim 1, it is characterised in that the depth of the isolated area is institute State the 50%~90% of semiconductive substrate thickness；The Part II of the antifuse configuring area is located at the length in the isolated area For the 10%~50% of the Part II total length；The width of the groove structure is the width of the antifuse configuring area 10%~50%；The depth of the groove structure is the 30%~70% of the semiconductive substrate thickness；The top of the conductive layer The distance between portion and the semiconductor substrate surface are the 20%~60% of the groove structure depth；The thickness of the dielectric layer Spend for the 0.1%~10% of the groove structure width.
- 8. semiconductor devices anti-fuse structures according to claim 1, it is characterised in that first contact hole with it is described The structure of second contact hole is identical, including conductive column and lateral wall and the bonding layer of bottom positioned at the conductive column.
- 9. according to semiconductor devices anti-fuse structures according to any one of claims 1 to 8, it is characterised in that described first Spacing is 0.3~30 nanometer；Second spacing is 0.3~30 nanometer.
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| CN107731784B (en) * | 2017-10-31 | 2023-07-04 | 长鑫存储技术有限公司 | Semiconductor device anti-fuse structure and preparation method thereof |
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Effective date of registration: 20181016 Address after: 230601 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |