CN207165563U - Array of capacitors structure - Google Patents
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- CN207165563U CN207165563U CN201721178000.6U CN201721178000U CN207165563U CN 207165563 U CN207165563 U CN 207165563U CN 201721178000 U CN201721178000 U CN 201721178000U CN 207165563 U CN207165563 U CN 207165563U
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- 239000003990 capacitor Substances 0.000 title claims abstract description 100
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000003491 array Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 description 414
- 239000000463 material Substances 0.000 description 74
- 238000000034 method Methods 0.000 description 27
- 230000000873 masking effect Effects 0.000 description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 18
- 229920005591 polysilicon Polymers 0.000 description 15
- 238000005530 etching Methods 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 8
- 238000001039 wet etching Methods 0.000 description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 229910021341 titanium silicide Inorganic materials 0.000 description 6
- 239000007772 electrode material Substances 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
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- 229910052751 metal Inorganic materials 0.000 description 3
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- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
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- 229910017107 AlOx Inorganic materials 0.000 description 2
- 229910019897 RuOx Inorganic materials 0.000 description 2
- 229910018316 SbOx Inorganic materials 0.000 description 2
- 229910003134 ZrOx Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
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- 229910052697 platinum Inorganic materials 0.000 description 2
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
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Abstract
The utility model provides a kind of array of capacitors structure, includes in the Semiconductor substrate formed with multiple pads in internal memory structure of arrays, the array of capacitors structure：Lower electrode layer, with the contact pads, the cross sectional shape of the lower electrode layer is that side wall is in wavy or rectangular toothed U-shaped；Capacitor dielectric layer, it is covered in inner surface and the outer surface of the lower electrode layer；And upper electrode layer, it is covered in the outer surface of the capacitor dielectric layer.Bottom electrode plate of the present utility model, capacitor dielectric layer and electric pole plate surface profile is corrugated or rectangular toothed, can be with significant increase electric capacity in the case where not increasing capacitor height.
Description
Technical field
The utility model belongs to semiconductor devices and manufacturing field, more particularly to a kind of array of capacitors structure.
Background technology
Dynamic RAM (Dynamic Random Access Memory, referred to as：DRAM) commonly used in computer
Semiconductor storage unit, be made up of the memory cell of many repetitions.In the DRAM processing procedures of 20nm once, DRAM uses heap
The capacitor structure of stack, its capacitor (Capacitor) are the cylindrical shapes of vertical high-aspect-ratio.
Fig. 1 to Fig. 6 is referred to, existing DRAM preparation method comprises the following steps：
1) semi-conductive substrate 11 is provided, formed with multiple welderings in internal memory structure of arrays in the Semiconductor substrate 11
Disk 111；
2) dielectric layer 12 and supporting layer 13 being alternately superimposed on are formed in the upper surface of the Semiconductor substrate 11, such as Fig. 1 institutes
Show；
3) upper surface of the structure obtained in step 2) forms Patterned masking layer 14, as shown in Figure 2；
4) supporting layer 13 and the dielectric layer 12 are etched according to the Patterned masking layer 14, with the supporting layer
13 and the dielectric layer 12 in form electric capacity hole 15, the electric capacity hole 15 exposes the pad 111, as shown in Figure 3；
5) in formation lower electrode layer 16 in the electric capacity hole 15, and the dielectric layer 12 is removed, as shown in Figure 4；
6) the capacitor dielectric layer of the covering lower electrode layer 16 is formed in the inner surface of the lower electrode layer 16 and outer surface
17, as shown in Figure 5；And
7) Top electrode 18 of the covering capacitor dielectric layer 17 is formed in the outer surface of the capacitor dielectric layer 17, such as Fig. 6
It is shown.
However, in above-mentioned technique, the dielectric layer 12 as sacrifice layer is single silicon oxide layer, the institute of formation
The side wall for stating electric capacity hole 15 is generally smooth upright side walls.In order to obtain enough electric capacity, need to form depth-to-width ratio at present non-
Often big capacitance structure, that is, need the depth-to-width ratio in the electric capacity hole 15 to be formed sufficiently large.But with the depth in the electric capacity hole 15
Width can all bring very big challenge than increase for etching technics and cleaning.
Utility model content
In view of the above the shortcomings that prior art, the purpose of this utility model is to provide a kind of array of capacitors knot
Structure, for solve in the prior art in order to obtain enough electric capacity, it is necessary to caused by forming the very big electric capacity hole of depth-to-width ratio it is right
Etching technics and cleaning bring the problem of very big challenge.
In order to achieve the above objects and other related objects, the utility model provides a kind of manufacturer of array of capacitors structure
Method, the manufacture method of the array of capacitors structure comprise the following steps：
1) semi-conductive substrate is provided, formed with multiple pads in internal memory structure of arrays in the Semiconductor substrate；
2) sacrifice layer and supporting layer being alternately superimposed on are formed in the upper surface of the Semiconductor substrate, wherein, the sacrifice
Layer includes the first material layer and second material layer being alternately superimposed on, and the first material layer is with the second material layer at same a moment
There is different etch rates in erosion processing procedure；
3) upper surface of the structure obtained in step 2) forms the Patterned masking layer with perforate, the pattern mask
Perforate in layer needs position and the shape in the electric capacity hole to be formed after defining；
4) supporting layer and the sacrifice layer are etched according to the Patterned masking layer, with the supporting layer and described
Formation side wall is corrugated in sacrifice layer or the electric capacity hole of rectangular toothed, the electric capacity hole expose the pad；
5) in forming lower electrode layer in the electric capacity hole；
6) sacrifice layer is removed；
7) the capacitor dielectric layer of the covering lower electrode layer is formed in the inner surface of the lower electrode layer and outer surface；And
8) upper electrode layer of the covering capacitor dielectric layer is formed in the outer surface of the capacitor dielectric layer.
Preferably, in step 2), the first material layer is silicon oxide layer, and the second material layer is polysilicon layer, institute
It is silicon nitride layer to state supporting layer.
Preferably, in step 2), 1 μm~1.5 μm of the total height of the sacrifice layer and the supporting layer；First material
Total number of plies of layer and the second material layer is more than 15 layers.
Preferably, step 4) comprises the following steps：
The supporting layer and the sacrifice layer 4-1) are etched using dry etch process according to the Patterned masking layer, with
The through hole of up/down perforation is formed in the supporting layer and the sacrifice layer, the through hole exposes the pad；
The side wall of the through hole 4-2) is etched using wet-etching technology according to the Patterned masking layer, to obtain side wall
Corrugated or rectangular toothed the electric capacity hole.
Preferably, step 4-1) and step 4-2) between also including the use of DHF (diluted hydrofluoric acid) solution to the through hole
The step of side wall is cleaned, to remove the silicon oxide layer on the polysilicon layer surface.
Preferably, the supporting layer formed in step 2) includes top supporting layer and intermediary's supporting layer, and the top support
Layer is the top layer of the structure obtained in step 2), and intermediary's support interlayer is located in the sacrifice layer and is located at the top support
Between layer and the Semiconductor substrate.
Preferably, step 6) comprises the following steps：
6-1) in forming the first opening in the supporting layer positioned at top layer, first opening exposes two layers of branch
Support the sacrifice layer between layer；
6-2) according to the described first opening, the sacrifice between two layers of supporting layer is removed using wet-etching technology
Layer；
6-3) in another supporting layer formed second opening, it is described second opening expose positioned at the supporting layer with
The sacrifice layer between the Semiconductor substrate；
6-4) according to the described second opening, removed using wet-etching technology and served as a contrast positioned at the supporting layer and the semiconductor
The sacrifice layer between bottom.
Preferably, step 6-2) and step 6-3) between be also included in the upper surface of the supporting layer positioned at top layer and deposit
The step of support layer material, it will be thickened positioned at the supporting layer of top layer.
Preferably, step 6-1) in, first opening only overlaps with an electric capacity hole, or described in one
First opening overlaps with multiple electric capacity holes simultaneously；Step 6-2) in, one it is described second opening only with the electric capacity
Hole overlaps, or first opening overlaps with multiple electric capacity holes simultaneously.
Preferably, in step 4), the maximum gauge in the electric capacity hole of formation is 1.05~1.2 times of its minimum diameter.
The utility model also provides a kind of array of capacitors structure, and the array of capacitors structure setting is in Semiconductor substrate
On, include in the Semiconductor substrate formed with multiple pads in internal memory structure of arrays, the array of capacitors structure：
Lower electrode layer, with the contact pads, the cross sectional shape of the lower electrode layer is that side wall is in wavy or rectangular teeth
Shape it is U-shaped；
Capacitor dielectric layer, it is covered in inner surface and the outer surface of the lower electrode layer；And
Upper electrode layer, it is covered in the outer surface of the capacitor dielectric layer.
Preferably, the array of capacitors also includes top supporting layer, positioned at the mouth periphery of the bottom electrode, and perpendicular to
The U-shaped side wall bearing of trend of the bottom electrode.
Preferably, the array of capacitors also includes intermediary's supporting layer, is served as a contrast positioned at the top supporting layer and the semiconductor
Between bottom, the minimum outer diameter of the lower electrode layer is defined by the bore size of the top supporting layer and intermediary's supporting layer.
Preferably, the maximum outside diameter of the lower electrode layer is 1.05~1.2 times of its minimum outer diameter.
The utility model also provides a kind of semiconductor memory device junction structure, and the semiconductor memory device junction structure is included as above
State the array of capacitors structure described in either a program.
The utility model also provides a kind of array of capacitors structure, and the array of capacitors structure setting is in Semiconductor substrate
On, include in the Semiconductor substrate formed with multiple pads in internal memory structure of arrays, the array of capacitors structure：
Lower electrode layer, with the contact pads, the cross sectional shape of the lower electrode layer is U-shaped, the side of the lower electrode layer
Wall has the perpendicular aperture portion that an at least borehole enlargement portion is connected the borehole enlargement portion with several；
Top supporting layer, extend positioned at the mouth periphery of the lower electrode layer, and perpendicular to the U-shaped side wall of the lower electrode layer
Direction, the perpendicular aperture portion are located at least between the top supporting layer and the borehole enlargement portion, so that the borehole enlargement portion
Edge Distance described in top supporting layer produce a gap；
Capacitor dielectric layer, it is covered in inner surface and the outer surface of the lower electrode layer；And
Upper electrode layer, it is covered in the outer surface of the capacitor dielectric layer.
Preferably, the array of capacitors structure also includes intermediary's supporting layer, is partly led with described positioned at the top supporting layer
Between body substrate, the external diameter of the perpendicular aperture portion is defined by the bore size of the top supporting layer and intermediary's supporting layer.
Preferably, the borehole enlargement portion is between the top supporting layer and intermediary's supporting layer.
Preferably, the borehole enlargement portion is between intermediary's supporting layer and Semiconductor substrate.
Preferably, the external diameter in the borehole enlargement portion is 1.05~1.2 times of the external diameter of the perpendicular aperture portion.
As described above, array of capacitors structure of the present utility model, has the advantages that：Electric capacity of the present utility model
Side wall is corrugated or the electric capacity hole of rectangular toothed by preparing for the manufacture method of device array structure, can be according to the electric capacity hole
Prepare that surface profile is corrugated or the bottom electrode plate of rectangular toothed, capacitor dielectric layer and electric pole plate, do not increasing electric capacity
, i.e., can be with the table of significant increase electric capacity in the case of the electric capacity hole that need not prepare very high-aspect-ratio in the case of device height
Area, so as to increase electric capacity.
Brief description of the drawings
Fig. 1 to Fig. 6 is shown as preparing the structural representation that DRAM each step is presented in the prior art.
Fig. 7 is shown as the flow chart for preparing array of capacitors structure provided in the utility model embodiment one.
The manufacture method that Fig. 8~Figure 17 is shown as the array of capacitors structure provided in the utility model embodiment one respectively walks
Suddenly the structural representation presented.
Figure 18 is shown as the structural representation of the array of capacitors structure provided in the utility model embodiment four.
Reference numerals explanation
11 Semiconductor substrates
111 pads
12 dielectric layers
13 supporting layers
14 Patterned masking layers
15 electric capacity holes
16 lower electrode layers
17 capacitor dielectric layers
18 upper electrode layers
21 Semiconductor substrates
211 pads
22 sacrifice layers
221 first material layers
222 second material layers
231 top supporting layers
232 intermediary's supporting layers
24 Patterned masking layers
241 perforates
25 electric capacity holes
251 through holes
26 lower electrode layers
261 lower electrode material layers
262 perpendicular aperture portions
263 borehole enlargement portions
27 capacitor dielectric layers
28 upper electrode layers
d1The maximum gauge in electric capacity hole
d2The minimum diameter in electric capacity hole
D1The maximum outside diameter of lower electrode layer
D2The minimum outer diameter of lower electrode layer
D3The external diameter in borehole enlargement portion
D4The external diameter of perpendicular aperture portion
Embodiment
Illustrate embodiment of the present utility model below by way of specific instantiation, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the present utility model easily.The utility model can also be by addition
Different embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints with answering
With, without departing from it is of the present utility model spirit under carry out various modifications or alterations.
Refer to Fig. 7~Figure 17.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though when the component relevant with the utility model is only shown in diagram rather than being implemented according to reality
Component count, shape and size are drawn, and it is actual when implementing form, quantity and the ratio of each component can be a kind of changing arbitrarily
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Referring to Fig. 7, the present embodiment provides a kind of manufacture method of array of capacitors structure, the array of capacitors
The manufacture method of structure comprises the following steps：
1) semi-conductive substrate is provided, formed with multiple pads in internal memory structure of arrays in the Semiconductor substrate；
2) sacrifice layer and supporting layer being alternately superimposed on are formed in the upper surface of the Semiconductor substrate, wherein, the sacrifice
Layer includes the first material layer and second material layer being alternately superimposed on, and the first material layer is with the second material layer at same a moment
There is different etch rates in erosion processing procedure；
3) upper surface of the structure obtained in step 2) forms the Patterned masking layer with perforate, the pattern mask
Perforate in layer needs position and the shape in the electric capacity hole to be formed after defining；
4) supporting layer and the sacrifice layer are etched according to the Patterned masking layer, with the supporting layer and described
Formation side wall is corrugated in sacrifice layer or the electric capacity hole of rectangular toothed, the electric capacity hole expose the pad；
5) in forming lower electrode layer in the electric capacity hole；
6) sacrifice layer is removed；
7) the capacitor dielectric layer of the covering lower electrode layer is formed in the inner surface of the lower electrode layer and outer surface；And
8) upper electrode layer of the covering capacitor dielectric layer is formed in the outer surface of the capacitor dielectric layer.
In step 1), S1 steps and Fig. 8 in Fig. 7 are referred to, there is provided semi-conductive substrate 21, the Semiconductor substrate
Formed with multiple pads 211 in internal memory structure of arrays on 21.
As an example, include in the Semiconductor substrate 21 formed with memory array structure, the memory array structure
Multiple pads 211.The memory array structure also includes transistor character line (Word line) and bit line
(Bitline), the pad 211 is electrically connected with the transistor source in the memory array structure.
As an example, the pad 211 can with but be not limited only in six square arrays arrange, with the capacitor battle array subsequently made
The arrangement of array structure is corresponding.
Isolated between the pad 211 by wall, the material of the wall can be silicon nitride (SiN),
Silica (SiO2), aluminum oxide (Al2O3) in any one or any two or more combinations, in the present embodiment, between described
The material selection of interlayer is SiN.
In step 2), S2 steps and Fig. 9 in Fig. 7 are referred to, is formed and handed in the upper surface of the Semiconductor substrate 21
For stacked sacrifice layer 22 and supporting layer, wherein, the sacrifice layer 22 includes the material of first material layer 221 and second being alternately superimposed on
The bed of material 222, the first material layer 221 have different etching speed from the second material layer 222 in same etching processing procedure
Rate.
As an example, using atom layer deposition process (Atomic Layer Deposition) or chemical vapour deposition work
Skill (Chemical Vapor Deposition) forms the sacrifice layer 22 and supporting layer, the sacrifice layer 22 and the support
The whole height of layer can be 1 μm~1.5 μm.
As an example, the sacrifice layer 22 is different from the material of the supporting layer, and it is sacrificial described in same etching processing procedure
The etch rate of domestic animal layer 22 is different from the etch rate of the supporting layer, is embodied in same etching processing procedure, the sacrifice
The etch rate of layer 22 is far longer than the etch rate of the supporting layer so that when the sacrifice layer 22 is completely removed, institute
Supporting layer is stated almost to be fully retained.
As an example, in same etching processing procedure, the etch rate of the first material layer 221 can be much smaller than described the
The etch rate of two material layers 222, is embodied in, it is described etching processing procedure include hole formation step with and subsequent hole cut
Facial contour modification step, hole formation step can use dry etching, and hole cross section profile modification step can use wet etching
Or dry etching, in the same corrosive liquid of wet etching, the etch rate of the first material layer 221 is much smaller than described second
The etch rate of material layer 222 so that entered using corrosive liquid to the first material layer 221 and the second material layer 222
During row corrosion, the lateral encroaching removal rate of the first material layer 221 is (i.e. along the length direction of the first material layer 221
Removal rate) much smaller than the second material layer 222 laterally remove speed (i.e. along the length of the second material layer 222
The removal rate in direction).Preferably, in the present embodiment, the first material layer 221 can be silicon oxide layer, second material
The bed of material 222 can be polysilicon layer, and the supporting layer can be silicon nitride layer.
As an example, the number of plies of the first material layer 221 and the second material layer 222 can according to be actually needed into
Row setting, it is preferable that in the present embodiment, total number of plies of the first material layer 221 and the second material layer 222 is more than 15
Layer, and ensure that there is the first material layer 221 of total number of plies more than 15 layers and the second material layer in 1 μm of height
222.The number of plies of the supporting layer can be set according to being actually needed, it is preferable that in the present embodiment, the layer of the supporting layer
Number is two layers, and the top layer of structure that the step obtains is one layer of supporting layer.
Because the first material layer 221 and the second material layer 222 have different quarters in same etching processing procedure
Speed is lost, side wall can be formed when subsequently forming electric capacity hole in the first material layer 221 and the second material layer 222
For the electric capacity hole on scraggly surface.
The first material layer 221 and the second material layer 222 are as the sacrifice layer 22 during subsequent technique
It can be removed, and the supporting layer is used for the first material layer 221 and the second material layer 222 during subsequent technique
Support frame is used as after being removed, due to embodiment adds the support frame, can not only greatly improve follow-up making
The mechanical strength of structure during capacitor, it can more avoid destroying to caused by capacitor during subsequent technique (such as grinding etc.).
As an example, the supporting layer includes top supporting layer 231 and intermediary's supporting layer 232, and the top supporting layer 231 is
The top layer of the structure obtained in step 2), intermediary's support interlayer 232 are located in the sacrifice layer 22 and are located at the topmast
Support between layer 231 and the Semiconductor substrate 21.
In step 3), S3 steps and Figure 10 in Fig. 7 are referred to, tool is formed in the upper surface for the structure that step 2) obtains
There is a Patterned masking layer 24 of perforate 241, the perforate 241 in the Patterned masking layer 24 needs the electric capacity to be formed after defining
The position in hole and shape.
As an example, first, photoresist is formed in the upper surface for the structure that step 2) obtains as mask layer, certainly,
The mask layer (for example, silicon nitride hard mask layer etc.) of other materials can also be formed in other examples；Then, using photoetching work
Skill is graphical by the mask layer, to obtain having the Patterned masking layer 24 of the perforate 241.
As an example, the opening 241 can be arranged along the surface of the Patterned masking layer 24 in six square arrays.
In step 4), S4 steps and Figure 11 to Figure 13 in Fig. 7 are referred to, is etched according to the Patterned masking layer 24
The supporting layer and the sacrifice layer 22, to be formed in the supporting layer and the sacrifice layer 22, side wall is corrugated or rectangle
The electric capacity hole 25 of dentation, the electric capacity hole 25 expose the pad 211.
As an example, step 4) comprises the following steps：
The supporting layer and the sacrifice layer 4-1) are etched using dry etch process according to the Patterned masking layer 24
22, to form the through hole 251 of up/down perforation in the supporting layer and the sacrifice layer 22, the through hole 251 exposes described
Pad 211, as shown in figure 11；
4-2) NH is used according to the Patterned masking layer 244OH or TMAH solution etch the side wall of the through hole 251, by
In in same etching processing procedure, the etch rate of the first material layer 221 can be much smaller than the quarter of the second material layer 222
Speed is lost, during corrosion, the speed that the second material layer 222 laterally removes is much larger than the first material layer 221
The speed laterally removed, can obtain that side wall is corrugated or the electric capacity hole 25 of rectangular toothed, as shown in FIG. 12 and 13,
Wherein, Tu12Zhong, the side wall in the electric capacity hole 25 is corrugated, Tu13Zhong, the rectangular dentation of side wall in the electric capacity hole 25.I.e.
The electric capacity hole 25 includes perpendicular aperture portion and several borehole enlargement portions being connected with the perpendicular aperture portion；In the present embodiment,
It is in contact positioned at the borehole enlargement portion of the top with the top supporting layer 231.
As an example, when the second material layer is polysilicon layer, after through hole 251 are formed, the through hole 251
The part polysilicon layer can be exposed, the polysilicon layer of exposure can be oxidized in atmosphere forms one layer of oxygen on its surface
SiClx layer, now, step 4-1) and step 4-2) between also including the use of DHF solution (hydrofluoric acid containing solution) to the through hole
The step of 251 side wall is cleaned, to remove the silicon oxide layer on the polysilicon layer surface, to ensure step 4-2) in
NH4OH or TMAH solution can carry out lateral encroaching to the polysilicon layer.
As an example, the maximum gauge d in the electric capacity hole 25 formed1For its minimum diameter d21.05~1.2 times.
In step 5), S5 steps and Figure 14 in Fig. 7 are referred to, in formation lower electrode layer 26 in the electric capacity hole 25.
As an example, first, sunk using atom layer deposition process (Atomic Layer Deposition) or chemical evapn
Side wall and bottom of the product technique (Chemical Vapor Deposition) in the electric capacity hole 25, and the institute positioned at top layer
The upper surface deposition lower electrode material layer 261 of supporting layer is stated, the lower electrode material layer 261 includes metal nitride and metallic silicon
The compound that one or both of compound is formed, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium
Silicide), nickle silicide (Titanium Silicide), silicon titanium nitride (TiSixNy)；Then, then using etching technics remove
The lower electrode material layer 261 positioned at the upper surface of the supporting layer of top layer, reservation positioned at the side in the electric capacity hole 25
Wall and the lower electrode material layer 261 of bottom are the lower electrode layer 26.
The side wall of the lower electrode layer 25 has perpendicular aperture portion and several holes being connected with the perpendicular aperture portion
Footpath expansion section；In the present embodiment, it is in contact positioned at the borehole enlargement portion of the top with the top supporting layer 231.
It should be noted that the knot that the side wall in the homogeneous electric capacity holes 25 of Figure 14 and follow-up Figure 15 to Figure 17 is corrugated
Structure is as example.
In step 6), S6 steps and Figure 15 in Fig. 7 are referred to, removes the sacrifice layer 22.
As an example, step 6) comprises the following steps：
6-1) in forming the first opening (not shown) in the supporting layer positioned at top layer, first opening exposes two
The sacrifice layer 22 between the layer supporting layer；
6-2) according to the described first opening, the sacrifice between two layers of supporting layer is removed using wet-etching technology
Layer 22；Exemplified by the top layer of the sacrifice layer 22 to be located in this example between two layers of supporting layer is polysilicon layer, first make
Use NH4OH or TMAH solution remove the polysilicon layer positioned at top layer, reuse hydrofluoric acid removal and are located at this layer of polycrystalline
Silicon oxide layer below silicon layer, so replaces successively, until removing the sacrifice layer 22 between two layers of supporting layer completely；
6-3) in the opening of formation second in another supporting layer (supporting layer i.e. in the sacrifice layer 22)
(not shown), second opening expose the sacrifice layer between the supporting layer and the Semiconductor substrate 11
22；
6-4) according to the described second opening, removed using wet-etching technology and served as a contrast positioned at the supporting layer and the semiconductor
The sacrifice layer 22 between bottom 11；With described sacrificial between the supporting layer and the Semiconductor substrate 11 in this example
The top layer of domestic animal layer 22 be polysilicon layer exemplified by, first using NH4OH or TMAH solution remove the polysilicon layer positioned at top layer, then
The silicon oxide layer below this layer of polysilicon layer is removed using hydrofluoric acid, is so replaced successively, until removing institute completely
State the sacrifice layer 22 between supporting layer and the Semiconductor substrate 11.
As an example, step 6-2) and step 6-3) between be also included in the upper surface of the supporting layer positioned at top layer and sink
The step of product support layer material, it will be thickened positioned at the supporting layer of top layer.This is due in step 6-2) during, position
A part can be removed in the supporting layer of top layer, in order to prevent being located at the supporting layer quilt of top layer during subsequent corrosion
Cut through, and ensure that the supporting layer positioned at top layer has enough support strengths, it is necessary in step 6-2) and step 6-3)
Between set up in the upper surface depositing support layer material of the supporting layer positioned at top layer the step of.
As an example, step 6-1) in, first opening is only overlapping with an electric capacity hole 25, or one
First opening is simultaneously overlapping with multiple electric capacity holes 25；Step 6-2) in, one it is described second opening only with an institute
It is overlapping to state electric capacity hole 25, or first opening is simultaneously overlapping with multiple electric capacity holes 25.
In step 7), S7 steps and Figure 16 in Fig. 7 are referred to, inner surface and outer surface in the lower electrode layer 26
Form the capacitor dielectric layer 27 for covering the lower electrode layer 26.
As an example, it is high K dielectric material that the material of the capacitor dielectric layer 27, which can be selected, to improve unit area electricity
The capacitance of container, it includes one kind in ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or above-mentioned material forms group
Two or more formed laminations in group.
In step 8), S8 steps and Figure 17 in Fig. 7 are referred to, in the capacitor dielectric, 27 outer surface, which is formed, to be covered
Cover the upper electrode layer 28 of the capacitor dielectric layer 27.
As an example, the material of the upper electrode layer 28 can include tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon,
One kind or above-mentioned material in p-type polysilicon form two or more the formed laminations in group.
Embodiment two
Incorporated by reference to embodiment one with continued reference to Figure 17, the present embodiment also provides a kind of array of capacitors structure, the electric capacity
Device array structure is manufactured by the manufacture method described in embodiment one and obtained, and the array of capacitors structure setting is in described half
On conductor substrate 21, formed with multiple pads in internal memory structure of arrays, the capacitor battle array in the Semiconductor substrate 21
Array structure includes：Lower electrode layer 26, the lower electrode layer 26 contact with the pad 211；The section shape of the lower electrode layer 26
Shape be side wall in wavy or rectangular toothed U-shaped, i.e., the cross sectional shape of described lower electrode layer 26 is U-shaped, and the bottom electrode
26 side wall is in wavy or rectangular toothed；Capacitor dielectric layer 27, the capacitor dielectric layer 27 are covered in the lower electrode layer 26
Inner surface and outer surface；And upper electrode layer 28, the Top electrode 28 are covered in the outer surface of the capacitor dielectric layer 27.
As an example, include in the Semiconductor substrate 21 formed with memory array structure, the memory array structure
Multiple pads 211.The memory array structure also includes transistor character line (Word line) and bit line
(Bitline), the pad 211 is electrically connected with the transistor source in the memory array structure.
As an example, the pad 211 can with but be not limited only in six square arrays arrange, with the capacitor battle array subsequently made
The arrangement of array structure is corresponding.
Isolated between the pad 211 by wall, the material of the wall can be silicon nitride (SiN),
Silica (SiO2), aluminum oxide (Al2O3) in any one or any two or more combinations, in the present embodiment, between described
The material selection of interlayer is SiN.
As an example, the cross sectional shape of the lower electrode layer 26 is that side wall is U-shaped in wavy or rectangular toothed right angle.Institute
Stating lower electrode layer 26 includes the compound that one or both of metal nitride and metal silicide are formed, such as titanium nitride
(Titanium Nitride), titanium silicide (Titanium Silicide), nickle silicide (Titanium Silicide), silicon nitridation
Titanium (TiSixNy).
As an example, the maximum outside diameter D of the lower electrode layer 261For its minimum outer diameter D21.05~1.2 times.
As an example, the array of capacitors structure also includes top supporting layer 231, the top supporting layer 231 is positioned at described
The mouth periphery of lower electrode layer 26, and perpendicular to the U-shaped side wall bearing of trend of the lower electrode layer 26.
As an example, the array of capacitors structure also includes intermediary's supporting layer 232, intermediary's supporting layer 232 is located at
Between the top supporting layer 231 and the Semiconductor substrate 21, the minimum outer diameter of the lower electrode layer 26 is by the top supporting layer
231 and the bore size of intermediary's supporting layer 232 define.
As an example, the material of the material of the top supporting layer 231 and intermediary's supporting layer 232 can be silicon nitride
Layer.
As an example, the capacitor dielectric layer 27 is high-k dielectric layer, to improve the capacitance of unit-area capacitance device, its
The two or more institutes in group are formed including one kind in ZrOx, HfOx, ZrTiOx, RuOx, SbOx, AlOx or above-mentioned material
The lamination of formation；The height of the array of capacitors is 1 μm~1.5 μm.
As an example, the material of the upper electrode layer 28 can include tungsten, titanium, nickel, aluminium, platinum, titanium nitride, N-type polycrystalline silicon,
One kind or above-mentioned material in p-type polysilicon form two or more the formed laminations in group.
Embodiment three
The present embodiment also provides a kind of semiconductor memory device junction structure, and the semiconductor memory device junction structure is included as implemented
Array of capacitors structure described in example two, the concrete structure of the array of capacitors structure refer to embodiment two, herein not
Tire out again and state.
As an example, the semiconductor memory device junction structure can be but be not limited only to dynamic RAM (DRAM).
Example IV
Figure 18 is referred to, the utility model also provides a kind of array of capacitors structure, the array of capacitors structure setting
In in Semiconductor substrate 21, formed with multiple pads 211 in internal memory structure of arrays, the electricity in the Semiconductor substrate 21
Vessel array structure includes：Lower electrode layer 26, the lower electrode layer 26 contact with the pad 211, the lower electrode layer 26
Cross sectional shape is U-shaped, and there is the side wall of the lower electrode layer 26 an at least borehole enlargement portion 263 to be connected the aperture with several
The perpendicular aperture portion 262 of expansion section 263；Top supporting layer 231, the top supporting layer 231 are located at outside the opening of the lower electrode layer 26
Enclose, and the top support is located at least in perpendicular to the U-shaped side wall bearing of trend of the lower electrode layer 26, the perpendicular aperture portion 262
Between layer 231 and the borehole enlargement portion 263, so that top supporting layer 231 described in the Edge Distance in the borehole enlargement portion 263 produces
A raw gap L；Capacitor dielectric layer 27, the capacitor dielectric layer 27 are covered in inner surface and the outer surface of the lower electrode layer 26；
And upper electrode layer 28, the upper electrode layer 28 are covered in the outer surface of the capacitor dielectric layer 27.The borehole enlargement portion 263
Top supporting layer 231 described in Edge Distance, which produces a gap L, to be helped to use during the array of capacitors structure is prepared
Etching liquid removes sacrifice layer in the part of the aperture perimeters of the top supporting layer 231, and the gap L can be as described in embodiment one
The thickness in monolayer definition of first material layer.
As an example, the array of capacitors structure also includes intermediary's supporting layer 232, intermediary's supporting layer 232 is located at
Between the top supporting layer 231 and the Semiconductor substrate 21, the external diameter of the perpendicular aperture portion 262 is by the top supporting layer 231
Defined with the bore size of intermediary's supporting layer 232.
In one example, the borehole enlargement portion 263 is only located at the top supporting layer 231 and intermediary's supporting layer 232
Between, i.e., there is no the borehole enlargement portion 263 between intermediary support 232 and the Semiconductor substrate 21.
In another example, the borehole enlargement portion 263 be only located at intermediary's supporting layer 232 and Semiconductor substrate 21 it
Between, i.e., there is no the borehole enlargement portion 263 between the top supporting layer 231 and intermediary's supporting layer 232.
In another example, as shown in figure 18, the borehole enlargement portion 263 be located at the top supporting layer 231 with it is described in
Between Jie's supporting layer 232 and between intermediary's supporting layer 232 and Semiconductor substrate 21.
As an example, the outer diameter D in the borehole enlargement portion 2633For the outer diameter D of the perpendicular aperture portion 26241.05~1.2
Times.
In summary, array of capacitors structure of the present utility model, the manufacture method of the array of capacitors structure include
Following steps：1) semi-conductive substrate is provided, formed with multiple pads in internal memory structure of arrays in the Semiconductor substrate；
2) sacrifice layer and supporting layer being alternately superimposed on are formed in the upper surface of the Semiconductor substrate, wherein, the sacrifice layer includes handing over
For stacked first material layer and second material layer, the first material layer is with the second material layer in same etching processing procedure
With different etch rates；3) upper surface of the structure obtained in step 2) forms the Patterned masking layer with perforate, institute
State the position that the electric capacity hole to be formed is needed after the perforate in Patterned masking layer defines and shape；4) graphically covered according to described
Film layer etches the supporting layer and the sacrifice layer, with formed in the supporting layer and the sacrifice layer side wall it is corrugated or
The electric capacity hole of rectangular toothed, the electric capacity hole expose the pad；5) in forming lower electrode layer in the electric capacity hole；6) remove
The sacrifice layer；7) the capacitor dielectric layer of the covering lower electrode layer is formed in the inner surface of the lower electrode layer and outer surface；
And 8) upper electrode layer of the covering capacitor dielectric layer is formed in the outer surface of the capacitor dielectric layer.Electric capacity of the present utility model
Side wall is corrugated or the electric capacity hole of rectangular toothed by preparing for the manufacture method of device array structure, can be according to the electric capacity hole
Prepare that surface profile is corrugated or the bottom electrode plate of rectangular toothed, capacitor dielectric layer and electric pole plate, do not increasing electric capacity
, i.e., can be with the table of significant increase electric capacity in the case of the electric capacity hole that need not prepare very high-aspect-ratio in the case of device height
Area, so as to increase electric capacity.
Above-described embodiment only illustrative principle of the present utility model and its effect are new not for this practicality is limited
Type.Any person skilled in the art can all be carried out without prejudice under spirit and scope of the present utility model to above-described embodiment
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the essence disclosed in the utility model
God and all equivalent modifications completed under technological thought or change, should be covered by claim of the present utility model.
Claims (10)
1. a kind of array of capacitors structure, it is characterised in that the array of capacitors structure setting is described in Semiconductor substrate
Include in Semiconductor substrate formed with multiple pads in internal memory structure of arrays, the array of capacitors structure：
Lower electrode layer, with the contact pads, the cross sectional shape of the lower electrode layer is that side wall is in wavy or rectangular toothed U
Type；
Capacitor dielectric layer, it is covered in inner surface and the outer surface of the lower electrode layer；And
Upper electrode layer, it is covered in the outer surface of the capacitor dielectric layer.
2. array of capacitors structure according to claim 1, it is characterised in that：The array of capacitors also includes top support
Layer, positioned at the mouth periphery of the lower electrode layer, and perpendicular to the U-shaped side wall bearing of trend of the lower electrode layer.
3. array of capacitors structure according to claim 2, it is characterised in that：The array of capacitors also includes intermediary's branch
Layer is supportted, between the top supporting layer and the Semiconductor substrate, the minimum outer diameter of the lower electrode layer is by the top support
The bore size of layer and intermediary's supporting layer defines.
4. according to the array of capacitors structure described in claim 1,2 or 3, it is characterised in that：The maximum of the lower electrode layer is outer
Footpath is 1.05~1.2 times of its minimum outer diameter.
5. a kind of semiconductor memory device junction structure, it is characterised in that the semiconductor memory device junction structure includes such as claim 1
Described array of capacitors structure.
6. a kind of array of capacitors structure, it is characterised in that the array of capacitors structure setting is described in Semiconductor substrate
Include in Semiconductor substrate formed with multiple pads in internal memory structure of arrays, the array of capacitors structure：
Lower electrode layer, with the contact pads, the cross sectional shape of the lower electrode layer is U-shaped, and the side wall of the lower electrode layer has
There is the perpendicular aperture portion that an at least borehole enlargement portion is connected the borehole enlargement portion with several；
Top supporting layer, positioned at the mouth periphery of the lower electrode layer, and perpendicular to the U-shaped side wall extension side of the lower electrode layer
To, the perpendicular aperture portion is located at least between the top supporting layer and the borehole enlargement portion, so that the borehole enlargement portion
Top supporting layer described in Edge Distance produces a gap；
Capacitor dielectric layer, it is covered in inner surface and the outer surface of the lower electrode layer；And
Upper electrode layer, it is covered in the outer surface of the capacitor dielectric layer.
7. array of capacitors structure according to claim 6, it is characterised in that also including intermediary's supporting layer, positioned at described
Between top supporting layer and the Semiconductor substrate, the external diameter of the perpendicular aperture portion is by the top supporting layer and intermediary's supporting layer
Bore size define.
8. array of capacitors structure according to claim 7, it is characterised in that the borehole enlargement portion is located at the topmast
Support between layer and intermediary's supporting layer.
9. array of capacitors structure according to claim 7, it is characterised in that the borehole enlargement portion is located at the intermediary
Between supporting layer and Semiconductor substrate.
10. the array of capacitors structure according to any one of claim 6 to 9, it is characterised in that the borehole enlargement portion
External diameter be the perpendicular aperture portion 1.05~1.2 times of external diameter.
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| CN201721178000.6U CN207165563U (en) | 2017-09-14 | 2017-09-14 | Array of capacitors structure |
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| CN201721178000.6U CN207165563U (en) | 2017-09-14 | 2017-09-14 | Array of capacitors structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634047A (en) * | 2017-09-14 | 2018-01-26 | 睿力集成电路有限公司 | Array of capacitors structure and its manufacture method |
| CN113764580A (en) * | 2020-06-04 | 2021-12-07 | 长鑫存储技术有限公司 | Double-sided capacitor structure and forming method thereof |
| WO2024000695A1 (en) * | 2022-06-27 | 2024-01-04 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
-
2017
- 2017-09-14 CN CN201721178000.6U patent/CN207165563U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634047A (en) * | 2017-09-14 | 2018-01-26 | 睿力集成电路有限公司 | Array of capacitors structure and its manufacture method |
| CN113764580A (en) * | 2020-06-04 | 2021-12-07 | 长鑫存储技术有限公司 | Double-sided capacitor structure and forming method thereof |
| CN113764580B (en) * | 2020-06-04 | 2023-09-12 | 长鑫存储技术有限公司 | Double-sided capacitor structure and forming method thereof |
| WO2024000695A1 (en) * | 2022-06-27 | 2024-01-04 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method therefor |
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Effective date of registration: 20181008 Address after: 230601 room 630, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee after: Changxin Storage Technology Co., Ltd. Address before: 230000 room 526, Hai Heng mansion 6, Cui Wei Road, Hefei economic and Technological Development Zone, Anhui Patentee before: Ever power integrated circuit Co Ltd |