CN108122833A - 制作半导体装置的方法 - Google Patents

制作半导体装置的方法 Download PDF

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CN108122833A
CN108122833A CN201711103608.7A CN201711103608A CN108122833A CN 108122833 A CN108122833 A CN 108122833A CN 201711103608 A CN201711103608 A CN 201711103608A CN 108122833 A CN108122833 A CN 108122833A
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dielectric layer
metal
groove
layer
semiconductor device
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CN108122833B (zh
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陈志良
庄正吉
赖志明
吴佳典
杨超源
曾健庭
萧***
刘如淦
林威呈
周雷峻
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种自对准通孔及利用由双重沟槽约束的自对准工艺形成所述通孔来制作半导体装置的方法。所述方法包括形成第一沟槽及在所述第一沟槽中沉积第一金属。此后，所述工艺包括在第一金属之上沉积介电层，使得所述介电层的顶表面处于与第一沟槽的顶表面实质上相同的水平高度。接下来，形成第二沟槽且通过蚀刻介电层的被第一沟槽与所述第二沟槽之间的重叠区暴露出的部分来形成通孔。通孔暴露出第一金属的一部分，且在第二沟槽中沉积第二金属，使得所述第二金属电耦合到所述第一金属。

Description

制作半导体装置的方法
技术领域
本发明实施例涉及一种自对准通孔且更具体来说涉及一种利用由双重沟槽约束的自对准工艺(double-trench constrained self alignment process)制作的自对准通孔。
背景技术
半导体装置可包括若干个层。一些层可包括用于对半导体装置的各种部件进行内连的导电路径。在一些情形中，一个层中的导电路径可能需要电耦合到另一层中的导电路径。为在各层之间实现此连接，可使用通孔。
发明内容
本发明实施例的一种制作半导体装置的方法包括以下步骤。在第一介电层的第一沟槽中沉积第一金属，使得所述第一金属的顶表面低于所述第一介电层的顶表面。在所述第一金属之上沉积第二介电层以及在所述第一介电层及所述第二介电层之上沉积第三介电层。蚀刻所述第三介电层以形成第二沟槽，所述第二沟槽暴露出所述第一介电层的一部分及所述第二介电层的一部分。蚀刻所述第二介电层的所述暴露出的部分，以暴露出所述第一金属的一部分来形成通往所述第一金属的通孔。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸：
图1是说明根据一些实施例的用于制作自对准通孔的第一方法的流程图；
图2A至图2J是根据一些实施例的包括自对准通孔的半导体装置在根据针对图1所述的第一方法的各种制作阶段处的透视图；
图3A至图3L是根据一些实施例的包括自对准通孔的半导体装置在根据针对图1所述的第一方法的各种制作阶段处的剖视图；
图4是说明根据一些实施例的用于制作自对准通孔的第二方法的流程图；
图5A至图5J是根据一些实施例的包括自对准通孔的半导体装置在根据针对图4所述的第二方法的各种制作阶段处的透视图；
图6A至图6J是根据一些实施例的包括自对准通孔的半导体装置在根据针对图4所述的第二方法的各种制作阶段处的剖视图；
图7是根据一些实施例的根据针对图1所述的第一方法制作的半导体装置的一些方面的剖视图；以及
图8是根据一些实施例的根据针对图4所述的第二方法制作的半导体装置的一些方面的剖视图。
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。例如，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
半导体装置持续变小。随着装置的大小变小，各导电路径之间的距离可减小，且因此未对准容差(tolerance for misalignment)减小。因此，在一些半导体装置中，可能存在与制作得到恰当对准的通孔相关联的挑战。在一些实施方案中，未对准的通孔可能在半导体装置内引起短接(short)或电压击穿(voltage breakdown)。
本发明实施例提供一种自对准通孔及其制作方法，所述自对准通孔及其制作方法可应对现有通孔及与其相关联的制作方法的一个或多个缺点。在一些实施例中，自对准通孔可利用由双重沟槽约束的自对准制作工艺来确保通孔在半导体装置内得到恰当对准。
图1是说明根据一些实施例的制作自对准通孔的第一方法的流程图。结合图2A至图2J及图3A至图3L来论述图1，图2A至图2J及图3A至图3L是对应半导体装置在各种制作阶段处的示意图。图2A至图2J是根据一些实施例的包括自对准通孔的半导体装置在根据针对图1所述的第一方法的各种制作阶段处的透视图。图3A至图3L是根据一些实施例的包括自对准通孔的半导体装置在根据针对图1所述的第一方法的各种制作阶段处的剖视图。
所述制作工艺开始于操作101，在操作101处，提供第一介电层201。第一介电层201可为金属层间介电(inter metal dielectric，IMD)层。可接受介电层的实例包括氧化硅、碳氧化硅、碳化硅、氮化硅、碳氮化硅、氧化铝等。图2A及图3A说明第一介电层201的实例。在操作102处，蚀刻第一介电层201以形成第一沟槽202。可通过若干种工艺(例如，化学的、机械的等)中的任一种来执行所述蚀刻工艺。另外，可将第一沟槽202制作成使得第一沟槽202如图2B中所示在第一方向上延伸。图3B说明第一沟槽202的剖视图。
在操作103处，以第一金属203填充第一沟槽202。第一金属203代表半导体装置的一层(某一层)上的导电路径。可接受的用作第一金属203的金属包括铜、钴、钨、镍、其他导体材料、及其组合。如图2C及图3C中所示，第一金属203可完全填充第一沟槽202。在一些实施例中，第一金属203可能不完全填充第一沟槽202。在操作104中，移除第一金属203的一部分。如图2D及图3D中所示，所述移除第一金属203的一部分使得第一金属203的顶表面低于第一介电层201的顶表面。在一些实施例中，可通过以使得无需进行进一步蚀刻的方式在第一沟槽202中沉积所需量的第一金属203而将操作103与操作104组合成单一操作。
在操作105中，在第一金属203之上沉积第二介电层204。如图2E及图3E中所示，第二介电层204可填充第一沟槽202的其余部分，使得第二介电层204的上表面与第一介电层201的上表面齐平。在一些实施例中，第一介电层201与第二介电层204可为具有不同蚀刻敏感性(etching sensitivity)的不同材料。如以下所更详细阐释，具有不同蚀刻敏感性使得所述层可被选择性地蚀刻。在操作106中，如图2F及图3F中所示，在第二介电层及第一介电层之上沉积第三介电层205。在一些实施例中，第三介电层205与第二介电层204可为具有不同蚀刻敏感性的不同材料。在一些实施例中，第三介电层205与第一介电层201可为相同材料或可为具有不同蚀刻敏感性的不同材料。
在沉积第三介电层205之后，在操作107中，蚀刻第三介电层205以形成第二沟槽206来暴露出第一介电层201的一部分及第二介电层204的一部分。如图2G(及作为图2G的沿第二沟槽206的长度截取的剖视图的图3G)中所示，第二沟槽206可在与第一沟槽202所延伸于的第一方向不同的第二方向上延伸。在一些实施例中，第一方向与第二方向可实质上相互垂直。在操作108中，选择性地蚀刻第二介电层204的暴露出的部分以暴露出第一金属203的一部分。如以上所论述，由于第二介电层204是与第一介电层201及第三介电层205不同的材料，因此可选择性地蚀刻第二介电层204。如图2H及图3H中所示，第一介电层201在两个侧面上对第二介电材料进行限界(或约束)且第三介电层205在另两个侧面上对第二介电材料进行限界(或约束)。因此，当选择性地蚀刻第二介电层204时，所得通孔208会因由第一介电层201及第二介电层204形成的双重沟槽而在第一金属203之上自对准。
在操作109中，在第二沟槽207中沉积第二金属209、210、211，使得第二金属209、210、211电耦合到第一金属203。在一些实施例中，可在单一步骤或两个步骤中完成此工艺。图2I、图2J、图3I、及图3J说明有两个步骤的工艺。如图2I及图3I中所示，在第二沟槽207及通孔208的一部分中涂覆第二金属209。此第二金属209的一部分可为金属胶(metal glue)以帮助耦合第一金属203与第二金属。如图2J及图3J中所示，分别在第二沟槽207的其余部分及通孔208的其余部分中涂覆第二金属210及211。在一些实施例中，也可在一个步骤中涂覆第二金属209、210、211，使得无需使用单独的金属胶层。
图3K及图3L说明可向半导体装置增加第三层的方式。如图所示，可蚀刻第二金属210且可在第二金属210之上增加又一介电层212。
图4是说明根据一些实施例的用于制作自对准通孔的第二方法的流程图。结合图5A至图5J及图6A至图6J来论述图4，图5A至图5J及图6A至图6J是对应半导体装置在各种制作阶段处的示意图。图5A至图5J是根据一些实施例的包括自对准通孔的半导体装置在根据针对图4所述的第二方法的各种制作阶段处的透视图。图6A至图6J是根据一些实施例的包括自对准通孔的半导体装置在根据针对图4所述的第二方法的各种制作阶段处的剖视图。
在此第二实施例中，所述制作工艺开始于操作401，在操作401处，提供第一介电层501。如以上针对第一实施例所论述，第一介电层501可为金属层间介电(IMD)层。可接受介电层的实例包括氧化硅、碳氧化硅、碳化硅、氮化硅、碳氮化硅、氧化铝等。图5A及图6A说明第一介电层501的实例。在操作402处，蚀刻第一介电层501以形成第一沟槽502。可通过若干种工艺(例如，化学的、机械的等)中的任一种来执行所述蚀刻工艺。另外，可将第一沟槽502制作成使得第一沟槽502如图5B中所示在第一方向上延伸。图6B说明第一沟槽502的剖视图。另外，在图6B中，两个第一沟槽502是以其不完全穿过第一介电层501延伸的方式形成。
在操作403处，以第一金属503填充第一沟槽502。第一金属503(如针对第一实施例所论述)代表半导体装置的一层(某一层)上的导电路径。可接受的用作第一金属503的金属包括铜、钴、钨、镍、其他导体材料、及其组合。如图5C及图6C中所示，第一金属503可完全填充第一沟槽502。在一些实施例中，第一金属503可能不完全填充第一沟槽502。在操作404中，移除第一介电层501的一部分。如图5D及图6D中所示，所述移除第一介电层501使得第一金属503被暴露出(例如，在至少三个侧面上被暴露出)。如图5D中所示，可移除第一介电层501且仅留下第一金属503，或如图6D中所示，可将第一介电层501蚀刻成使得第一金属503留在充当介电衬底的第一介电层501上。
在操作405中，在第一金属503之上沉积第二介电层504。如图5E及图6E中所示，第二介电层504覆盖第一金属503(例如，覆盖在至少三个侧面上)。与之前的实施例中不同，此实施例中的第二介电层不被沟槽约束。在一些实施例中，第二介电层504可如图5E及图6E中所示完全覆盖第一金属503及第一介电层501。第二介电层504与第一介电层501可为具有不同蚀刻敏感性的不同材料。
在操作406中，如图5F及图6F中所示在第二介电层504及第一介电层501之上及环绕第二介电层504及第一介电层501沉积第三介电层505。在一些实施例中，第三介电层505与第二介电层504可为具有不同蚀刻敏感性的不同材料。在一些实施例中，第三介电层505与第一介电层501可为相同材料或可为具有不同蚀刻敏感性的不同材料。
在沉积第三介电层505之后，在操作407中，蚀刻第三介电层505以形成第二沟槽506来暴露出第二介电层504的一部分及第三介电层505的下部部分。如图5G(及作为图5G的沿第二沟槽506的长度截取的剖视图的图6G)中所示，第二沟槽506可在与第一沟槽502所延伸于的第一方向不同的第二方向上延伸。在一些实施例中，第一方向与第二方向可实质上相互垂直。在操作408中，选择性地蚀刻第二介电层504的暴露出的部分以暴露出第一金属503的一部分。如以上所论述，由于第二介电层504是与第一介电层501及第三介电层505不同的材料，因此可选择性地蚀刻第二介电层504。如图5H及图6H中所示，第三介电层505在所有四个侧面上对第二介电材料进行限界(或约束)。因此，当选择性地蚀刻第二介电层504时，所得通孔508会因由第三介电层505形成的双重沟槽而在第一金属503之上自对准。
在操作409中，在第二沟槽507中沉积第二金属509、510、511，使得第二金属电耦合到第一金属503。在一些实施例中，可在单一步骤或两个步骤中完成此工艺。图5I、图5J、图6I、及图6J说明有两个步骤的工艺。如图5I及图6I中所示，在沟槽507及通孔508的一部分中涂覆第二金属509。此第二金属509可为金属胶以帮助耦合第一金属503与第二金属。如图5J及图6J中所示，分别在沟槽507的其余部分及通孔508的其余部分中涂覆第二金属510及511。在一些实施例中，也可在一个步骤中涂覆第二金属509、510、511，使得无需使用单独的金属胶层。
图7是根据一些实施例的根据针对图1所述的第一方法制作的半导体装置的一些方面的剖视图。图8是根据一些实施例的根据针对图4所述的第二方法制作的半导体装置的一些方面的剖视图。
在图7中，图的右侧部分的剖视图与图3J中所示的图相同，也就是说，通孔被形成为将第一金属M0电耦合到第二金属M1。相似地，在图8中，图的右侧部分的剖视图与图5J中所示的图相同，也就是说，通孔被形成为将第一金属M0电耦合到第二金属M1。在图7及图8中，图的左侧部分说明当通孔未被形成为在所述两个导电路径的交叉部位处将第一金属M0耦合到第二金属M1的情况。如所属领域中的技术人员所容易理解，在半导体装置中，在第一层上可形成有多个导电路径且在所述第一层(上方或下方)的第二层上可形成有多个导电路径。这些导电路径可在多个位置处交叉，但并非所有导电路径均将包括用于连接来自不同层的导电路径的通孔。事实上，视半导体装置的所期望操作而定，一些交叉区域可具有通孔而另一些则可不具有通孔。具有通孔的交叉部位与不具有通孔的交叉部位之间的外观差别可参见图7及图8中的每一图。
另外，如以上所论述，第二介电层204、504可为与第一介电层201及第三介电层505不同的材料。在一些实施例中，第一金属203、503顶上的材料可具有与第一金属203、503的侧面上的材料不同的蚀刻敏感性。举例来说，如果第一金属顶上的材料具有为1的蚀刻速率，则第一金属203、503的侧面上的材料可具有小于0.5或约0.5的蚀刻速率。
重新参照图7及图8，在一些实施例中，为防止未对准及短接，通孔高度HV可介于相邻金属线之间的距离(即，金属节距)的0.2倍与0.8倍之间。举例来说，在一些实施例中，通孔高度HV可为金属节距的0.2倍、0.3倍、0.4倍、0.5倍、0.6倍、0.7倍、或0.8倍。
本文所述的一些实施例可包括一种制作半导体装置的方法，所述方法包括在第一介电层的第一沟槽中沉积第一金属，使得所述第一金属的顶表面低于所述第一介电层的顶表面。接下来，所述方法可包括在所述第一金属之上沉积第二介电层以及在所述第一介电层及所述第二介电层之上沉积第三介电层。蚀刻所述第三介电层以形成第二沟槽，所述第二沟槽暴露出所述第一介电层的一部分及所述第二介电层的一部分。接下来，蚀刻所述第二介电层的所述暴露出的部分，以暴露出所述第一金属的一部分来形成通往所述第一金属的通孔。
在一些实施例中，进一步包括在所述第二沟槽中沉积第二金属，使得所述第二金属电耦合到所述第一金属。
在一些实施例中，所述第二介电层的顶表面处于与所述第一介电层的所述顶表面实质上相同的水平高度。
在一些实施例中，所述第一介电层与所述第二介电层具有不同的蚀刻敏感性。
在一些实施例中，所述第三介电层与所述第二介电层具有不同的蚀刻敏感性。
在一些实施例中，所述第三介电层与所述第一介电层是相同的材料。
在一些实施例中，所述第一金属代表所述半导体装置的一层上的第一导电路径，且所述第二金属代表所述半导体装置的另一层上的第二导电路径，所述第二导电路径经由通过对所述第二介电层进行蚀刻而形成的所述通孔耦合到所述第一导电路径。
在一些实施例中，所述第一沟槽在第一方向上延伸，且所述第二沟槽在与所述第一方向不同的第二方向上延伸。
在一些实施例中，所述第一方向与所述第二方向实质上相互垂直。
在一些实施例中，所述第一介电层、所述第二介电层、及所述第三介电层中的至少一个是氧化硅层、碳氧化硅层、碳化硅层、氮化硅层、碳氮化硅层、或氧化铝层。
在一些实施例中，所述通孔的高度介于所述半导体装置的金属节距的0.2倍与0.8倍之间。
在一些实施例中，所述第一金属及所述第二金属是铜、钴、钨、镍、其他导体材料、及其组合中的至少一种。
本文所述的一些实施例可包括一种制作半导体装置的方法，所述方法包括：提供第一介电层；蚀刻所述第一介电层以形成第一沟槽；以及在所述第一沟槽中沉积第一金属。接着移除所述第一介电材料，且在所述第一金属之上及环绕所述第一金属沉积第二介电层。接下来，所述方法包括在所述第二介电层及所述第一金属之上及环绕所述第二介电层及所述第一金属沉积第三介电层，以及蚀刻所述第三介电层以形成第二沟槽，所述第二沟槽暴露出所述第二介电层的一部分以及所述第三介电层的下部层的一部分。蚀刻所述第二介电层的所述暴露出的部分，以暴露出所述第一金属的一部分，且在所述第二沟槽中沉积第二金属，使得所述第二金属电耦合到所述第一金属。
在一些实施例中，所述第三介电层与所述第二介电层具有不同的蚀刻敏感性。
在一些实施例中，所述第一金属代表所述半导体装置的一层上的第一导电路径，且所述第二金属代表所述半导体装置的另一层上的第二导电路径，所述第二导电路径经由通过对所述第二介电层进行蚀刻而形成的通孔耦合到所述第一导电路径。
在一些实施例中，所述第一沟槽在第一方向上延伸，且所述第二沟槽在与所述第一方向不同的第二方向上延伸。
在一些实施例中，所述第一方向与所述第二方向实质上相互垂直。
在一些实施例中，所述第一介电层、所述第二介电层、及所述第三介电层中的其中一个可以是氧化硅层、碳氧化硅层、碳化硅层、氮化硅层、碳氮化硅层、或氧化铝层。
一些实施例可包括一种制作半导体装置的方法，所述方法包括：形成第一沟槽；以及在所述第一沟槽中沉积第一金属，使得所述第一金属的顶表面低于所述第一沟槽的顶表面。接下来，所述工艺通过以下来继续进行：在所述第一金属之上沉积介电层，使得所述介电层的顶表面处于与所述第一沟槽的所述顶表面实质上相同的水平高度。形成第二沟槽且接着通过蚀刻所述介电层的被所述第一沟槽与所述第二沟槽之间的重叠区暴露出的部分来形成通孔。所述通孔暴露出所述第一金属的一部分，且在所述第二沟槽中沉积第二金属，使得所述第二金属电耦合到所述第一金属。
在一些实施例中，所述第一金属代表所述半导体装置的一层上的第一导电路径，且所述第二金属代表所述半导体装置的另一层上的第二导电路径，所述第二导电路径经由通过对所述第二介电层进行蚀刻而形成的所述通孔耦合到所述第一导电路径。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替、及变更。

Claims (1)

1.一种制作半导体装置的方法，其特征在于，包括：
在第一介电层的第一沟槽中沉积第一金属，使得所述第一金属的顶表面低于所述第一介电层的顶表面；
在所述第一金属之上沉积第二介电层；
在所述第一介电层及所述第二介电层之上沉积第三介电层；
蚀刻所述第三介电层以形成第二沟槽，所述第二沟槽暴露出所述第一介电层的一部分及所述第二介电层的一部分；以及
蚀刻所述第二介电层的所述暴露出的部分，以暴露出所述第一金属的一部分来形成通往所述第一金属的通孔。
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