CN108022835A - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
- Publication number
- CN108022835A CN108022835A CN201711038448.2A CN201711038448A CN108022835A CN 108022835 A CN108022835 A CN 108022835A CN 201711038448 A CN201711038448 A CN 201711038448A CN 108022835 A CN108022835 A CN 108022835A
- Authority
- CN
- China
- Prior art keywords
- film
- chip
- protection band
- manufacture method
- sog film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229920001721 polyimide Polymers 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 33
- 239000011521 glass Substances 0.000 claims description 9
- 238000004528 spin coating Methods 0.000 claims description 8
- 238000009832 plasma treatment Methods 0.000 claims description 7
- 239000002253 acid Substances 0.000 claims 1
- 150000003949 imides Chemical class 0.000 claims 1
- 239000007767 bonding agent Substances 0.000 abstract description 16
- 238000005516 engineering process Methods 0.000 description 11
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 8
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005336 cracking Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002466 imines Chemical class 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229920002647 polyamide Polymers 0.000 description 2
- 238000012797 qualification Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 235000011194 food seasoning agent Nutrition 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Weting (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
本发明提供一种半导体装置的制造方法,抑制在从晶片的表面剥离保护带时保护带的粘接剂残留于晶片的表面。半导体装置的制造方法包括以下步骤:在具有半导体基板和聚酰亚胺膜并且聚酰亚胺膜露出于表面的晶片上以覆盖所述聚酰亚胺膜的方式形成SOG膜;在所述SOG膜的表面粘贴保护带;对粘贴有所述保护带的晶片进行处理;以及将所述保护带从所述晶片剥离。
Description
技术领域
本说明书公开的技术涉及半导体装置的制造方法。
背景技术
专利文献1公开了如下技术:在半导体装置的制造步骤中,在晶片的表面粘贴保护带,对晶片进行处理,然后将保护带从晶片剥离。在对晶片进行处理时,通过保护带来抑制在晶片的表面产生损伤等。
在先技术文献
专利文献
专利文献1:日本特开2007-311735号公报
存在一种具有半导体基板和聚酰亚胺膜并且聚酰亚胺膜露出于表面的晶片。对于这种晶片,有时以覆盖聚酰亚胺膜的方式粘贴保护带。保护带以较高的粘接力粘贴于聚酰亚胺膜。尤其,在半导体装置的制造过程中,有时在聚酰亚胺膜的表面产生龟裂。保护带以特别高的粘接力粘贴于在表面产生龟裂的聚酰亚胺膜。因此,若以覆盖聚酰亚胺膜的方式粘贴保护带,则在晶片的处理后剥离保护带时,会产生保护带的粘接剂残留于聚酰亚胺膜的表面这样的问题。
发明内容
本说明书公开的半导体装置的制造方法包括以下步骤:在具有半导体基板和聚酰亚胺膜并且聚酰亚胺膜露出于表面的晶片上以覆盖所述聚酰亚胺膜的方式形成SOG膜;在所述SOG膜的表面粘贴保护带;对粘贴有所述保护带的晶片进行处理;以及将所述保护带从所述晶片剥离。
需要说明的是,上述的“SOG膜”是旋涂玻璃(Spin-On-Glass)膜,是指通过旋涂玻璃(Spin-On-Glass)法形成的氧化硅膜。并且,上述的“处理”是针对晶片的各种处理中的任一个,例如包括晶片的研磨、晶片的蚀刻、对晶片的离子注入、向晶片的表面的电极形成、向晶片的表面的绝缘层的形成或者它们的任意的组合等。
在该制造方法中,以覆盖聚酰亚胺膜的方式形成SOG膜,在该SOG膜上粘贴保护带。SOG膜较薄,因此通过在SOG膜的表面粘贴保护带,能够适当地保护晶片的表面。因此,在然后对晶片进行处理的步骤中,抑制在晶片的表面产生损伤。在对晶片进行处理之后,将保护带从晶片剥离。如上述那样,聚酰亚胺膜被SOG膜覆盖,在SOG膜的表面粘贴有保护带。保护带能够容易地从SOG膜剥离。因此,抑制保护带的粘接剂残留于SOG膜的表面。因此,能够抑制由于残留的粘接剂而在半导体装置的制造步骤中产生不良情况。
附图说明
图1是半导体晶片的剖视图。
图2是等离子处理后的半导体晶片的剖视图。
图3是SOG膜形成后的半导体晶片的剖视图。
图4是保护带粘贴后的半导体晶片的剖视图。
图5是感光处理后的半导体晶片的剖视图。
图6是进行了感光的SOG膜除去后的半导体晶片的剖视图。
图7是金属膜形成后的半导体晶片的剖视图。
图8是未进行感光的SOG膜除去后的半导体晶片的剖视图。
附图标记说明
10:晶片
12:半导体基板
14:Al电极
16:保护膜
18:聚酰亚胺膜
20:SOG膜
22:保护带
24:金属膜
40:凹部
具体实施方式
说明实施方式的半导体装置的制造方法。首先,准备图1所示的晶片10。晶片10具有半导体基板12、Al电极14、保护膜16和聚酰亚胺膜18。半导体基板12由硅构成。虽然未图示,但是在半导体基板12的内部形成有IGBT(Insulated Gate Bipolar Transistor:绝缘栅双极型晶体管)的构造的一部分和pn二极管的构造的一部分。Al电极14设于半导体基板12的表面。Al电极14由铝构成。在Al电极14的表面形成有凹部40。保护膜16覆盖凹部40和该凹部40的周围的Al电极14的表面。聚酰亚胺膜18覆盖保护膜16的表面。聚酰亚胺膜18露出于晶片10的表面。在未设置聚酰亚胺膜18的范围内,Al电极14露出于晶片10的表面。
首先,对晶片10的表面进行等离子处理。更详细而言,使包含氟的蚀刻气体(本实施方式中为SF4)等离子化,将Al电极14暴露于产生的等离子体中。由此,在Al电极14的表面,氟与铝结合(所谓氟终端处理)。在将Al电极14暴露于等离子体的过程中,聚酰亚胺膜18也暴露于等离子体中。当聚酰亚胺膜18暴露于等离子体中时,如图2所示,聚酰亚胺膜18的表面18a发生龟裂(粗糙化)。
接着,如图3所示,通过SOG(Spin-On-Glass)法在晶片10的表面形成氧化硅膜(即SOG膜)20。更详细而言,在使晶片10以高速旋转的状态下,将包含氧化硅的溶剂涂敷于晶片10的表面(聚酰亚胺膜18露出的表面)的中心部。于是,溶剂因离心力而向晶片10的表面整体扩展。然后,通过使溶剂干燥而在晶片10的表面整体形成SOG膜20。SOG膜20覆盖聚酰亚胺膜18的表面18a和Al电极14的表面。SOG膜20具有感光性。即,SOG膜20在受到特定的波长的光(例如g线、h线、i线等)时发生变质。SOG膜20具有400℃左右的耐热性。
接着,如图4所示,在SOG膜20的表面粘贴保护带22。保护带22在下表面侧具有粘接剂层。通过粘接剂层粘着于SOG膜20,将保护带22固定于SOG膜20。由于在聚酰亚胺膜18与保护带22之间存在SOG膜20,所以保护带22不与聚酰亚胺膜18接触。
接着,通过对半导体基板12的背侧的表面(与设有聚酰亚胺膜18等的表面相反的一侧的表面,图示省略)进行蚀刻,使半导体基板12薄板化。而且,通过向半导体基板12的背侧的表面注入p型杂质,形成IGBT的集电极区域。而且,通过向半导体基板12的背侧的表面注入n型杂质,形成pn二极管的阴极区域。在针对半导体基板12的背侧的表面的这些步骤的期间,粘贴有保护带22的一侧的晶片10的表面由保护带22保护。由此,抑制在晶片10的表面产生损伤等。
接着,如图5所示,从晶片10剥离保护带22。此时,保护带22相对于SOG膜20的粘接力并不那么高,因此能够适宜地从SOG膜20剥离保护带22。因此,保护带22的粘接剂几乎不会残留于SOG膜20的表面。由于在SOG膜20的表面几乎没有保护带22的粘接剂残留,所以几乎不会因残留的粘接剂而在此后的步骤中产生不良情况。因此,根据该制造方法,能够以较高的合格率制造半导体装置。
接着,如图5所示,以光不照到聚酰亚胺膜18上的SOG膜20且光照到其他部分的SOG膜20的方式向SOG膜20照射光。在此,照射SOG膜20感光的波长的光(例如包含g线、h线、i线等的光)。由此,使照射光的范围的SOG膜20感光(变质)。以下,将进行了感光的SOG膜20称为SOG膜20b,将未进行感光的SOG膜20(聚酰亚胺膜18上的SOG膜20)称为SOG膜20a。
接着,如图6所示,利用TMAH(Tetramethylammonium hydroxide:四甲基氢氧化铵)等显影液来除去SOG膜20b。SOG膜20a与TMAH不反应而不会被除去。因此,如图6所示,SOG膜20a残留于聚酰亚胺膜18上。
接着,如图7所示,通过溅射法等在晶片10的表面形成金属膜24。由于SOG膜20a和Al电极14露出于晶片10的表面,所以在SOG膜20a的表面和Al电极14的表面形成金属膜24。在本实施方式中,金属膜24由镍构成。由于提前对Al电极14进行了等离子处理,所以金属膜24牢固地连接于Al电极14。因此,金属膜24难以从Al电极14剥离。
接着,如图8所示,利用以NMP(n-methyl-2-pyrrolidone:N-甲基吡咯烷酮)等为主要成分的剥离液来将SOG膜20a除去。此时,在SOG膜20a的表面配置的金属膜24也被除去。因此,聚酰亚胺膜18露出于晶片10的表面。根据该方法,能够以在与Al电极14接触的范围内残留金属膜24且在聚酰亚胺膜18上不存在金属膜24的方式对金属膜24进行图案形成。在该方法中,通过使用了SOG膜20的光刻法来对金属膜24进行图案形成,因此能够高精度地对金属膜24进行图案形成。
需要说明的是,也能够以覆盖聚酰亚胺膜18的表面的方式将金属掩模固定于晶片10的表面,经由金属掩模来形成金属膜24。通过以金属掩模的开口部位于Al电极14的露出范围的上部的方式配置金属掩模,能够与图8一样选择性地在Al电极14的露出范围内形成金属膜24。然而,由于金属掩模通过磁力固定于晶片10的表面,所以在磁力不充分的部分有时金属掩模发生浮动。即,有时在金属掩模与晶片10之间产生间隙。在该情况下,有时在该间隙的部分,在金属掩模的下部的聚酰亚胺膜18的表面形成金属膜24,无法准确地对金属膜24进行图案形成。
相对于此,根据本实施方式(即使用了SOG膜20a的光刻法),不会发生上述的浮动,因此能够更准确对金属膜24进行图案形成。并且,根据本实施方式,不需要金属掩模,因此能够用更低的成本来制造半导体装置。
然后,通过形成必要的电极、绝缘层等,半导体装置完成。
如以上说明的那样,在本实施方式的制造方法中,将保护带22粘贴于SOG膜20,因此在剥离保护带22时粘接剂难以残留于SOG膜20a的表面。因此,能够抑制由残留的粘接剂引起的不良情况。并且,即便假设是粘接剂残留于SOG膜20a的表面的情况,在除去SOG膜20时粘接剂也被除去。因此,在该情况下,也能够抑制由残留的粘接剂引起的不良情况。因此,根据本实施方式的制造方法,能够以较高的合格率制造半导体装置。
并且,在本实施方式的制造方法中,SOG膜20具有感光性,将剥离保护带22后的SOG膜20作为用于对金属膜24进行图案形成的掩模来使用。由于SOG膜20具有感光性,所以能够使用光刻法。因此,能够以高精度对金属膜24进行图案形成。并且,能够将用于抑制粘接剂的残留的SOG膜20延用为掩模,因此能够削减形成用于对金属膜24进行图案形成的掩模所需要的步骤及材料。因此,根据本实施方式的制造方法,能够用较低的成本来制造半导体装置。
关于本说明书公开的技术要素,以下列述。需要说明的是,以下的各技术要素能够分别独立使用。
在本说明书公开的一例的结构中,SOG膜可以具有感光性。在该情况下,可以实施在剥离保护带之后通过使SOG膜感光而在SOG膜上形成开口部的步骤和在开口部内形成金属膜的步骤。
根据该结构,能够将具有开口部的SOG膜作为形成金属膜时的掩模来使用。在该方法中,能够通过光刻法高精度地形成金属膜。
本说明书公开的一例的制造方法可以在形成SOG膜的步骤之前还包括对聚酰亚胺膜露出的晶片的表面进行等离子处理的步骤。
需要说明的是,等离子处理是指将晶片的表面暴露于等离子体中的处理。
在该结构中,通过等离子处理而在聚酰亚胺膜的表面产生龟裂。在这样的情况下,若在聚酰亚胺膜的表面粘贴保护带,则在剥离保护带时较多的粘接剂残留于聚酰亚胺膜的表面。相对于此,通过使用SOG膜,能够防止粘接剂的残留。在该情况下,SOG膜对粘接剂的残留抑制效果更有用。
以上,详细地说明了实施方式,但是这些只是例示,并不对权利要求书进行限定。权利要求书记载的技术包含对以上例示的具体例进行各种变形、变更后的技术。本说明书或附图中说明的技术要素单独或通过各种组合而发挥技术有用性,并不受申请时权利要求记载的组合限定。并且,本说明书或附图中例示的技术同时达成多个目的,达成其中一个目的的内容本身具有技术有用性。
Claims (3)
1.一种半导体装置的制造方法,包括以下步骤:
在具有半导体基板和聚酰亚胺膜并且聚酰亚胺膜露出于表面的晶片上,以覆盖所述聚酰亚胺膜的方式形成旋涂玻璃膜;
在所述旋涂玻璃膜的表面粘贴保护带;
对粘贴有所述保护带的晶片进行处理;以及
将所述保护带从所述晶片剥离。
2.根据权利要求1所述的半导体装置的制造方法,其中,
所述旋涂玻璃膜具有感光性,
所述半导体装置的制造方法还包括以下步骤:
在将所述保护带剥离之后,通过使所述旋涂玻璃膜感光而在所述旋涂玻璃膜上形成开口部;以及
在所述开口部内形成金属膜。
3.根据权利要求1或2所述的半导体装置的制造方法,其中,
在形成所述旋涂玻璃膜的步骤之前,还包括对所述聚酰亚胺膜露出的所述晶片的表面进行等离子处理的步骤。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016-214634 | 2016-11-01 | ||
JP2016214634A JP6561966B2 (ja) | 2016-11-01 | 2016-11-01 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN108022835A true CN108022835A (zh) | 2018-05-11 |
Family
ID=62019871
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201711038448.2A Pending CN108022835A (zh) | 2016-11-01 | 2017-10-30 | 半导体装置的制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US10128162B2 (zh) |
JP (1) | JP6561966B2 (zh) |
CN (1) | CN108022835A (zh) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2561602B2 (ja) * | 1991-12-02 | 1996-12-11 | 現代電子産業株式会社 | 多層金属配線構造のコンタクトの製造方法 |
JP2006302919A (ja) * | 2005-04-15 | 2006-11-02 | Sony Corp | 面発光型半導体レーザおよびその製造方法 |
US20060273319A1 (en) * | 2005-06-03 | 2006-12-07 | Semiconductor Energy Laboratory Co., Ltd. | Integrated circuit device and manufacturing method thereof |
WO2008136158A1 (ja) * | 2007-04-24 | 2008-11-13 | Sharp Kabushiki Kaisha | 表示装置用基板、表示装置及び配線基板 |
US20120043539A1 (en) * | 2010-08-20 | 2012-02-23 | Seth Prejean | Semiconductor chip with thermal interface tape |
CN104271694A (zh) * | 2012-05-14 | 2015-01-07 | 琳得科株式会社 | 带粘接性树脂层的片和半导体装置的制造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005303218A (ja) * | 2004-04-16 | 2005-10-27 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP5352045B2 (ja) * | 2005-06-03 | 2013-11-27 | 株式会社半導体エネルギー研究所 | 集積回路装置の作製方法 |
JP4698517B2 (ja) | 2006-04-18 | 2011-06-08 | 日東電工株式会社 | 保護テープ剥離方法およびこれを用いた装置 |
JP2009021462A (ja) * | 2007-07-13 | 2009-01-29 | Disco Abrasive Syst Ltd | ウェーハの加工方法 |
JP2010062415A (ja) | 2008-09-05 | 2010-03-18 | Toyota Motor Corp | 保護テープの剥離方法、及び、半導体装置の製造方法 |
-
2016
- 2016-11-01 JP JP2016214634A patent/JP6561966B2/ja active Active
-
2017
- 2017-09-06 US US15/696,606 patent/US10128162B2/en not_active Expired - Fee Related
- 2017-10-30 CN CN201711038448.2A patent/CN108022835A/zh active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2561602B2 (ja) * | 1991-12-02 | 1996-12-11 | 現代電子産業株式会社 | 多層金属配線構造のコンタクトの製造方法 |
JP2006302919A (ja) * | 2005-04-15 | 2006-11-02 | Sony Corp | 面発光型半導体レーザおよびその製造方法 |
US20060273319A1 (en) * | 2005-06-03 | 2006-12-07 | Semiconductor Energy Laboratory Co., Ltd. | Integrated circuit device and manufacturing method thereof |
WO2008136158A1 (ja) * | 2007-04-24 | 2008-11-13 | Sharp Kabushiki Kaisha | 表示装置用基板、表示装置及び配線基板 |
US20100110320A1 (en) * | 2007-04-24 | 2010-05-06 | Hidehito Kitakado | Display device substrate, display device, and wiring substrate |
US20120043539A1 (en) * | 2010-08-20 | 2012-02-23 | Seth Prejean | Semiconductor chip with thermal interface tape |
CN104271694A (zh) * | 2012-05-14 | 2015-01-07 | 琳得科株式会社 | 带粘接性树脂层的片和半导体装置的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2018074068A (ja) | 2018-05-10 |
JP6561966B2 (ja) | 2019-08-21 |
US10128162B2 (en) | 2018-11-13 |
US20180122717A1 (en) | 2018-05-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105514038B (zh) | 切割半导体晶片的方法 | |
US7642629B2 (en) | Methods and apparatus for packaging integrated circuit devices | |
US7495341B2 (en) | Methods and apparatus for packaging integrated circuit devices | |
TWI539508B (zh) | 半導體裝置之製造方法及電子裝置之製造方法 | |
JP5232185B2 (ja) | 半導体装置の製造方法 | |
JP2003347441A (ja) | 半導体素子、半導体装置、及び半導体素子の製造方法 | |
JP2004055684A (ja) | 半導体装置及びその製造方法 | |
CN107221517B (zh) | 一种包覆型芯片尺寸封装结构及其封装方法 | |
US20130224910A1 (en) | Method for chip package | |
CN110838452A (zh) | 封装方法、面板组件、晶圆封装体以及芯片封装体 | |
TW201906120A (zh) | 半導體封裝件及半導體封裝件之製造方法 | |
JP4725639B2 (ja) | 半導体装置の製造方法 | |
TW201740468A (zh) | 具有高溫塗層之晶片封裝構造之製造方法 | |
JP5471064B2 (ja) | 半導体装置の製造方法 | |
JP2004349461A (ja) | 半導体装置の製造方法 | |
US8912653B2 (en) | Plasma treatment on semiconductor wafers | |
CN108022835A (zh) | 半导体装置的制造方法 | |
CN110875231A (zh) | 晶圆级封装方法及封装结构 | |
JP2007095894A (ja) | 半導体装置及びその製造方法 | |
KR20060024320A (ko) | 반도체 장치의 제조 방법 | |
JP2003229381A (ja) | 半導体装置の製造方法 | |
JP2004018964A (ja) | 半導体ウエハおよび半導体装置の製造方法 | |
KR20040025951A (ko) | 반도체 소자의 백그라인딩 방법 | |
JP2010147353A (ja) | 半導体装置の製造方法 | |
JPH0945638A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20200413 Address after: Aichi Prefecture, Japan Applicant after: DENSO Corp. Address before: TOYOTA City, Aichi Prefecture, Japan Applicant before: Toyota Motor Corp. |
|
TA01 | Transfer of patent application right | ||
AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20220429 |
|
AD01 | Patent right deemed abandoned |