CN107967041B - Multi-FPGA power-on configuration control method - Google Patents

Multi-FPGA power-on configuration control method Download PDF

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CN107967041B
CN107967041B CN201711265491.2A CN201711265491A CN107967041B CN 107967041 B CN107967041 B CN 107967041B CN 201711265491 A CN201711265491 A CN 201711265491A CN 107967041 B CN107967041 B CN 107967041B
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fpga
power supply
configuration
ldo
time
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CN107967041A (en
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余达
刘金国
周怀得
马庆军
陈佳豫
张博研
浦前帅
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/189—Power distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Logic Circuits (AREA)
  • Power Sources (AREA)

Abstract

A multi-FPGA power-on configuration control method relates to a multi-FPGA power-on configuration control method, and solves the problems that the prior multi-FPGA has insufficient power supply in the power-on configuration process, which causes the failure of partial or all FPGA configuration, and causes the resource waste when a high-power supply is used, and the like; the voltage output by the DC/DC power supply respectively supplies power to an external circuit, IO (input/output) of the FPGA and a kernel through a transmission cable and each LDO (low dropout regulator); the RC delay circuit is used for controlling the IO power supply LDO output voltage of the FPGA, the kernel power supply LDO output voltage and the program _ b enable of the FPGA; through the staggering of the loading time of each FPGA, the size of the total output current of the DC/DC can be reduced, and the utilization efficiency of the power supply is improved.

Description

Multi-FPGA power-on configuration control method
Technical Field
The invention relates to a multi-FPGA power-on configuration control method, in particular to a multi-FPGA power-on configuration control method based on aerospace application.
Background
In the power-on configuration process of the FPGA, large configuration peak current is needed; if several FPGAs are powered by the same power supply and are configured in the same time, several times of current of single chip configuration is needed, and if the current or voltage output by the power supply is insufficient, the configuration of part or all of the FPGAs fails. One solution is to use a high-power supply, and the power consumption required after successful configuration is small, and the resource waste is serious.
Disclosure of Invention
The invention provides a multi-FPGA power-on configuration control method, which aims to solve the problems that in the power-on configuration process of the existing multi-FPGA, when a power supply is insufficient, the configuration of part or all of the FPGAs fails, when a high-power supply is used, the resource is wasted and the like.
A multi-FPGA power-on configuration control method comprises an FPGA power-on configuration control system, wherein the FPGA power-on configuration control system comprises a DC/DC power supply, an external circuit, an IO power supply LDO of the FPGA, a kernel power supply LDO of the FPGA and an RC delay circuit; the voltage output by the DC/DC power supply respectively supplies power to an external circuit, IO (input/output) of the FPGA and a kernel through a transmission cable and each LDO (low dropout regulator); the RC delay circuit is used for controlling the IO power supply LDO output voltage of the FPGA, the kernel power supply LDO output voltage and the program _ b enable of the FPGA; in the process of power-on configuration control, time-sharing power-on is adopted, and the specific power-on configuration control method comprises the following steps:
step one, electrifying an external circuit; the LDO is in an output normal enable state, and the LDO starts to output voltage after the DC/DC power supply outputs the voltage;
step two, IO power supply LDO output of the FPGA is enabled;
the IO power supply LDO is controlled by the RC delay circuit, when the voltage of the RC delay circuit rises to the threshold voltage IO power supply LDO and begins to output voltage, the IO power supply LDO of the multiple FPGAs output and enable within the same delay time, and the delay time is 0.2tconfig(ii) a In the formula tconfigMaximum power supply rise time configured for the FPGA;
thirdly, the kernel of the FPGA supplies power to the LDO output to enable;
the output of the LDO powered by the kernel is controlled by the RC delay circuit, and the LDO powered by the kernel starts to output voltage after the voltage of the RC delay circuit rises to the threshold voltage;
setting n FPGAs, the enabling interval time of the kernel power supply of the n FPGAs is 0.6tconfigN; namely, the initial configuration time of the first FPGA is 0.2tconfig+0.6tconfigThe initial configuration time of the second FPGA is 0.2tconfig+0.6tconfigX 2/n, the configuration starting time of the nth FPGA is 0.2tconfig+0.6tconfig×n/n；
Step four, enabling program _ b of the FPGA to start configuration, wherein the program _ b is controlled by the RC delay circuit, and when the voltage of the RC delay circuit rises to a threshold voltage, the program _ b outputs the enable; the specific control method comprises the following steps:
the Done of the FPGA controls program _ b of the FPGA;
setting the configuration interval time of each FPGA as the configuration completion time of a single chip; the Done of the first FPGA is connected with the program _ b of the second FPGA, and the Done of the second FPGA is connected with the program _ b of the third FPGA until the connection of the last FPGA is completed;
total length of configuration time T of multiple FPGAtotalComprises the following steps:in the formula TiFor the configuration time of the ith slice, TdelayRC delay time of program _ b of the first FPGA;
the above-mentionedWhere l is the total length of the configuration data, m is the bit width for reading data from the PROM, fcclkFor reading clock frequencies from PROMs, Tdelay_iThe time during the configuration process when data is not read out.
The invention has the beneficial effects that: according to the multi-FPGA power-on configuration control method, the number of DC/DC modules is reduced, and the number of transmission cables and the number of connectors are reduced; secondly, surge current generated by the DC/DC power supply can be reduced through time-sharing enabling of the power supply of each part; and thirdly, the magnitude of the total output current of the DC/DC can be reduced and the utilization efficiency of the power supply can be improved by staggering the loading time of each FPGA.
Drawings
FIG. 1 is a block diagram of a multi-FPGA serial power-on configuration control system according to the present invention;
FIG. 2 is a block diagram of a multi-FPGA time-sharing power-on configuration control system of the present invention;
FIG. 3 is a circuit diagram of the RC delay combined with the comparator according to the present invention.
Detailed Description
In a first specific embodiment, the present embodiment is described with reference to fig. 1 to 3, and a multi-FPGA power-on configuration control method includes an FPGA power-on configuration control system, where the FPGA power-on configuration control system includes a DC/DC power supply, a transmission cable, an external circuit, multiple FPGAs IO power supply LDOs, multiple FPGAs core power supply LDOs, and an RC delay circuit. And the voltage output by the DC/DC power supply supplies power to an external circuit, IO (input/output) of the FPGA and a kernel through the transmission cable and each LDO (low dropout regulator). In the power-on configuration process, each part adopts time-sharing power-on, and the specific process is as follows:
(1) electrifying an external circuit of the FPGA: the LDO with the part of power supply is in an output normally enabled state, and the LDO starts to output after the DC/DC starts to output.
(2) The IO power supply LDO of the FPGA outputs and enables: the output of the LDO of the partial power supply is controlled by an RC delay circuit, when the voltage of the RC circuit rises to the threshold voltage and then begins to be output, the IO power supply LDO of a plurality of pieces of FPGA outputs and enables within the same delay time, and the delay time is 0.02tconfig(ii) a In the formula tconfigMaximum power supply rise time configured for the FPGA;
(3) the core of the FPGA supplies power to the LDO output to enable: the LDO output of the part of power supply is controlled by the RC delay circuit, and the output is started when the voltage of the RC circuit rises to the threshold voltage. For n FPGAs, the enabling interval time of the kernel power supply of the n FPGAs is 0.6tconfigN; that is, the arrangement start time of the first slice is 0.2tconfig+0.6tconfigN, second tablet is 0.2tconfig+0.6tconfigX 2/n, the nth sheet is 0.2tconfig+0.6tconfigX n/n. In the formula tconfigThe maximum power rise time allowed is configured for the FPGA.
(4) Enabling and configuring program _ b of the FPGA: the output of the part is controlled by an RC delay circuit, and the part starts to be enabled when the voltage of the RC circuit rises to the rear of the threshold voltage. The specific control method comprises the following steps:
the Done of the FPGA controls program _ b; as shown in fig. 1, the configuration interval time of each FPGA is the configuration completion time of a single chip; the Done of the first slice is connected to the program _ b of the second slice, the Done of the second slice is connected to the program _ b of the third slice, and so on until the last slice.
Total length T of multi-chip FPGA configuration timetotalComprises the following steps:in the formula TiFor the configuration time of the ith slice, TdelayIs the RC delay time of program _ b of the first FPGA.Where l is the total length of the configuration data, m is the bit width for reading data from the PROM, fcclkFor reading clock frequencies from PROMs, Tdelay_iThe time during the configuration process when data is not read out.
In this embodiment, in the process of enabling, starting and configuring program _ b of the FPGA, the program _ b output is controlled by the RC delay circuit, and when the voltage of the RC circuit rises to the threshold voltage, the program _ b side starts enabling, and the control method can also be implemented in the following manner:
with reference to fig. 2, RC delay with reference to the comparator is used: by combining RC time delay of the comparator, the time from the start of IO power supply enabling of different FPGAs to the start of high-level starting configuration of the corresponding program _ b can be controlled; with reference to fig. 3, not only the delay adjustment can be performed by setting the RC parameter, but also the delay adjustment can be performed by setting the threshold level through the voltage dividing circuit.
In this embodiment, the time from the start of the IO power supply enable to the time when the corresponding program _ b changes to the high-level start configurationIn the formula, tau is the charging time coefficient of an RC circuit powered by the IO power supply, and k is the voltage division coefficient of a voltage division circuit powered by the IO power supply, namely the ratio of threshold voltage to power supply voltage, wherein k is more than 0 and less than 1. The total time for a multi-chip FPGA configuration depends on the configuration time for the longest FPGA configured.
The output voltage requirement of the DC/DC power supply described in this embodiment is not lower than: IO supply voltage of the FPGA + voltage difference of the LDO + resistance of the output cable multiplied by peak current of the output cable in the configuration process.
The output current of the DC/DC power supply is not lower than 120% of the peak current of the configuration process.
The FPGA in the present embodiment is a virtex 2 series FPGA such as XQ2V 3000; the LDO adopts MSK 5101; the DC/DC power supply adopts a DC/DC module of VPT company.

Claims (4)

1. A multi-FPGA power-on configuration control method is characterized in that; the FPGA power-on configuration control system comprises a DC/DC power supply, an external circuit, an IO power supply LDO of the FPGA, an inner core power supply LDO of the FPGA and an RC delay circuit;
the voltage output by the DC/DC power supply respectively supplies power to an external circuit, IO (input/output) of the FPGA and a kernel through a transmission cable and each LDO (low dropout regulator); the RC delay circuit is used for controlling the IO power supply LDO output voltage of the FPGA, the kernel power supply LDO output voltage and the program _ b enable of the FPGA; in the process of power-on configuration control, time-sharing power-on is adopted, and the specific power-on configuration control method comprises the following steps:
step one, electrifying an external circuit; the LDO is in an output normal enable state, and the LDO starts to output voltage after the DC/DC power supply outputs the voltage;
step two, IO power supply LDO output of the FPGA is enabled;
the IO power supply LDO is controlled by the RC delay circuit, when the voltage of the RC delay circuit rises to the threshold voltage IO power supply LDO and begins to output voltage, the IO power supply LDO of the multiple FPGAs output and enable within the same delay time, and the delay time is 0.2tconfig(ii) a In the formula tconfigMaximum power supply rise time configured for the FPGA;
thirdly, the kernel of the FPGA supplies power to the LDO output to enable;
the output of the LDO powered by the kernel is controlled by the RC delay circuit, and the LDO powered by the kernel starts to output voltage after the voltage of the RC delay circuit rises to the threshold voltage;
setting n FPGAs, the enabling interval time of the kernel power supply of the n FPGAs is 0.6tconfigN; namely, the initial configuration time of the first FPGA is 0.2tconfig+0.6tconfigThe initial configuration time of the second FPGA is 0.2tconfig+0.6tconfigX 2/n, the configuration starting time of the nth FPGA is 0.2tconfig+0.6tconfig×n/n；
Step four, enabling program _ b of the FPGA to start configuration, wherein the program _ b is controlled by the RC delay circuit, and when the voltage of the RC delay circuit rises to a threshold voltage, the program _ b outputs the enable; the specific control method comprises the following steps:
the Done of the FPGA controls program _ b of the FPGA;
setting the configuration interval time of each FPGA as the configuration completion time of a single chip; the Done of the first FPGA is connected with the program _ b of the second FPGA, and the Done of the second FPGA is connected with the program _ b of the third FPGA until the connection of the last FPGA is completed;
total length of configuration time T of multiple FPGAtotalComprises the following steps:in the formula TiFor the configuration time of the ith slice, TdelayRC delay time of program _ b of the first FPGA;
the above-mentionedWhere l is the total length of the configuration data, m is the bit width for reading data from the PROM, fcclkFor reading clock frequencies from PROMs, Tdelay_iThe time during the configuration process when data is not read out.
2. The power-on configuration control method for multiple FPGAs according to claim 1, wherein; in the fourth step, program _ b enabling of the FPGA is controlled by the RC delay circuit, and when the voltage of the RC delay circuit rises to a threshold voltage, program _ b enabling is carried out; the method also comprises another control method, which specifically comprises the following steps:
setting independence among the FPGAs, and controlling program _ b of the FPGAs by adopting RC delay circuits respectively combined with comparators: and controlling the time from the IO power supply enabling of different FPGAs to the time when the program _ b of the corresponding FPGA is changed into high level to start configuration by combining the RC delay circuit of the comparator.
3. The power-on configuration control method for multiple FPGAs according to claim 2, wherein; starting IO power supply enabling until program _ b pin of corresponding FPGA becomes high level to start configurationTime of standingTau is the charging time coefficient of the RC circuit of IO power supply, and k is the voltage division coefficient of the bleeder circuit of IO power supply, k's scope is: k is more than 0 and less than 1.
4. The power-on configuration control method for multiple FPGAs according to claim 1, wherein; the output voltage requirement of the DC/DC power supply is more than or equal to the sum of the output voltage of the IO power supply LDO of the FPGA and the voltage difference of the LDO, the resistance of a transmission cable and the peak current of the transmission cable in the configuration process.
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