CN107863341B - 复合型沟槽mos器件及其制造方法 - Google Patents
复合型沟槽mos器件及其制造方法 Download PDFInfo
- Publication number
- CN107863341B CN107863341B CN201710571363.4A CN201710571363A CN107863341B CN 107863341 B CN107863341 B CN 107863341B CN 201710571363 A CN201710571363 A CN 201710571363A CN 107863341 B CN107863341 B CN 107863341B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- contact
- contact hole
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000002131 composite material Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical group C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 214
- 239000002184 metal Substances 0.000 claims description 214
- 238000000151 deposition Methods 0.000 claims description 43
- 239000010936 titanium Substances 0.000 claims description 36
- 229910052719 titanium Inorganic materials 0.000 claims description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 33
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 33
- 229910052721 tungsten Inorganic materials 0.000 claims description 33
- 239000010937 tungsten Substances 0.000 claims description 33
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 27
- 238000001312 dry etching Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 15
- 230000000903 blocking effect Effects 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000011084 recovery Methods 0.000 abstract description 3
- 238000011161 development Methods 0.000 description 3
- 238000004134 energy conservation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明属于半导体功率器件技术领域,具体涉及到一种复合型沟槽MOS器件及其制造方法,本发明将肖特基二极管结构和TMBS结构集成在每一个沟槽MOSFET单胞的接触孔中,在MOSFET单胞的接触孔侧壁形成肖特基接触,降低开关损耗和抑制尖峰电压和尖峰电流,提高反向恢复特性;并且在接触孔的底部形成TMBS结构,能够在器件内部形成平衡电场,提升器件击穿特性,从而达到提高器件性能的同时,有效的节约硅表面面积,降低芯片成本;本发明制造工艺简单,成本低,结构新颖,产品性能和可靠性高,并能有效抑制沟槽MOSFET器件反向恢复的尖峰电压和尖峰电流以及提高器件耐压。
Description
技术领域
本发明涉及半导体功率器件技术领域,具体涉及一种复合型沟槽MOS器件结构及其制造方法。
背景技术
随着我国经济持续快速的迅猛发展,能源消耗也逐年增加,特别是在全球变暖的大背景下,“低碳经济”逐渐成为全球热点,因此节约能源已成为我国的基本国策之一。而新型电力电子器件在其中扮演者特别重要的角色,其中沟槽MOS器件是作为如今发展迅速、市场前景好的半导体器件,它具有开关速度快、输入阻抗高、热稳定性好、可靠性强等优点,在计算机、通讯设备、普通办公设备的电源供应电路以及汽车电子电路领域有着广泛的应用。
大多数功率MOSFET器件的一个特有之处是具有一个“寄生”的漏-源内置二极管。在许多应用场合中,漏-源内置二极管不会处于反偏状态,因此并不影响电路的工作。但随着近些年来微处理器时钟频率的提高,我们需要低电压、大电流和高电流摆率(di/dt>;150A)的电压调制模块(VRM),通常对于DC-DC变换器,工作频率需要提高到1MHZ甚至更高。为满足这一要求,减小沟槽MOS器件的反向恢复电荷Qrr是十分有效的,而且可以阻止导通时的功耗损失和自开启。为了实现这一目的,其中一种做法就是在沟槽MOSFET器件的源极S与漏极D之间并联一肖特基二极管SBD,其发展主要经历了如下历程:
第一阶段是将独立封装的肖特基二极管与独立封装的沟槽MOSFET并联安装在电路板上。缺点是成本高,占用电路板更多面积以及由于较长走线引入寄生电感的影响,带来额外损耗以及EMC和EMI问题。
第二阶段是将独立的肖特基芯片与独立的沟槽MOSFET芯片并联封装在同一半导体器件封装内,依靠打线是沟槽MOSFET芯片和肖特基芯片实现并联。缺点依然是成本高,并且对封装要求高,以及封装后整体面积大。
第三阶段是将沟槽MOSFET与肖特基二极管设计设计制作在同一芯片中,在处理沟槽MOSFET与肖特基二极管的方式上都是采用分区设计加区分制作的方案,而通过打线实现互联,还是占据了大量的芯片面积和成本。因此存在的缺点总是:1、肖特基二极管结构占用了大量硅表面面积,导致芯片面积大,成本高;2、工艺复杂,导致制造成本高。
发明内容
有鉴于此,本发明的主要目的在于提供一种复合型沟槽MOS器件结构及其制造方法。
本发明实施例提供一种复合型沟槽MOS器件,该器件包括漏极区、位于所述漏极区上方的N+单晶硅衬底和N-外延层、位于所述N-外延层上方的P型阱区层、位于所述P型阱区层上方的源极区层、位于所述源极区层上方的绝缘介质层、和位于所述绝缘介质层上方的源极金属区层,还包括:
沟槽,其穿过所述P型阱区层,延伸至所述N-外延层的内部;
栅氧化层,其与所述沟槽接触;
多晶硅层,其与栅氧化层接触,顶部与所述绝缘介质层接触;
接触孔,所述接触孔穿过所述绝缘介质层和所述P型阱区层,延伸至所述N-外延层,所述接触孔内填充有金属,所述金属的顶端连接所述源极金属区层;
接触孔底部氧化层,其位于所述接触孔底部,与所述N-外延层连接;
接触孔底部多晶层,其与所述接触孔底部氧化层接触,形成TMBS结构;
接触金属层,所述接触金属层底部与所述接触孔底部多晶层接触,所述接触金属层顶部与所述源极金属区层接触,所述接触金属层包括肖特基接触层和欧姆接触层,所述肖特基接触层是所述接触金属层在源极接触孔的侧壁与所述N-外延层接触,所述欧姆接触层是所述接触金属层在源极接触孔的侧壁与N+源极和所述P型阱区层接触;
其中,所述源极金属区层为MOS管源极金属电极,即肖特基的阳极金属电极,所述漏极区为MOS管漏极金属电极,即肖特基的阴极金属电极。
上述方案中,所述肖特基接触层包括金属钨连接层、氮化钛阻挡层与金属钛粘结层,所述金属钨连接层与所述源极金属区层的底部接触,所述氮化钛阻挡层与所述金属钨连接层的侧面端接触,所述金属钛粘结层与所述氮化钛阻挡层的侧面端接触,所述金属钛粘结层在所述接触孔的侧面端与所述N-外延层形成肖特基接触。
上述方案中,所述欧姆接触层所述欧姆接触层位于所述接触孔的侧壁处,所述金属钛粘结层与源极区层形成N+源极欧姆接触;所述金属钛粘结层与P+接触区形成P型阱的欧姆接触。
上述方案中,所述接触孔底部氧化层与所述N-外延层连接,所述接触孔底部多晶层底部与所述接触孔底部氧化层连接,而顶部与源极金属区层的底端接触,最终形成TMBS结构。
上述方案中,所述接触孔底部多晶层为N型重掺杂的多晶硅。
本发明实施例还提供一种制造上述方案中任意一项所述的复合型沟槽MOS器件的制造方法,其特征在于,该方法通过以下步骤实现:
在N型高掺杂浓度的N+单晶硅衬底上,生长N型低掺杂浓度的N-外延层;
在N-外延层表面上生长第一介质层后,对所述第一介质层进行光刻,定义出MOS管单胞阵列的沟槽区图形;
通过干法刻蚀,去除未被光刻胶保护的第一介质层,曝露出沟槽区图形对应的N-外延层,再去除光刻胶后,保留下来的第一介质层作为第一硬掩膜;
以所述第一硬掩膜作为阻挡层,在N-外延层中的表面形成沟槽,在所述沟槽和N-外延层的表面淀积一层为二氧化硅的第二介质层,形成栅氧化层;
在所述栅氧化层上淀积导电多晶硅层,通过干法刻蚀去掉N-外延层顶部的导电多晶硅层以及栅氧化层;
将P型杂质离子注入到所述N-外延层内,然后通过快速退火处理,在所述N-外延层内形成P型阱区层;
在所述P型阱区层的上方定义出源极区层;
在源极区层的表面淀积第三介质层,该第三介质层为二氧化硅层,或者氮化硅层,或者二氧化硅层和氮化硅层的复合层;
位于所述源极区层上方的第三介质层形成绝缘介质层,对作为绝缘介质层的第三介质层实施干法刻蚀,穿透所述绝缘介质层和所述P型阱区层,延伸至所述N-外延层,形成接触孔;
在所述接触孔中淀积一层氧化层和一层多晶硅,通过干法蚀刻形成所述接触孔底部氧化层和所述接触孔底部多晶层的TMBS结构;
对接触孔进行金属填充,先沉积金属钛粘结层,在金属钛粘结层上淀积氮化钛阻挡层,再接着沉积钨金属层以及铝金属层,靠近所述接触孔侧面端的所述P型阱区层处设有P+接触区,位于所述接触孔侧面端的金属钛粘结层和氮化钛阻挡层与源极区层形成N+源极欧姆接触,位于所述接触孔的侧壁的金属钛粘结层和氮化钛阻挡层与P+接触区形成P型阱的欧姆接触层;
在所述欧姆接触层下方金属钛粘结层与所述N-外延层侧面接触,在接触孔侧壁形成肖特基接触,在金属钛粘结层上淀积氮化钛阻挡层,在氮化钛阻挡层上淀积金属钨连接层,金属钛粘结层、氮化钛阻挡层及金属钨连接层形成肖特基接触层;
在所述欧姆接触层和肖特基接触层的侧面淀积钨金属形成接触金属层;而在所述接触金属层的下方形成由所述接触孔底部氧化层和所述接触孔底部多晶层组成的TMBS结构。
在所述绝缘介质层的上表面淀积金属,形成源极金属区层,所述接触孔通过接触金属层与所述源极金属区层连接,形成源极金属电极;
对金属区层实施光刻,用光刻胶保护MOS管单胞阵列区的源极金属电极区域和MOS管单胞阵列区***的栅极金属电极区域,即定义源极金属电极区域和栅极金属电极区域图形;
采用干法刻蚀方法,选择性去除未被光刻胶保护的金属区层,曝露出作为绝缘介质层的第三介质层,去除光刻胶后,留下的位于单胞阵列区域的金属区层形成MOS管源极金属电极,同时也是肖特基二极管的阳极金属电极,留下的位于单胞阵列区域***的金属区层形成MOS管栅极金属电极;
在N+单晶硅衬底的底面沉积金属层,形成漏极区,该金属层形成MOS管漏极金属电极,同时也是肖特基二极管的阴极金属电极。
上述方案中,所述多晶硅层的掺杂类型为N型掺杂或者P型掺杂。
上述方案中,所述在绝缘介质层的上表面淀积金属,形成源极金属区层,具体步骤为:在绝缘介质层的上表面淀积金属钨,金属钨填满接触孔,然后采用干法刻蚀方法,选择性去除金属钨,使作为绝缘介质层的第三介质层曝露出来,接触孔中依然填满钨,然后再淀积铝层,或者掺杂有铜的铝层,或者掺杂有铜和硅的铝层。
上述方案中,所述在绝缘介质层的上表面淀积金属,形成源极金属区层,具体步骤为:在绝缘介质层的上表面淀积铝层,或者掺杂有铜的铝层,或者掺杂有铜和硅的铝层,并填满接触孔。
上述方案中,所述接触孔底部氧化层与所述接触孔底部氧多晶硅层接触,所述多晶硅层顶端与所述接触金属层底部接触,所述接触金属层与所述源极金属区层接触。
与现有技术相比,本发明的有益效果:
1、本发明提供的一种复合型沟槽MOS器件,其在每个单胞源极的接触孔侧壁集成TMBS结构,达到平衡器件内部电场的目的,有效提升器件的击穿特性,增加器件的耐压。
2、本发明提供的一种复合型沟槽MOS器件,其在每个单胞源极的接触孔侧壁集成肖特基二极管结构,其有效且极大地降低开关损耗,抑制尖峰电压和尖峰电流。
3、本发明提供的一种复合型沟槽MOS器件,在接触孔的底部集成TMBS结构,且肖特基二极管的接触金属层位于接触孔侧壁。使得器件不仅拥有TMBS结构和肖特基二极管的优势,而且有效地节约硅表面面积,降低器件的成本。
4、本发明提供的一种复合型沟槽MOS器件,其结构新颖,产品性能高。
5、本发明提供的一种复合型沟槽MOS器件的制造方法,制作工艺简单,与传统方式相比,制造成本降低,单胞集成度高。
附图说明
图1是本发明的结构剖面示意图。
图1中,1为N+单晶硅衬底;2为N-外延层;3为P型阱区层;4为源极区层;5为沟槽;6为栅氧化层;7为多晶硅层;8为接触孔;9为接触孔底部氧化层;10为接触孔底部多晶硅层;11为肖特基接触层;12为欧姆接触层;13为绝缘介质氧化层;14为源区金属电极层;15为背面漏区金属电极层。
图2~11是本发明的工艺步骤示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
本发明实施例提供一种复合型沟槽MOS器件,如图1所示,该器件包括漏极区、位于所述漏极区上方的N+单晶硅衬底1和N-外延层2、位于所述N-外延层2上方的P型阱区层3、位于所述P型阱区层3上方的源极区层4、位于所述源极区层4上方的绝缘介质层13、和位于所述绝缘介质层13上方的源极金属区层,还包括:
沟槽5,其穿过所述P型阱区层3,延伸至所述N-外延层2的内部;
栅氧化层6,其与所述沟槽5接触;
多晶硅层7,其与栅氧化层6接触,顶部与所述绝缘介质层接触;
接触孔8,所述接触孔8穿过所述绝缘介质层和所述P型阱区层3,延伸至所述N-外延层2,所述接触孔8内填充有金属,所述金属的顶端连接所述源极金属区层;
接触孔底部氧化层9,其位于所述接触孔8底部,与所述N-外延层2;
接触孔底部多晶层10,其与所述接触孔底部氧化层9接触,形成TMBS结构;
接触金属层,所述接触金属层底部与所述接触孔底部多晶层10接触,所述接触金属层顶部与所述源极金属区层接触,所述接触金属层包括肖特基接触层11和欧姆接触层12,所述肖特基接触层11是接触金属层在源极接触孔的侧壁与所述N-外延层2接触,所述欧姆接触层12是接触金属层在源极接触孔的侧壁与所述P型阱区层3接触;
其中,所述源极金属区层为MOS管源极金属电极,即肖特基的阳极金属电极,所述漏极区为MOS管漏极金属电极,即肖特基的阴极金属电极。
所述肖特基接触层11包括金属钨连接层、氮化钛阻挡层与金属钛粘结层,所述金属钨连接层与所述源极金属电极层的底部接触,所述氮化钛阻挡层与所述金属钨连接层的侧面端接触,所述金属钛粘结层与所述氮化钛阻挡层的侧面端接触,所述金属钛粘结层在所述接触孔8的侧面端与所述N-外延层2形成肖特基接触。
所述欧姆接触层12位于所述接触孔8的侧壁处,所述金属钛粘结层与源极区层4形成N+源极欧姆接触;所述金属钛粘结层与P+接触区形成P型阱的欧姆接触。
所述接触孔底部氧化层9与所述N-外延层2连接,所述接触孔底部多晶层10底部与所述接触孔底部氧化层9连接,而顶部与源极金属区层的底端接触,最终形成TMBS结构。
所述接触孔底部多晶层10为N型重掺杂的多晶硅。
本发明实施例还提供一种复合型沟槽MOS器件的制造方法,如图1-11所示,具体实施步骤:
在N型高掺杂浓度的N+单晶硅衬底1上,生长N型低掺杂浓度的N-外延层2;
在N-外延层2表面上生长第一介质层后,对所述第一介质层进行光刻,定义出MOS管单胞阵列的沟槽区图形;
通过干法刻蚀,去除未被光刻胶保护的第一介质层,曝露出沟槽5区图形对应的N-外延层2,再去除光刻胶后,保留下来的第一介质层作为第一硬掩膜;
以所述第一硬掩膜作为阻挡层,在N-外延层2中的表面形成沟槽5,在所述沟槽5和N-外延层2的表面淀积一层为二氧化硅的第二介质层,形成栅氧化层6;
在所述栅氧化层6上淀积导电多晶硅层7,通过干法刻蚀去掉N-外延层2顶部的导电多晶硅层7以及栅氧化层6;
将P型杂质离子注入到所述N-外延层2内,然后通过快速退火处理,在所述N-外延层2内形成P型阱区层3;
在所述P型阱区层3的上方定义出源极区层4;
在源极区层4的表面淀积第三介质层,该第三介质层为二氧化硅层,或者氮化硅层,或者二氧化硅层和氮化硅层的复合层;
位于所述源极区层4上方的第三介质层形成绝缘介质层,对作为绝缘介质层的第三介质层实施干法刻蚀,穿透所述绝缘介质层和所述P型阱区层3,延伸至所述N-外延层2,形成接触孔8;
在所述接触孔8中淀积一层氧化层和一层多晶硅,通过干法蚀刻形成所述接触孔底部氧化层9和所述接触孔底部多晶层10的TMBS结构;
对接触孔8进行金属填充,先沉积金属钛粘结层,在金属钛粘结层上淀积氮化钛阻挡层,再接着沉积钨金属层以及铝金属层,靠近所述接触孔8侧面端的所述P型阱区层3处设有P+接触区,位于所述接触孔8侧面端的金属钛粘结层和氮化钛阻挡层与源极区层4形成N+源极欧姆接触,位于所述接触孔8的侧壁的金属钛粘结层和氮化钛阻挡层与P+接触区形成P型阱的欧姆接触层12;
在所述欧姆接触层12下方金属钛粘结层与所述N-外延层2侧面接触,在接触孔8侧壁形成肖特基接触,在金属钛粘结层上淀积氮化钛阻挡层,在氮化钛阻挡层上淀积金属钨连接层,金属钛粘结层、氮化钛阻挡层及金属钨连接层形成肖特基接触层11;
在所述欧姆接触层12和肖特基接触层11的侧面淀积钨金属形成接触金属层;而在所述接触金属层的下方形成由所述接触孔底部氧化层9和所述接触孔底部多晶层组成的TMBS结构。
在所述绝缘介质层的上表面淀积金属,形成源极金属区层,所述接触孔8通过接触金属层与所述源极金属区层连接,形成源极金属电极;
对金属区层实施光刻,用光刻胶保护MOS管单胞阵列区的源极金属电极区域和MOS管单胞阵列区***的栅极金属电极区域,即定义源极金属电极区域和栅极金属电极区域图形;
采用干法刻蚀方法,选择性去除未被光刻胶保护的金属区层,曝露出作为绝缘介质层的第三介质层,去除光刻胶后,留下的位于单胞阵列区域的金属区层形成MOS管源极金属电极,同时也是肖特基二极管的阳极金属电极,留下的位于单胞阵列区域***的金属区层形成MOS管栅极金属电极;
在N+单晶硅衬底1的底面沉积金属层,形成漏极区,该金属层形成MOS管漏极金属电极,同时也是肖特基二极管的阴极金属电极。
所述多晶硅层7的掺杂类型为N型掺杂或者P型掺杂。
所述在绝缘介质层的上表面淀积金属,形成源极金属区层,具体步骤为:在绝缘介质层的上表面淀积金属钨,金属钨填满接触孔8,然后采用干法刻蚀方法,选择性去除金属钨,使作为绝缘介质层的第三介质层曝露出来,接触孔8中依然填满钨,然后再淀积铝层,或者掺杂有铜的铝层,或者掺杂有铜和硅的铝层。
所述在绝缘介质层的上表面淀积金属,形成源极金属区层,具体步骤为:在绝缘介质层的上表面淀积铝层,或者掺杂有铜的铝层,或者掺杂有铜和硅的铝层,并填满接触孔8。
所述接触孔底部氧化层9与所述接触孔8底部多晶硅层7接触,所述多晶硅层7顶端与所述接触金属层底部接触,所述接触金属层与所述源极金属区层接触。
最后采用干法刻蚀方法,选择性去除未被光刻胶保护的金属区层,形成MOS管源区金属电极层14,同时也是肖特基二极管的阳极金属电极,留下的位于单胞阵列区域***的金属区层形成MOS管栅极金属电极;在N+单晶硅衬底的底面沉积金属层,形成漏极区,该金属层形成MOS管背面漏区金属电极层15,同时也是肖特基二极管的阴极金属电极。
本发明原理是:N型沟槽MOFET器件的硅片由N型高掺杂浓度的N+单晶硅衬底1上生长N型低掺杂浓度的N-外延层2构成,MOSFET漏极位于硅片底面高掺杂部分,源极位于硅片表面较低掺杂的外延层部分,栅极则由垂直于硅片表面的沟槽5构成,沟槽MOSFET芯片所能承受的最大反向偏置电压由外延层的厚度和掺杂浓度决定,而导通电流的大小则由导电沟道的宽度,即沟槽的总边长决定,在接触孔8侧壁的肖特基接触势垒由肖特基金属和N-外延层2来决定,在接触孔8底部的TMBS结构由接触孔底部氧化层9和多晶硅层7决定,在有限面积下,沟槽周期排列以期获得最大的有效边长。包含有沟槽、源极的最小重复单元称为单胞,每个单胞即为一个完整的MOSFET器件。这些单胞并联在一起,构成MOSFET芯片。
本发明在每个沟槽MOSFET单胞中的接触孔侧壁集成肖特基二极管结构,具有这种结构的沟槽MOSFET在功率应用中可以有效降低开关损耗和抑制尖峰电压和尖峰电流。同时在接触孔的底部形成TMBS结构达到平衡器件体内电场的目的,能有效提升器件的击穿特性,提高器件击穿电压。而且,本发明工艺步骤简单,能大批量投入生产,降低成本,增加市场竞争力,使得本发明具有突出的实质性特点和显著的进步。
本发明将肖特基二极管结构和TMBS结构集成在源极接触孔内部,制造的MOS器件能有效地节约硅表面面积,与传统方式相比,降低了芯片成本低,单胞集成度高。
总之,本发明中的沟槽MOS器件,可以用低成本、工艺步骤简单的方式实现,并且可以获得高性能和高可靠型的沟槽MOSFET器件,达到节能减排的目的。
本发明还有其他供选择的实施例,这里就不再做详细说明。
尽管本发明的实施方案已公开如上,但其并不仅仅限于说明书和实施方式中所列运用,它完全可以被适用于各种适合本发明的领域,对于熟悉本领域的人员而言,可容易地实现另外的修改,因此在不背离权利要求及等同范围所限定的一般概念下,本发明并不限于特定的细节和这里示出与描述的图例。
Claims (10)
1.一种复合型沟槽MOS器件,其特征在于,该器件包括漏极区、位于所述漏极区上方的N+单晶硅衬底和N-外延层、位于所述N-外延层上方的P型阱区层、位于所述P型阱区层上方的源极区层、位于所述源极区层上方的绝缘介质层、和位于所述绝缘介质层上方的源极金属区层,还包括:
沟槽,其穿过所述P型阱区层,延伸至所述N-外延层的内部;
栅氧化层,其与所述沟槽接触;
多晶硅层,其与栅氧化层接触,顶部与所述绝缘介质层接触;
接触孔,所述接触孔穿过所述绝缘介质层和所述P型阱区层,延伸至所述N-外延层,所述接触孔内填充有金属,所述金属的顶端连接所述源极金属区层;
接触孔底部氧化层,其位于所述接触孔底部,与所述N-外延层连接;
接触孔底部多晶层,其与所述接触孔底部氧化层接触,形成TMBS结构;
接触金属层,所述接触金属层底部与所述接触孔底部多晶层接触,所述接触金属层顶部与所述源极金属区层接触,所述接触金属层包括肖特基接触层和欧姆接触层,所述肖特基接触层是所述接触金属层在源极接触孔的侧壁与所述N-外延层接触,所述欧姆接触层是所述接触金属层在源极接触孔的侧壁与N+源极和所述P型阱区层接触;
其中,所述源极金属区层为MOS管源极金属电极,即肖特基的阳极金属电极,所述漏极区为MOS管漏极金属电极,即肖特基的阴极金属电极。
2.根据权利要求1所述的复合型沟槽MOS器件,其特征在于:所述肖特基接触层包括金属钨连接层、氮化钛阻挡层与金属钛粘结层,所述金属钨连接层与所述源极金属区层的底部接触,所述氮化钛阻挡层与所述金属钨连接层的侧面端接触,所述金属钛粘结层与所述氮化钛阻挡层的侧面端接触,所述金属钛粘结层在所述接触孔的侧面端与所述N-外延层形成肖特基接触。
3.根据权利要求1所述的复合型沟槽MOS器件,其特征在于,所述欧姆接触层所述欧姆接触层位于所述接触孔的侧壁处,所述金属钛粘结层与源极区层形成N+源极欧姆接触;所述金属钛粘结层与P+接触区形成P型阱的欧姆接触。
4.根据权利要求1所述的复合型沟槽MOS器件,其特征在于,所述接触孔底部氧化层与所述N-外延层连接,所述接触孔底部多晶层底部与所述接触孔底部氧化层连接,而顶部与源极金属区层的底端接触,最终形成TMBS结构。
5.如权利要求4所述一种复合型沟槽MOS器件,其特征在于,所述接触孔底部多晶层为N型重掺杂的多晶硅。
6.一种制造权利要求1至5中任意一项所述的复合型沟槽MOS器件的制造方法,其特征在于,该方法通过以下步骤实现:
在N型高掺杂浓度的N+单晶硅衬底上,生长N型低掺杂浓度的N-外延层;
在N-外延层表面上生长第一介质层后,对所述第一介质层进行光刻,定义出MOS管单胞阵列的沟槽区图形;
通过干法刻蚀,去除未被光刻胶保护的第一介质层,曝露出沟槽区图形对应的N-外延层,再去除光刻胶后,保留下来的第一介质层作为第一硬掩膜;
以所述第一硬掩膜作为阻挡层,在N-外延层中的表面形成沟槽,在所述沟槽和N-外延层的表面淀积一层为二氧化硅的第二介质层,形成栅氧化层;
在所述栅氧化层上淀积导电多晶硅层,通过干法刻蚀去掉N-外延层顶部的导电多晶硅层以及栅氧化层;
将P型杂质离子注入到所述N-外延层内,然后通过快速退火处理,在所述N-外延层内形成P型阱区层;
在所述P型阱区层的上方定义出源极区层;
在源极区层的表面淀积第三介质层,该第三介质层为二氧化硅层,或者氮化硅层,或者二氧化硅层和氮化硅层的复合层;
位于所述源极区层上方的第三介质层形成绝缘介质层,对作为绝缘介质层的第三介质层实施干法刻蚀,穿透所述绝缘介质层和所述P型阱区层,延伸至所述N-外延层,形成接触孔;
在所述接触孔中淀积一层氧化层和一层多晶硅,通过干法蚀刻形成所述接触孔底部氧化层和所述接触孔底部多晶层的TMBS结构;
对接触孔进行金属填充,先沉积金属钛粘结层,在金属钛粘结层上淀积氮化钛阻挡层,再接着沉积钨金属层以及铝金属层,靠近所述接触孔侧面端的所述P型阱区层处设有P+接触区,位于所述接触孔侧面端的金属钛粘结层和氮化钛阻挡层与源极区层形成N+源极欧姆接触,位于所述接触孔的侧壁的金属钛粘结层和氮化钛阻挡层与P+接触区形成P型阱的欧姆接触层;
在所述欧姆接触层下方金属钛粘结层与所述N-外延层侧面接触,在接触孔侧壁形成肖特基接触,在金属钛粘结层上淀积氮化钛阻挡层,在氮化钛阻挡层上淀积金属钨连接层,金属钛粘结层、氮化钛阻挡层及金属钨连接层形成肖特基接触层;
在所述欧姆接触层和肖特基接触层的侧面淀积钨金属形成接触金属层;而在所述接触金属层的下方形成由所述接触孔底部氧化层和所述接触孔底部多晶层组成的TMBS结构;
在所述绝缘介质层的上表面淀积金属,形成源极金属区层,所述接触孔通过接触金属层与所述源极金属区层连接,形成源极金属电极;
对金属区层实施光刻,用光刻胶保护MOS管单胞阵列区的源极金属电极区域和MOS管单胞阵列区***的栅极金属电极区域,即定义源极金属电极区域和栅极金属电极区域图形;
采用干法刻蚀方法,选择性去除未被光刻胶保护的金属区层,曝露出作为绝缘介质层的第三介质层,去除光刻胶后,留下的位于单胞阵列区域的金属区层形成MOS管源极金属电极,同时也是肖特基二极管的阳极金属电极,留下的位于单胞阵列区域***的金属区层形成MOS管栅极金属电极;
在N+单晶硅衬底的底面沉积金属层,形成漏极区,该金属层形成MOS管漏极金属电极,同时也是肖特基二极管的阴极金属电极。
7.根据权利要求6所述的制造方法,其特征在于,所述多晶硅层的掺杂类型为N型掺杂或者P型掺杂。
8.根据权利要求6或7所述的制造方法,其特征在于,所述在所述绝缘介质层的上表面淀积金属,形成源极金属区层,具体步骤为:在绝缘介质层的上表面淀积金属钨,金属钨填满接触孔,然后采用干法刻蚀方法,选择性去除金属钨,使作为绝缘介质层的第三介质层曝露出来,接触孔中依然填满钨,然后再淀积铝层,或者掺杂有铜的铝层,或者掺杂有铜和硅的铝层。
9.根据权利要求6或7所述的制造方法,其特征在于,所述在所述绝缘介质层的上表面淀积金属,形成源极金属区层,具体步骤为:在绝缘介质层的上表面淀积铝层,或者掺杂有铜的铝层,或者掺杂有铜和硅的铝层,并填满接触孔。
10.根据权利要求6所述的制造方法,其特征在于,所述接触孔底部氧化层与所述接触孔底部氧多晶硅层接触,所述多晶硅层顶端与所述接触金属层底部接触,所述接触金属层与所述源极金属区层接触。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710571363.4A CN107863341B (zh) | 2017-07-13 | 2017-07-13 | 复合型沟槽mos器件及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201710571363.4A CN107863341B (zh) | 2017-07-13 | 2017-07-13 | 复合型沟槽mos器件及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107863341A CN107863341A (zh) | 2018-03-30 |
CN107863341B true CN107863341B (zh) | 2023-07-04 |
Family
ID=61699149
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710571363.4A Active CN107863341B (zh) | 2017-07-13 | 2017-07-13 | 复合型沟槽mos器件及其制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN107863341B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108807504B (zh) * | 2018-08-28 | 2022-01-25 | 电子科技大学 | 碳化硅mosfet器件及其制造方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101853852A (zh) * | 2010-04-29 | 2010-10-06 | 苏州硅能半导体科技股份有限公司 | 单胞中集成肖特基二极管的沟槽mos器件及制造方法 |
CN201663162U (zh) * | 2010-04-29 | 2010-12-01 | 苏州硅能半导体科技股份有限公司 | 单胞中集成肖特基二极管的沟槽mos器件 |
CN102280487A (zh) * | 2011-08-22 | 2011-12-14 | 无锡新洁能功率半导体有限公司 | 一种新型沟槽结构的功率mosfet器件及其制造方法 |
CN104425628A (zh) * | 2013-08-22 | 2015-03-18 | 大中积体电路股份有限公司 | 半导体功率元件及其半导体结构 |
CN104681448A (zh) * | 2013-11-29 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | 肖特基晶体管的结构及制造方法 |
CN207199624U (zh) * | 2017-07-13 | 2018-04-06 | 西安华羿微电子股份有限公司 | 一种复合型沟槽mos器件 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090039456A1 (en) * | 2007-08-08 | 2009-02-12 | Alpha & Omega Semiconductor, Ltd | Structures and methods for forming Schottky diodes on a P-substrate or a bottom anode Schottky diode |
-
2017
- 2017-07-13 CN CN201710571363.4A patent/CN107863341B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101853852A (zh) * | 2010-04-29 | 2010-10-06 | 苏州硅能半导体科技股份有限公司 | 单胞中集成肖特基二极管的沟槽mos器件及制造方法 |
CN201663162U (zh) * | 2010-04-29 | 2010-12-01 | 苏州硅能半导体科技股份有限公司 | 单胞中集成肖特基二极管的沟槽mos器件 |
CN102280487A (zh) * | 2011-08-22 | 2011-12-14 | 无锡新洁能功率半导体有限公司 | 一种新型沟槽结构的功率mosfet器件及其制造方法 |
CN104425628A (zh) * | 2013-08-22 | 2015-03-18 | 大中积体电路股份有限公司 | 半导体功率元件及其半导体结构 |
CN104681448A (zh) * | 2013-11-29 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | 肖特基晶体管的结构及制造方法 |
CN207199624U (zh) * | 2017-07-13 | 2018-04-06 | 西安华羿微电子股份有限公司 | 一种复合型沟槽mos器件 |
Also Published As
Publication number | Publication date |
---|---|
CN107863341A (zh) | 2018-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105702676B (zh) | 与mosfet集成的增强型耗尽积累/反转通道器件 | |
TWI464885B (zh) | 在金氧半場效電晶體元件中整合肖特基之結構及其方法 | |
US9209173B2 (en) | Single die output power stage using trench-gate low-side and LDMOS high-side MOSFETS, structure and method | |
CN108962977B (zh) | 一种集成SBD的碳化硅沟槽型MOSFETs及其制备方法 | |
CN101853852B (zh) | 单胞中集成肖特基二极管的沟槽mos器件及制造方法 | |
TWI697965B (zh) | 橫向擴散金屬氧化物半導體(ldmos)電晶體及其製造方法 | |
CN109119463B (zh) | 一种横向沟槽型mosfet器件及其制备方法 | |
CN114937692B (zh) | 一种具有沟道二极管的阶梯沟槽栅SiC MOSFET结构及其制备方法 | |
CN114937693B (zh) | 一种具有双沟道二极管的沟槽栅SiC MOSFET器件及其制备方法 | |
CN116387362A (zh) | 一种集成HJD的SiC UMOSFET器件及其制备方法 | |
CN116721925B (zh) | 集成sbd的碳化硅sgt-mosfet及其制备方法 | |
CN201663162U (zh) | 单胞中集成肖特基二极管的沟槽mos器件 | |
CN115832057A (zh) | 一种碳化硅mosfet器件以及制备方法 | |
CN116598358A (zh) | 一种沟槽型功率mosfet器件及工艺流程 | |
CN106328647B (zh) | 高速的沟槽mos器件及其制造方法 | |
US20130001699A1 (en) | Trench junction barrier schottky structure with enhanced contact area integrated with a mosfet | |
CN107863341B (zh) | 复合型沟槽mos器件及其制造方法 | |
CN116525683B (zh) | 一种深阱型SiC Mosfet器件及制备方法 | |
CN107863386B (zh) | 集成tmbs结构的沟槽mos器件及其制造方法 | |
CN112864250A (zh) | 改善栅漏电荷的沟槽型功率半导体器件及其制备方法 | |
CN207199624U (zh) | 一种复合型沟槽mos器件 | |
CN109192780B (zh) | 一种横向mosfet器件及其制备方法 | |
CN116487437A (zh) | 半导体器件 | |
CN103022155A (zh) | 一种沟槽mos结构肖特基二极管及其制备方法 | |
CN206134681U (zh) | 高速的沟槽mos器件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: 710000 No. 8928, Shang Ji Road, an ecological industrial park in Xi'an, Shaanxi economic and Technological Development Zone Applicant after: HUAYI MICROELECTRONICS Co.,Ltd. Address before: 710000 No. 8928, Shang Ji Road, an ecological industrial park in Xi'an, Shaanxi economic and Technological Development Zone Applicant before: XI'AN HUAYI MICROELECTRONICS CO.,LTD. |
|
CB02 | Change of applicant information | ||
GR01 | Patent grant | ||
GR01 | Patent grant |