CN107819026B - Ldmos器件 - Google Patents

Ldmos器件 Download PDF

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CN107819026B
CN107819026B CN201710904201.8A CN201710904201A CN107819026B CN 107819026 B CN107819026 B CN 107819026B CN 201710904201 A CN201710904201 A CN 201710904201A CN 107819026 B CN107819026 B CN 107819026B
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颜树范
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution

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Abstract

本发明公开了一种LDMOS器件，包括：漂移区，体区；由栅介质层和多晶硅栅叠加形成的栅极结构，源区和漏区；在漏区的外侧的漂移区中形成有由P+区组成的空穴注入区；空穴注入区的深度大于漏区的深度；在积累层区域中形成有由N型掺杂区组成的电荷存储区；空穴注入区在器件导通时提供空穴注入以减少导通电阻，电荷存储区用于对空穴漂移进行阻挡。电荷存储区的掺杂浓度大于漂移区的掺杂浓度以及电荷存储区的掺杂浓度小于体区的掺杂浓度，使器件截止时漂移区的耗尽由体区和漂移区的掺杂浓度决定。本发明能降低器件的导通电阻，同时保持良好的击穿电压。

Description

LDMOS器件
技术领域
本发明涉及一种半导体集成电路，特别是涉及一种LDMOS器件。
背景技术
如图1所示，是现有LDMOS器件的结构示意图；现有LDMOS器件包括：
N型掺杂的漂移区102。所述漂移区102由深N阱组成。所述深N阱形成于半导体衬底101表面。较佳为，所述半导体衬底101为P型掺杂。所述半导体衬底101为硅衬底。
P型掺杂的体区103，所述体区103的结深小于所述漂移区102的结深，所述体区103和所述漂移区102横向交叠。
由栅介质层104和多晶硅栅105叠加形成的栅极结构，所述多晶硅栅105覆盖所述体区103的表面且所述多晶硅栅105的第二侧面延伸到所述漂移区102的表面；被所述多晶硅栅105所覆盖的所述体区103表面用于形成沟道，被所述多晶硅栅105所覆盖的所述漂移区102为积累层区域。较佳为，所述栅介质层104为栅氧化层。
由N+区组成的源区106形成于所述体区103表面并和所述多晶硅栅105的第一侧面自对准。
由N+区组成的漏区107形成于所述漂移区102表面并和所述多晶硅栅105的第二侧面相隔一段距离。
在所述体区103的表面还形成有由P+区组成的体引出接触区108。
所述源区106和所述体引出接触区108都通过接触孔连接到由正面金属层组成的源极。
所述漏区107都通过接触孔连接到由正面金属层组成的漏极。
所述多晶硅栅105的顶部通过接触孔连接到由正面金属层组成的栅极。
图1所示的现有器件的导通电阻为：
Rsp＝Rcs+Rch+Ra+Rdrift+Rcd；
其中Rsp表示导通电阻，Rcs为源接触电阻；Rch为沟道电阻；Ra为积累层电阻，也即被多晶硅栅105所覆盖的漂移区102的电阻；Rdrift为漂移区电阻；Rcd为漏接触电阻；对于高压LDMOS：Rdrift占很大比例。
发明内容
本发明所要解决的技术问题是提供一种LDMOS器件，能降低器件的导通电阻。
为解决上述技术问题，本发明提供的LDMOS器件包括：
N型掺杂的漂移区。
P型掺杂的体区，所述体区的结深小于所述漂移区的结深，所述体区和所述漂移区横向交叠。
由栅介质层和多晶硅栅叠加形成的栅极结构，所述多晶硅栅覆盖所述体区的表面且所述多晶硅栅的第二侧面延伸到所述漂移区的表面；被所述多晶硅栅所覆盖的所述体区表面用于形成沟道，被所述多晶硅栅所覆盖的所述漂移区为积累层区域。
源区形成于所述体区表面并和所述多晶硅栅的第一侧面自对准。
漏区形成于所述漂移区表面并和所述多晶硅栅的第二侧面相隔一段距离。
在所述漏区的外侧的所述漂移区中形成有由P+区组成的空穴注入区；所述空穴注入区的深度大于所述漏区的深度；在所述积累层区域中形成有由N型掺杂区组成的电荷存储区；所述空穴注入区在器件导通时提供空穴注入以减少导通电阻，所述电荷存储区用于对空穴漂移进行阻挡。
所述电荷存储区的掺杂浓度大于所述漂移区的掺杂浓度以及所述电荷存储区的掺杂浓度小于所述体区的掺杂浓度，使器件截止时所述漂移区的耗尽由所述体区和所述漂移区的掺杂浓度决定。
进一步的改进是，所述空穴注入区的结深小于等于所述漂移区的结深。
进一步的改进是，所述电荷存储区的结深和所述空穴注入区的结深相当。
进一步的改进是，所述漂移区由深N阱组成。
进一步的改进是，所述深N阱形成于半导体衬底表面。
进一步的改进是，所述半导体衬底为P型掺杂。
进一步的改进是，所述半导体衬底为硅衬底。
进一步的改进是，所述栅介质层为栅氧化层。
进一步的改进是，在所述体区的表面还形成有由P+区组成的体引出接触区。
进一步的改进是，所述源区和所述体引出接触区都通过接触孔连接到由正面金属层组成的源极。
进一步的改进是，所述空穴注入区和所述漏区横向接触。
进一步的改进是，所述空穴注入区和所述漏区都通过接触孔连接到由正面金属层组成的漏极。
进一步的改进是，所述多晶硅栅的顶部通过接触孔连接到由正面金属层组成的栅极。
本发明通过在漏区外侧设置结深较大的由P+区组成的空穴注入区，空穴注入区能在器件导通时注入空穴到漂移区中，从而能降低器件的漂移区电阻，进而能降低器件的导通电阻；同时，本发明根据空穴注入区在积累层区域的漂移区中设置了电荷存储区，电荷存储区能够对注入到漂移区中的空穴进行阻挡，防止空穴通过积累层区域并进而进入到体区，从而消除注入的空穴对沟道的影响。
本发明的空穴注入区由于设置在漏区的外侧，在器件截止时对漂移区的耗尽无影响，从而不影响器件的击穿电压；同时，本发明的电荷存储区的掺杂浓度小于体区的掺杂浓度以及大于漂移区的掺杂浓度，使得电荷存储区不对漂移区的耗尽产生巨大影响，漂移区的耗尽主要是由体区和漂移区之间形成的PN结的耗尽，故器件的击穿主要是由体区和漂移区的耗尽决定，所以本发明的电荷存储区也不会对击穿电压产生较大影响，也即本发明能保持良好的击穿电压。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明：
图1是现有LDMOS器件的结构示意图；
图2是本发明实施例LDMOS器件的结构示意图；
图3是图2的截止状态时的耗尽区的示意图；
图4是图2的导通状态时的空穴注入的示意图。
具体实施方式
如图2所示，是本发明实施例LDMOS器件的结构示意图；本发明实施例LDMOS器件包括：
N型掺杂的漂移区2。所述漂移区2由深N阱组成。所述深N阱形成于半导体衬底1表面。较佳为，所述半导体衬底1为P型掺杂。所述半导体衬底1为硅衬底。
P型掺杂的体区3，所述体区3的结深小于所述漂移区2的结深，所述体区3和所述漂移区2横向交叠。
由栅介质层4和多晶硅栅5叠加形成的栅极结构，所述多晶硅栅5覆盖所述体区3的表面且所述多晶硅栅5的第二侧面延伸到所述漂移区2的表面；被所述多晶硅栅5所覆盖的所述体区3表面用于形成沟道，被所述多晶硅栅5所覆盖的所述漂移区2为积累层区域。较佳为，所述栅介质层4为栅氧化层。
由N+区组成的源区6形成于所述体区3表面并和所述多晶硅栅5的第一侧面自对准。
由N+区组成的漏区7形成于所述漂移区2表面并和所述多晶硅栅5的第二侧面相隔一段距离。
在所述漏区7的外侧的所述漂移区2中形成有由P+区组成的空穴注入区9；所述空穴注入区9的深度大于所述漏区7的深度，且所述空穴注入区9的结深小于等于所述漂移区2的结深。所述空穴注入区9和所述漏区7横向接触。
在所述积累层区域中形成有由N型掺杂区组成的电荷存储区10；所述电荷存储区10的结深和所述空穴注入区9的结深相当。所述空穴注入区9在器件导通时提供空穴注入以减少导通电阻，所述电荷存储区10用于对空穴漂移进行阻挡。
所述电荷存储区10的掺杂浓度大于所述漂移区2的掺杂浓度以及所述电荷存储区10的掺杂浓度小于所述体区3的掺杂浓度，使器件截止时所述漂移区2的耗尽由所述体区3和所述漂移区2的掺杂浓度决定。
在所述体区3的表面还形成有由P+区组成的体引出接触区8。
所述源区6和所述体引出接触区8都通过接触孔连接到由正面金属层组成的源极。
所述空穴注入区9和所述漏区7都通过接触孔连接到由正面金属层组成的漏极。
所述多晶硅栅5的顶部通过接触孔连接到由正面金属层组成的栅极。
如图3所示，是图2的截止状态时的耗尽区的示意图；在截止状态下，栅极电压即Vg为0V，源极电压即Vs为0V，漏极电压即Vd大于0V，由于栅源电压相等，故沟道为未形成，器件截止，漏极电压和源极电压使得体区和漂移区之间形成耗尽，耗尽区中包括标记201所示的受主离子，以及标记202所示的施主离子。本发明实施例的空穴注入区9由于设置在漏区7的外侧，在器件截止时对漂移区2的耗尽无影响，从而不影响器件的击穿电压；同时，本发明实施例的电荷存储区10的掺杂浓度小于体区3的掺杂浓度以及大于漂移区2的掺杂浓度，使得电荷存储区10不对漂移区2的耗尽产生巨大影响，漂移区2的耗尽主要是由体区3和漂移区2之间形成的PN结的耗尽，故器件的击穿主要是由体区3和漂移区2的耗尽决定，所以本发明实施例的电荷存储区10也不会对击穿电压产生较大影响。
如图4所示，是图2的导通状态时的空穴注入的示意图，在导通状态下，栅极电压即Vg为大于等于Vt，Vt为阈值电压，源极电压即Vs为0V，漏极电压即Vd大于0V，由于栅源电压大于等于Vt，故沟道为形成，器件导通。本发明实施例通过在漏区7外侧设置结深较大的由P+区组成的空穴注入区9，空穴注入区9能在器件导通时注入空穴到漂移区2中，空穴如标记203所示，从而能降低器件的导通电阻；同时，本发明实施例根据空穴注入区9在积累层区域的漂移区2中设置了电荷存储区10，电荷存储区10能够对注入到漂移区2中的空穴进行阻挡，防止空穴通过积累层区域并进而进入到体区3，从而消除注入的空穴对沟道的影响，沟道的电子如标记204所示。
以上通过具体实施例对本发明进行了详细的说明，但这些并非构成对本发明的限制。在不脱离本发明原理的情况下，本领域的技术人员还可做出许多变形和改进，这些也应视为本发明的保护范围。

Claims (13)

1.一种LDMOS器件，其特征在于，包括：
N型掺杂的漂移区；
P型掺杂的体区，所述体区的结深小于所述漂移区的结深，所述体区和所述漂移区横向交叠；
由栅介质层和多晶硅栅叠加形成的栅极结构，所述多晶硅栅覆盖所述体区的表面且所述多晶硅栅的第二侧面延伸到所述漂移区的表面；被所述多晶硅栅所覆盖的所述体区表面用于形成沟道，被所述多晶硅栅所覆盖的所述漂移区为积累层区域；
源区形成于所述体区表面并和所述多晶硅栅的第一侧面自对准；
漏区形成于所述漂移区表面并和所述多晶硅栅的第二侧面相隔一段距离；
在所述漏区的远离所述栅极结构一端的外侧的所述漂移区中形成有由P+区组成的空穴注入区；所述空穴注入区的深度大于所述漏区的深度；在所述积累层区域中形成有由N型掺杂区组成的电荷存储区；所述空穴注入区在器件导通时提供空穴注入以减少导通电阻，所述电荷存储区用于对空穴漂移进行阻挡；
所述电荷存储区的掺杂浓度大于所述漂移区的掺杂浓度以及所述电荷存储区的掺杂浓度小于所述体区的掺杂浓度，使器件截止时所述漂移区的耗尽由所述体区和所述漂移区的掺杂浓度决定。
2.如权利要求1所述的LDMOS器件，其特征在于：所述空穴注入区的结深小于等于所述漂移区的结深。
3.如权利要求1或2所述的LDMOS器件，其特征在于：所述电荷存储区的结深和所述空穴注入区的结深相当。
4.如权利要求1所述的LDMOS器件，其特征在于：所述漂移区由深N阱组成。
5.如权利要求4所述的LDMOS器件，其特征在于：所述深N阱形成于半导体衬底表面。
6.如权利要求5所述的LDMOS器件，其特征在于：所述半导体衬底为P型掺杂。
7.如权利要求5或6所述的LDMOS器件，其特征在于：所述半导体衬底为硅衬底。
8.如权利要求7所述的LDMOS器件，其特征在于：所述栅介质层为栅氧化层。
9.如权利要求1所述的LDMOS器件，其特征在于：在所述体区的表面还形成有由P+区组成的体引出接触区。
10.如权利要求9所述的LDMOS器件，其特征在于：所述源区和所述体引出接触区都通过接触孔连接到由正面金属层组成的源极。
11.如权利要求1所述的LDMOS器件，其特征在于：所述空穴注入区和所述漏区横向接触。
12.如权利要求11所述的LDMOS器件，其特征在于：所述空穴注入区和所述漏区都通过接触孔连接到由正面金属层组成的漏极。
13.如权利要求1所述的LDMOS器件，其特征在于：所述多晶硅栅的顶部通过接触孔连接到由正面金属层组成的栅极。
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